AN3962, PCB Layout Design for Analog Applications
AN3962, PCB Layout Design for Analog Applications
AN3962, PCB Layout Design for Analog Applications
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Power Ground Separation (Noise Isolation)<br />
Current Flow at Boost Topology<br />
IL<br />
Rr1 Rr2<br />
IL x Rr1<br />
A<br />
IL x Rr1<br />
Isw x R sw<br />
B<br />
Figure 4. Ground Noise Expression<br />
As shown in Figure 4, each ground connection point A, B, and C will have a different voltage ripple, which will be<br />
reflected to the connected <strong>Analog</strong> block. This may cause unwanted per<strong>for</strong>mance issues.<br />
The connection point of power ground and analog ground should be carefully managed, to avoid this problem when<br />
doing the layout. The rule of thumb is to connect these two grounds prior to the input capacitor, and close to the input<br />
connector or input voltage supply. By doing this, two main benefits can be expected: the common impedance is<br />
reduced, and the switching ripple (or noise) will be filtered by the capacitor.<br />
<strong>PCB</strong> <strong>Layout</strong> <strong>Design</strong> Guide <strong>for</strong> <strong>Analog</strong> <strong>Applications</strong>, Rev. 2.0<br />
12 Freescale Semiconductor<br />
RSW<br />
<strong>Analog</strong> Block<br />
C<br />
Id<br />
IL x Rr1<br />
Id x Rr2
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