Decorated Operations for QorIQ P3/P4/P5 Processors - Freescale ...

Silicon Implementation of Decorated Operations
case where seven cores tried to update the same shared variable multiple times and hence also had to wait
for the lock to be freed, the update took on average 95 times longer than the private variable. See Section 3,
“Using Decorations in Software and Performance Results,” for urther details on the benchmark.
Freescale’s implementation of decorated operations goes back to the initial, most basic problem, namely,
how to share data in a multicore environment. Freescale’s decorated operations solve this problem by
means that do not introduce sequential code and have a low software overhead and complexity. This is
done by using other parts of the SoC besides the cores to perform relative operations on data, such as
“increase x by 10.” By moving the operation out from the core into a central location, it is possible to
guarantee atomic operations and simpler inter-core order of execution.
We will discuss how Decorated Operations are implemented in Freescale’s high-end QorIQ processor
family with the P3, P4 and P5 devices and how these operations can be made use of by software in order
to reach performance numbers that are equal to operations on private variables. Use-cases and examples
will mainly be taken from the P4080 but is generally applicable for all the P3, P4 and P5 devices.
2 Silicon Implementation of Decorated Operations
Decorated operations, or decorated storage, as it is also commonly named, is a set of core instructions
added to the Power Architecture instruction set [6]. The instructions are “decorated” with a computation
and attribute to the common load/store instruction. For example, the stbx (Store Byte Indexed) now also
has a decorated version: stbdx (Store Byte Decorated Indexed). This is also applied to half-word, word,
double-word, and double-float versions of the store as well as load instructions (that is, stbdx, sthdx,
stwdx, stddx 1 , and stfddx, and lbdx, lhdx, lwdx, lddx 2 , and lfddx). An additional dsn (Notify) instruction
has also been added that does not have any corresponding load/store version, but is interpreted as a nop
(No Operation by the core) and carries a decoration.
This decoration does not have any direct meaning to the core itself, but depending on the SoC
implementation, it is interpreted by other parts of the device. In the case of Freescale’s QorIQ processor
family, these decorations are interpreted by the CPC, which carries out the operations together with the
CoreNet DDR queue and DDR controller (see Figure 3). These act similarly to transactional memory [7]
to perform operations on a global scale outside the cores. Unlike transactional memory, there is no need to
handle rollbacks, because CoreNet buffer transactions are required and ensure the correct order of
execution. The decorations for load instructions include clear, set, decrement, and increment of data. Store
instructions include accumulate (could be negative), combined increment and accumulate, maximum
threshold, and minimum threshold. The notify instruction can carry increment as well as clear operations.
Versions are available for signed and unsigned data, but also 32- and 64-bit-word lengths.
1. Declared with “volatile” to ensure that no unfair compiler optimizations were used, and that a full read-update-write cycle was
executed.
2. Not implemented on P3/P4, but available on P5.
Decorated Operations for QorIQ P3/P4/P5 Processors, Rev. A
4 Freescale Confidential Proprietary Freescale Semiconductor
Preliminary—Subject to Change Without Notice