Decorated Operations for QorIQ P3/P4/P5 Processors - Freescale ...

Implementation Details
Addresses to which decorated loads are performed should be marked Guarded 1 , that is, there is no
speculative execution allowed for those instructions. If guarded is not set, then speculative execution, for
example, of a load operation triggers data updated. This is not problematic if the speculation turns out to
be correct. However, if it is not, the case and the load are thrown out from the core pipeline, but the
decoration is still executed in the memory subsystem. This in turn results in an incorrect value of the data.
Variables (that is, accumulators) affected by decorated operations should be naturally aligned to their
variable size (for example, word should be 4-byte-aligned). An error here can result in incorrect data
changes, both to the variable operated on and adjacent data.
Decorated load, store, and notify operations behave the same as normal load and store operations in all
other aspects, such as Access control, Debug event, Storage attributes, and Alignment and memory access
ordering. In other words, there is no difference between decorated operations and normal operations when
it comes to application usage. Any application can use them without any OS kernel or Hypervisor
interaction or permission.
4.1 Load—Memory Loaded to Core Register with Decoration Result
For decorated load operations, the processor performs a load operation with the specified decoration to the
given address and places the data provided by the device in the target register. The different operations are
as follows:
8-/16-/32-/64-bit Clear
8-/16-/32-/64-bit Set
8-/16-/32-/64-bit Decrement
8-/16-/32-/64-bit Increment
4.2 Store—Core Register Stored in Memory with Result from
Decoration
For decorated store operations, the processor performs a store operation with the specified decoration to
the given address and provides the data specified in the source register to the device. The different
operations are as follows:
32-/64-bit accumulate
32-/64-bit increment and 32/64-bit accumulate
64-bit maximum threshold with unsigned double word
32-bit maximum threshold with unsigned word
64-bit minimum threshold with unsigned double word
32-bit minimum threshold with unsigned word
1. Guarded: All loads and stores to this page are performed without speculation. That is, they are known to be required.
Decorated Operations for QorIQ P3/P4/P5 Processors, Rev. A
8 Freescale Confidential Proprietary Freescale Semiconductor
Preliminary—Subject to Change Without Notice