Full-Chip Verification for Mboa-compliant UWB Radio

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UWB Receiver Co-Simulation Results � Transient Co-Simulation of UWB Receiver � Baseband and RF waveforms � UWB OFDM Frame � Transient and Spectral display � Demodulated symbol Constellation
IFFT FFTL=128 FFT FFTL=128 I Q M=4 RITOC R I BSRC RANDOM NB=112*2*symbols/2.5 BR=data_rate*2 SEED=1 SP tx_freq BMEN 0110/6 NB=2 CMUX TYPE=0 NS1=1 NS2=56 CCONST REAL_CONST=0V IMAG_CONST=0V NSAMP=symbols SAMPLE_RATE=data_rate CDMUX TYPE=0 NS1=56 NS2=56 CMUX TYPE=0 NS1=15 NS2=56 CCONST REAL_CONST=0V IMAG_CONST=0V NSAMP=15*symbols SAMPLE_RATE=data_rate CMUX TYPE=0 NS1=57 NS2=71 SP tx_time SP rx_freq SP tx_bits CSCALE GAIN=1/sqrt(2) CMUX TYPE=0 NS1=32 NS2=128 CMUX TYPE=0 NS1=160 NS2=5 CCONST REAL_CONST=0V IMAG_CONST=0V NSAMP=32*symbols SAMPLE_RATE=data_rate CCONST REAL_CONST=0V IMAG_CONST=0V NSAMP=5*symbols SAMPLE_RATE=data_rate CDMUX TYPE=0 NS1=32 NS2=133 SP rx_time SINK CDMUX TYPE=0 NS1=128 NS2=5 SINK CDMUX TYPE=0 NS1=57 NS2=71 CDMUX TYPE=0 NS1=1 NS2=56 CDMUX TYPE=0 NS1=15 NS2=56 SINK SINK CMUX TYPE=0 NS1=56 NS2=56 I Q M=4 CTORI R I MBEN 6/0110 NB=2 CSCALE GAIN=sqrt(2) SP rx_bits BERP EVMP I Q I ref ref Q EVM CTORI R I CTORI R I RITOC R I SINK SRDC DF=40 SP bbrx CTORI R I SP bbtx DAC U1 DAC2 papr=9 expand=40 fcutoff=256MHz flength=1024 fbeta=0.02 CDMUX NS1=time_sync_drop NS2=2^20 CSCALE MIXER3P IN OUT LO MIXER3P IN OUT LO SP timing_recov_rx rx_in rx_out_I rx_out_Q U2 UWB_Rx Vsupply=1.2 LNA_PD=0 Balun_PD=0 RxMx_PD=0 LNA_LG=0 flo=4g rxlo_amp=800m txrx=0 RxBB_PD=0 Vctrl1=-0.145 Vctrl2=-0.11 VcmOut=0.68 Ibias_lna=0 Ibias_mx=0 40 AMP MS21=15 SP mod_out S x ( ) f x final_tx FFTL=8192*2 TYPE=1 WINDOW_TYPE=1 INITSAMP=0 MNCH Hata SP rx_rfin Vector Signal Generator Vector Signal Analyzer Receiver Chip 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx_in rx_out_I rx_out_Q V2776 V2777 V2778 V2779 V2780 V2781 V2782 I2783 I2784 I2785 0.6n L2786 0.6n L2787 0.6n L2788 0.4n L2789 0.4n L2790 1.2n L2791 1.2n L2792 0.02 R2793 0.02 R2794 0.02 R2795 0.01 R2796 0.01 R2797 0.2 R2798 0.2 R2799 0.2n L2800 10k R2801 1e-012 C2802 10k R2803 1e-012 C2804 V E2806 V E2808 V2809 V2810 E2811 E2812 V2813 V2814 V2815 E2816 E2817 V2818 V2819 3.5n L2820 0.2 R2821 100p C2822 0.2 R2823 0.15n L2824 1.2n L2825 1.2n L2826 1.2n L2827 1.2n L2828 1.2n L2829 1.2n L2830 V2831 V2832 V2833 V2834 V2835 V2836 V2837 A UMC 0.13um 1.2V/3.3V Twin, Tripple Well Mixed_Mode mos_corner=tt res_case=res_typ UMC 0.13um 1.2V/3.3V Twin, Tripple Well RFCMOS coremos_corner=tt iomos_corner=tt cirspl_case=typ sqskspl_case=typ mimcap_case=typ varmis12_case=typ varmis33_case=typ vardio_case=typ npn_vn_case=typ rnhr_case=typ pnp_vn_case=typ rnnpo_case=typ rnppo_case=typ npn_vs_case=typ diodn_esd_case=typ diop_esd_case=typ pad_rf_case=typ UMC 0.13um 1.2V/3.3V Twin, Tripple Well Mixed_Mode mos_corner=tt V V V V V 0.6n L2847 V V V V V2852 V2853 V2854 V2855 V2856 E2857 E2858 E2859 E2860 1p C2861 1p C2862 1p C2863 1p C2864 200 R2865 200 R2866 200 R2867 200 R2868 V2869 S error=1 ANT LNA_PD LNA_GND LNA_GND1 LNA_GC LNA_VDD LNA_Ibias Tx RxTx TRsw_GND1 TRsw_GND2TRsw_GND3 TRsw_VDD1 TRsw_VDD2 Balun_GND Balun_VDD Balun_PD Ibias_mxi Ibias_mxq RxMx_VDD RxMx_PD LOi LOib LOq LOqb RxMx_GND BB_AVDD LPF_Tun BB_Ibias VoutI VoutIn VoutQ VoutQn Vctrl_2n Vctrl_2p Vctrl_1n Vctrl_1p BB_AGND U6 RX_TOP -0.145(min gain)
Page 1 and 2: Full-chip Verification for MBOA-com
Page 3 and 4: UMC - Ansoft UWB Project � Circui
Page 5 and 6: Circuit Modification Summary* � T
Page 7 and 8: index=8 l=80.8u w=74.2u c_pad=38.6f
Page 9 and 10: Layout for UWB T/R Switch
Page 11 and 12: � UMC and Ansoft provide referenc
Page 13 and 14: RFIC Design Challenges � Time- an
Page 15 and 16: Monolithic ICs are Produced Using C
Page 17 and 18: HFSS - 3D Electromagnetics Industry
Page 19 and 20: System Design and Behavioral Modeli
Page 21 and 22: � Spiral Design Kit Contents: Ans
Page 23 and 24: HFSS/Nexxim Dynamic Link
Page 25 and 26: UMC 0.13um 1.2V/3.3V Twin, Tripple
Page 27 and 28: UMC 0.13um 1.2V/3.3V Twin, Tripple
Page 29 and 30: VCO Circuit Using HFSS Post-Layout
Page 31 and 32: Enlarge the Size of Negative Genera
Page 33 and 34: Exposed Die Paddle Die Vias Package
Page 35: BSRC RANDOM NB=112*2*symbols/2.5 BR
Page 39: Conclusion � UMC and Ansoft teame
Page 42 and 43: Previous Work for UWB T/R Switch
Page 44 and 45: sw=0, Receiving UWB T/R Switch from
Page 46 and 47: Modifications for UWB T/R Switch
Page 48 and 49: sw=0, Receiving Final Result for UW
Page 50 and 51: Modification Summary for T/R Switch
Page 52 and 53: Previous Work for UWB LNA
Page 54 and 55: UWB LNA from Previous Work
Page 56 and 57: Modifications for UWB LNA_v1
Page 58 and 59: Final Result for UWB LNA_v1 FF, 1.3
Page 60 and 61: Modification Summary for LNA_v1 �
Page 62 and 63: Addition for UWB Active Balun (no p
Page 64 and 65: Broadband Active Balun Added Phase
Page 66 and 67: Previous work & Modifications for U
Page 68 and 69: IQ Modulator Refinement vdd_mix gnd
Page 70 and 71: Modification Summary for IQ Modulat
Page 72 and 73: Original work of UWB Synthesizer
Page 74 and 75: Complex Signal Spectrum for Synthes
Page 76 and 77: Complex Signal Spectrum for Synthes
Page 78 and 79: Synthesizer Settling
Page 80 and 81: Spectrum Directly from Nexxim Ch2
Page 82 and 83: Modifications for UWB Synthesizer
Page 84 and 85: Synthesizer Schematic
Page 86 and 87:
UMC TT Ch2 Spectrum
Page 88 and 89:
Simulation Results TT: MOS=tt, res=
Page 90 and 91:
Layout for Synthesizer
Page 92 and 93:
0 V240 0 0 0 0 0 0 in inb U MC 0.13
Page 94 and 95:
CMOS Analog Baseband Filter & AGC F
Page 96 and 97:
HPF, LPF and VGA I & Q Stages UWB A
Page 98 and 99:
Gm Cell used in UWB Analog BB LPF f
Page 100 and 101:
UWB Analog BB filter (HPF portion)
Page 102 and 103:
PD GND VDD INV VSS U276 INV8 A Y VD
Page 104 and 105:
Common Mode Aux. Amplifier GND VDD
Page 106 and 107:
Section 3: Results Analog Baseband
Page 108 and 109:
Page 110 and 111:
Page 112:
Layout for Analog Gm-C Filter
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Full-Chip Verification for Mboa-compliant UWB Radio

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