Full-Chip Verification for Mboa-compliant UWB Radio

Full-chip Verification for MBOA-compliant 

UWB Radio 

Dr. Lawrence Williams 

Director of Business Development

Ansoft’s UWB Radio From 2004 

� Last Year 

� System and Circuit design for a UWB radio based on the 

Multiband OFDM Alliance (MBOA) Specification 

� This Year 

� Accomplished: Production-ready UWB Circuits With Layout 

� Resulted in: A New Design Flow for RFIC

UMC - Ansoft UWB Project 

� Circuit and System Design of a 

“Mode 1” radio that supports the 

MBOA proposal. 

� Direct conversion architecture 

� All circuits implemented in UMC 

0.13 um process – Nexxim 

design kit available. 

� Ansoft Designs Circuits; UMC 

Performs Layout and Fabrication

Last Year 

� Last year we presented initial circuit designs and simulation 

results for T/R Switch, LNA, Synthesizer, I/Q Mod/Demod, 

and Power Amplifier

Circuit Modification Summary* 

� T/R Switch - Slight changes to compensate for package 

parasitics and new LNA match. 

� LNA - Changed from a single ended design to a pseudodifferential 

design so that LNA is less sensitive to package 

parasitics and less likely to oscillate. 

� Synthesizer - A fixed frequency filter and tracking filter added 

at output of the 1st and 2nd complex mixer for better spur 

rejection; added real striped-band switching VCO 

� I/Q demod - No change, aside from some minor biasing 

changes. 

� Baseband signal conditioning - Re-designed for bandwidth 

enhancements and more aggressive low pass filtering. 

*See appendix for full details

Today 

� Complete, production-ready circuits with layout that take into 

account packaging, on-chip passive parasitics, and actual 

implementation of sources (VCO), bias, etc.

index=8 

l=80.8u 

w=74.2u 

c_pad=38.6f 

UMC 0.13um 1.2V/3.3V 

Twin, Tripple Well RFCMOS 

NMOS 

PMOS 

STI 

STI 

STI 

p-type 

coremos_corner=tt 

iomos_corner=tt 

cirspl_case=typ 

sqskspl_case=typ 

mimcap_case=typ 

varmis12_case=typ 


vardio_case=typ 

npn_vn_case=typ 

npn_vs_case=typ 

pnp_vn_case=typ 

rnhr_case=typ 

rnnpo_case=typ 

rnppo_case=typ 

diodn_esd_case=typ 

diop_esd_case=typ 

pad_rf_case=typ 

gnd_sw 

ps_filt 

vdd_sw 

gnd_sw 

gnd_sw 

do=136.01u 

w=6u 

s=1.8u 

nt=4.5 

mimcaps_rf 

c_tot_m=0.508p 

l=21.68u 

w=21.68u 

M=1 

vdd_sw 

0 

V53 

vdd_sw 

l_cr20k_rf 

p_ls=2.3n 

gnd_sw 

DC=1.2 

vdd_sw 

gnd_sw 

gnd_sw 

0 

gnd_sw 

V58 

DC=0 

mimcaps_rf 


l=20.27u 

w=20.27u 

M=1 

vdd_sw 

Port3 

nt=6.5 

s=1.8u 

w=1.9u 

do=149.12u 

gnd_sw 

gnd_sw 

U1 

TRswitch3 

rx 

ps_filt 

tx 

vdd_sw 

ctrl 

gnd_sw 

0 

gnd_sw 

V50 

Port1 

Port2 

DC=if(sw==1, 1.2, 0) 

Original Circuit 

p_ls=7.9n 

l_cr20k_rf 

n_bpw_12_rf 

lf=0.12u 

wf=1.8u 

nf=16 

M=3 

wt=28.8u 

rnhr_rf 

r_zbt=4.816k 

wt=28.8u 

M=3 

nf=16 

wf=1.8u 

lf=0.12u 

gnd_sw 

gnd_sw 

l=5u 

w=1u 

m=1 

l=5u 

w=1u 

vdd_sw 

m=1 

n_bpw_12_rf 

vdd_sw 

rnhr_rf 

r_zbt=4.816k 

gnd_sw 

gnd_sw 

vdd_sw 

UWB T/R Switch 

ctrl 

� Modifications: 

p_12_rf 

lf=0.12u 

wf=2.4u 

nf=16 

M=1 

wt=38.4u 

n_12_rf 

vdd_sw 

lf=0.12u 

wf=1.8u 

nf=16 

M=1 

wt=28.8u 

gnd_sw 

� Tuned circuit to improve input match and 

insertion loss on receive channel with slight 

sacrifice of transmit characteristics. 

� Eliminated the one of inductors in the 

matching circuit 

� Reducing the size of the T/R switch. 

� Improved the receiving characteristics. 

gnd_sw 

Inductor removed 

to reduce layout 

size 

rnhr_rf 

r_zbt=20.636k 

rnhr_rf 

r_zbt=20.636k 

l=20u 

w=1u 

l=20u 

w=1u 

tx 

rx 

vdd_sw 

m=1 

vdd_sw 

m=1 

gnd_sw 

gnd_sw 

index=8 

l=80.8u 

w=74.2u 

c_pad=38.6f 

gnd_sw 

ps_f ilt 

vdd_sw 

gnd_sw 

mimcaps_rf 


l=c1_len 

w=c1_len 

M=1 

gnd_sw 

do=Ls_do 

w=Ls_w 

s=Ls_s 

nt=Ls_nt 

vdd_sw 

l_cr20k_rf 

p_ls=1.8n 

gnd_sw 

vdd_sw 

gnd_sw 

gnd_sw 

Modified Circuit 

mimcaps_rf 


l=c2_len 

w=c2_len 

M=1 

vdd_sw 

gnd_sw 

gnd_sw 

n_bpw_12_rf 

lf =0.12u 

wf =7.2u 

nf =16 

M=1 

wt=115.2u 

wt=86.4u 

M=1 

nf=16 

wf=5.4u 

lf=0.12u 

gnd_sw 

rnhr_rf 

r_zbt=4.816k 

gnd_sw 

l=5u 

w=1u 

m=1 

l=5u 

w=1u 

vdd_sw 

m=1 

n_bpw_12_rf 

vdd_sw 

rnhr_rf 

r_zbt=4.816k 

gnd_sw 

gnd_sw 

vdd_sw 

ctrl 

p_12_rf 

lf =0.12u 

wf =2.4u 

nf =16 

M=1 

wt=38.4u 

n_12_rf 

vdd_sw 

lf =0.12u 

wf =1.8u 

nf =16 

M=1 

wt=28.8u 

gnd_sw 

Refernce: TALWALKAR et al.: Integrated CMOS Transmit-Receive Switch Using LC-Tuned 

Substrate Bias for 2.4-GHz and 5.2 GHz Applications, IEEE JOURNAL OF SOLID-STATE 

CIRCUITS, VOL. 39, NO. 6, JUNE 2004 

gnd_sw 

rnhr_rf 

r_zbt=20.636k 

rnhr_rf 

r_zbt=20.636k 

l=20u 

w=1u 

l=20u 

w=1u 

tx 

rx 

vdd_sw 

m=1 

gnd_sw 

vdd_sw 

m=1 

gnd_sw

sw=0, Receiving 

sw=1, Transmitting 

Simulation Results 

Original Circuit Modified Circuit 


sw=1, Transmitting

Layout for UWB T/R Switch

Schedule 

� All circuit design is complete � 

� All circuit layout is complete � 

� Mask set complete and sent on July shuttle � 

� Shuttle returns mid-October, stay tuned for measured results! 

vdd_bln 

nt=5.5 

s=2u 

w=1.5u 

do=100u 

gnd_bln 

gnd_bln lf=0.12u 

wf=1.8u 

nf=4 

M=1 

wt=7.2u 

gnd_bln 

vdd_bln 

p_ls=3.43n 

l_cr20k_rf 

gnd_bln 

n_12_rf 

n_12_rf 

v_div2 

lf=0.12u 

wf=1.8u 

nf=8 

M=1 

wt=14.4u 

v_div1 

vdd_bln 

gnd_bln 

vdd_bln 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

vdd_bln 

gnd_bln 

vdd_bln 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

gnd_bln 

M=1 

w=100u 

l=100u 

gnd_bln 

gnd_bln 

vdd_bln 

l_cr20k_rf 

vg_cs p_ls=1.02n 

vg_cs 

do=120u 

w=5u 

s=2u 

nt=2.5 

vg1_cg 

c_tot_m=10.174p 

mimcaps_rf 

gnd_bln 

vdd_bln 

M=1 

w=100u 

l=100u 

gnd_bln 

vg2_cg 

l=74.8u 

w=48.5u 

M=1 

c_tot_m=10.174p 

mimcaps_rf 

gnd_bln 

vdd_bln 

mimcaps_rf 


gnd_bln 

vdd_bln vdd_bln 

vdd_bln vdd_bln vdd_bln 

vdd_bln 

gnd_bln 

vdd_bln 

m=3 

w=2u 

l=5u 

n_bpw_12_rf 

lf=0.12u 

wf=wf2_cg 

nf=nf2_cg 

M=m2_cg 

wt=115.2u 

n_bpw_12_rf 

lf=0.12u 

wf=wf1_cg 

nf=nf1_cg 

M=m1_cg 

wt=115.2u 

m=3 

w=2u 

l=6.9u 

gnd_bln 

r_zbt_m=0.104k 

rnnpo_rf 

l=100u 

w=100u 

vdd_bln M=1 


rnnpo_rf 

gnd_bln 

vdd_bln 

gnd_bln 

mimcaps_rf 

c_tot_m=10.174p out 

mimcaps_rf 

c_tot_m=10.174p outb 

gnd_bln 

gnd_bln gnd_bln 

vdd_bln 

m=3 

w=2u 

l=5u 

n_bpw_12_rf 

lf=0.12u 

wf=7.2u 

nf=10 

M=1 

wt=72u 

m=3 

w=2u 

l=7u 

gnd_bln 


rnnpo_rf 


rnnpo_rf 

l=100u 

w=100u 

M=1 

vdd_bln 

gnd_bln 

vdd_bln 

M=2 

w=71u 

l=79u 

gnd_bln 


gnd_bln 


mimcaps_rf

� UMC and Ansoft provide 

reference flow for RFIC 

� Cadence RFIC Flow 

� Nexxim Circuit Simulation 

� HFSS EM Extraction 

� Benefits 

Design Flow for RFIC 

� Adds Harmonic Balance + 

Transient 

� Robust S-parameter model 

support 

� High Capacity and Advanced 

Numerical Algorithms 

� Time and Frequency Domain 

consistency 

� Full electromagnetic accuracy of 

on chip passives and parasitics 

(using HFSS)

Market Trends 

� Convergence of 3G cellular, TV, digital 

camera, gaming, and mobile music in a 

single handheld 

� Devices With More Si, Digital + 

Analog/RF 

� Low power consumption for portability 

� Multiple Radios in Single Platform 

� Cellular, Bluetooth, UWB 

� Portable Devices With Rich Digital 

Content and High-performance Analog 

Processing and I/O 

� GHz Frequencies

RFIC Design Challenges 

� Time- and Frequency-Domain 

� VCO, PLL, mixers, filters, amplifiers, AGC loop, DAC, ADC 

� Verification Coverage 

� Full transceiver chain simulation often exceeds limits of traditional EDA 

tools 

� Forces compromise on the breadth of verification simulations due to long 

simulation run time and short design schedules 

� Accuracy and capacity required for sensitive analog simulation 

� Parasitics and Packaging 

� Modern signaling methods like OFDM and fast frequency hopping 

require circuits that perform at high frequency with high switching speed 

� Extremely sensitive to active and passive device models, distributed 

layout parasitics, substrate coupling effects, inter-stage impedances, IC 

packaging, and power supply noise.

“Best in Class Technology 

in 

Established Design Flows”

Monolithic ICs are Produced Using Cadence 

Best in Class Technology in Established Design Flows 

Cadence 

Schematic, 

Layout, & 

Simulation 

Nexxim HFSS 

Ansoft Customers can gain 

dramatic new benefits by adding 

Ansoft Technology to the 

Cadence design flow.

Nexxim 

� Analog and mixed-signal circuit simulator 

� Nexxim supports: 

� Transient 

� Harmonic Balance 

� DC and DC noise 

� Phase Noise and Noise Figure 

� LNA/DC small signal 

� Parameter Sweeps 

� HSPICE® and Spectre® compatible 

� 100% SPICE Simulation accuracy 

� Integration with Cadence and EM tools 

� Consistency of results across time and 

frequency domains 

dQ(t,x) 

dt 

� S-parameters and W-elements + F(t,x) = 0 

V 

rx_in 

UMC 0.13um 1.2V/3.3V 

Twin, Tripple Well Mixed_Mode 

mos_corner= tt 

UMC 0.13um 1.2V/3.3V 


0 

V2819 

R2823 

0 

0 

mos_corner= tt 

res_case=res_typ 

UMC 0.13um 1.2V/3.3V 

Twi n, Trippl e W el l RFCMOS 



cirspl _case= typ 









rnhr_case=typ S 

rnnpo_case=typ error=1 





1p 

C2861 

1p 

C2862 

V2854 V2855 V2852 

R2821 

L2820 

3.5n 

0.2 

V2836 

0.2 

0.15n 

L2824 

100p 

C2822 

L2847 

0.6n 

V2831 

C2863 

V2832 

1p 

0 

0 

V2833 

R2865 

200 

0 

I2783 I2785 

RxTx 

LNA_PD 

Balun_PD 

RxMx_PD 

V2835 

0 

V2837 

I2784 

V2834 

V 

V 

V V 

E2857 

R2866 

200 

R2867 

200 

E2858 

E2859 

0 

0 

0 

V2781 

V2777 V2779 

V2776 

0 

V2780 

V2778 

L2825 

1.2n 

L2826 

1.2n 

L2827 

1.2n 

L2828 

1.2n 

L2829 

1.2n 

L2830 

1.2n 

LNA_Ibias Ibias _mx q Ibias _mx i BB_Ibias 

TRsw _VD D1 TR sw _VDD 2 LNA_VDD Balun_VDDRxMx_VDD 

BB_AVD D LPF_Tun 

VoutI 

LNA_GC 

VoutIn 

ANT 

Tx LOq LOqb LOi LOib TRsw _GNDTRsw 1 _GN D2TRsw _GND 3LNA_GND 

LNA_GND1 Balun_GN DRxMx_GNDBB_AGN 

D Vc trl_1p Vc tr l_1 n Vc tr l_2p Vc tr l_2 n 

L2786 

0.6n 

L2787 

0.6n 

L2788 

0.6n 

L2789 

0.4n 

L2790 

0.4n 

L2791 

1.2n 

L2792 

1.2n 

R2793 

R2794 0.02 

R2795 0.02 

R2796 0.02 

R2797 0.01 

R2798 0.01 

R2799 0.2 

0.2 

E2860 

200 

R2868 

V2869 

1p 

C2864 

U6 

RX_TOP 

0.2n 

L2800 

0 

V2853 

0 

0 

A 

V2782 

E2811 E2812 

V2809 V2810 

V2813 

VoutQ 

VoutQn 

0 

V2856 

10k 

R2801 

10k 

R2803 

V 

C2802 

1e-012 

C2804 

1e-012 

E2806 

E2816 E2817 

0 

0 

0 

Q(tn+ 

1,xn+ 

1 ) − Q(tn 

,xn 

) 

+ F(tn+ 

1,xn+ 

1 ) = 0 

hn+ 

1 

Q(t , xˆ 

n+ 

1 ) − Q(tn 

,xn 

) 

G(tn+ , x) 

= 

+ F(tn 

h 

V2818 

V 

V2814 V2815 

0 

0 

V V 

V 

rx_out_I 

-0.145(min gain)

HFSS – 3D Electromagnetics Industry 

Standard 

� Full-wave 3D EM Simulation 

Software Based on Finite Elements 

� Computes Fields, S-parameters and 

Full-wave Spice Models 

� Applications 

� On-chip passives 

� Layout Extraction 

� Package Analysis 

� Features 

� Parametric Studies 

� Optimization 

� Links to Cadence and Nexxim 

Spiral Inductor 

Modeling 

Inductance[nH] 

20 

16 

12 

8 

4 

0 

-4 

-8 

-12 

IND605 comparison 

-16 

-12 

0 2 4 6 8 10 12 14 16 18 20 

Frequency[GHz] 

Layout Extraction 

Package Analysis 

IND605_m_L 

IND605_S_L 

IND605_m_Q 

IND605_5_Q 

15 

12 

9 

6 

3 

0 

-3 

-6 

-9 

Quality Factor

Nexxim Direct Cadence Link 

Cadence ADE Tool Select Launch Nexxim 

Spectre-RF 

Nexxim

System Design and 

Behavioral Modeling 

Testbench Development 

Circuit 

Specifications 

Circuit Design w/ 

Idealized Interconnect 

Time and Frequency 

Domain Circuit 

Simulation 

Layout 

Verification in 

System Bench 

Tapeout or 

Chip Integration... 

RFIC Design Flow 

Foundry 

Design Kit 

Electromagnetic 

Layout 

Extraction 

Design/Extraction of 

Critical On-Chip Passives 

Design/Extraction of 

Package Parasitics

Ansoft Tools in the RFIC Flow 

Design Flow 

System Design and 

Behavioral Modeling 

Schematic Entry and 

Design Environment 

Time and Frequency 

Domain Circuit Simulation 

Layout 

Electromagnetic 

Extraction 

Parasitic Extraction, 

DRC, and LVS 

Verification in 

System Bench 

Design Tools 

Ansoft Designer 

Matlab 

HDL 

Spreadsheet 

Cadence Virtuoso 

Schematic 

Ansoft Nexxim 

Cadence Spectre 

Cadence Ultra-sim 

Cadence Virtuoso-XL 

Cadence Encounter P&R 

Ansoft HFSS 

Ansoft Q3D 

Ansoft TPA 

Cadence Assura DRC/LVS 

Mentor Calibre DRC/LVS 

Ansoft Nexxim + Designer

� Spiral Design Kit Contents: 

Ansoft Spiral Design Kit 

� Parameterized HFSS Projects 

� Circular, stacked rectangular, transformer, symmetric spiral. 

� Software Installer 

� Installs custom UDPs and projects 

� Documentation 

Users can explore new spiral 

geometries and can examine higherorder 

effects of layout and proximity 

� Describes standard models and provides suggestions on how to modify for 

specific needs. 

Circular Stacked 

Transformer 

Symmetric 

Download Design Kit at: 

www.onchippassivesdesign.com


Courtesy of 

16 

13 

10 

7 

4 

1 

-2 

-5 

-8 

-11 

-14 

Do = 150um 

Ansoft HFSS - Accuracy 

IND602 real-comparison 

IND602_m_L 

IND602_S_L 

IND602_m_Q 

IND602_S_Q 

0 2 4 6 8 10 12 14 16 18 20 


Nt/Width/Spacing = 3.5/15um/2um 

16 

14 

12 

10 

8 

6 

4 

2 

0 

-2 

-4 

Quality Factor 


20 

16 

12 

8 

4 

0 

-4 

-8 

-12 

-16 

Do = 300um 

IND605 comparison 

0 2 4 6 8 10 12 14 16 18 20 


IND605_m_L 

IND605_S_L 

IND605_m_Q 

IND605_5_Q 

15 

12 

9 

6 

3 

0 

-3 

-6 

-9 

-12 

Quality Factor

HFSS/Nexxim Dynamic Link

Vertical MOM Capacitor 

� Metal-Oxide-Metal Capacitor has 

great application for RF Circuits 

and Data Converters 

� EM Design and extraction used to 

Support “Sharp VGA/ADC” 

design, first silicon success. 

� Now working on “Macroni’s 90nm 

ADC” design 

Cap=117.02 fF 

3207 2.4%

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 

UMC 0.13um 1.2V/3.3V 


0 

Frequency Domain 

mos_corner=tt 


UMC 0.13um 1.2V/3.3V 













rnhr_case=typ 






UWB Analog Baseband Simulation 

0 

0 

0 

V1776 

V1777 

V1957 

V 

V 

E1781 

E1782 

E1760 E1761 

V1758 V1759 

0 

0 

V1769 

0 

V1772 

U1 

BB1 

LPF_Vtun AVDD 

BBIp 

BBIn 

BBqp 

AGND 

0 

0 

0 

R1745 

R1747 

0 

10k 

10k 

V 

C1746 

C1748 

E1765 E1766 

1e-012 

1e-012 

V1763 V1764 

V 

E1750 

0 

V V 

-0.145(min gain)

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 


UMC 0.13um 1.2V/3.3V 













rnhr_case=typ 






UWB Analog Baseband Simulation 

Time Domain 

0 

0 

0 

V1776 

V1777 

V1957 

V 

V 

E1781 

E1782 

E1760 E1761 

V1758 V1759 

0 

V1769 

0 

V1772 

0 

U1 

BB1 

LPF_Vtun AVDD 

BBIp 

BBIn 

BBqp 

AGND 

0 

0 

0 

Overdriven (Clipped) Output 

0 

0 

R1745 

R1747 

10k 

10k 

V 

C1746 

C1748 

E1765 E1766 

1e-012 

1e-012 

V1763 V1764 

V 

E1750 

0 

V V 

-0.145(min gain)

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 


UMC 0.13um 1.2V/3.3V 













rnhr_case=typ 






V 

PNUM=1 

RZ=50Ohm 

IZ=0Ohm 

UWB Top Level (Full RX) Simulation 

High Capacity 

V1200 

0 

R1205 

0.2 

R1211 

V1251 

0.2 

V1231 

0.15n 

L1214 

C1208 

L1690 

0.6n 

V1232 

0 

L1204 

100p 

3.5n 

V1233 

LNA_Ibias Ibias_mxq Ibias_mxi BB_Ibias 

TRsw_VDD1 TRsw_VDD2 

LNA_VDD Balun_VDD RxMx_VDD 

BB_AVDD 

LNA_GC 

ANT 

RxTx 

LNA_PD 

Balun_PD 

RxMx_PD 

I1143 

I1144 

I1145 

Tx LOq LOqb LOi LOib TRsw_GND1TRsw_GND2TRsw_GND3 LNA_GND LNA_GND1 Balun_GND RxMx_GND BB_AGND Vctrl_1p Vctrl_1n Vctrl_2p Vctrl_2n 

V1234 

V 

V1236 

V 

V1587 

V 

V 

0 

V1136 

V1137 

V1138 

0 

V1139 

L1222 

1.2n 

L1223 

1.2n 

L1224 

1.2n 

L1225 

1.2n 

L1226 

1.2n 

L1227 

1.2n 

V1140 

V1141 

L1147 

1.2n 

L1148 

1.2n 

L1149 

1.2n 

L1150 

1.2n 

L1151 

1.2n 

L1152 

1.2n 

L1153 

1.2n 

L1154 

1.2n 

U1 

RxTop 

R1155 

R11560.2 

R11570.2 

R11580.2 

R11590.2 

R11600.2 

R11610.2 

R11620.2 

0.2 

V1723 V1724 V1717 V1720 

0.2n 

L1165 

BRD_GND 

0 

A 

0 

LPF_Tun 

V1142 

VoutI 

VoutIn 

VoutQ 

VoutQn 

E1189 E1190 

V1187 V1188 

-0.145(min gain)

vdd_vco 

p_12_rf 

VCO Circuit With Block-level Layout 

Extraction 

vdd_vco 

gnd_vco 

vdd_vco 

lf=0.12u 

wf=2.4u 

nf=28 

M=1 

wt=67.2u 

vdd_vco 

vdd_vco 

1 

ref 

2 

vdd_vco 

vdd_vco 

lf=0.12u 

wf=2.4u 

nf=28 gnd_vco 

M=1 

wt=67.2u vdd_vco 

vdd_vco 

mimcaps_rf 

out_l c_tot_m=5.09p 

rnhr_rf 

r_zbt_m=20.003k 

mimcaps_rf 


gnd_vco l_cr20k_rf 

p_ls=1.15n 

mimcaps_rf 


rnhr_rf 

r_zbt_m=20.003k 

mimcaps_rf 

c_tot_m=5.09p out_r 

w=70.48u 

l=70.48u 

M=1 

gnd_vco 

gnd_vco 

l=19.4u 

w=1u 

m=1 

w=30u 

l=30u 

M=1 

gnd_vco 

do=150u 

w=8u 

s=1.8u 

nt=2.5 

gnd_vco 

l=30u 

w=30u 

M=1 

gnd_vco 

l=19.4u 

w=1u 

l=70.48u 

w=70.48u 

m=1 

M=1 

gnd_vco 

gnd_vco 

n_12_rf 

lf=0.12u 

wf=1.8u 

nf=14 

M=1 

wt=25.2u 

gnd_vco 

VCO Schematic VCO Layout 

l=0.15u 

w=5u 

nf=8 

m=1 

l=0.15u 

w=5u 

nf=8 

m=1 

gnd_vco gnd_vco 

vdd_vco 

mimcaps_rf 


l=24u 

w=24u 

M=1 

gnd_vco 

U16 

mos_var_array4 

n_12_rf 

n_12_rf 

1 2 

3 

gnd_vco lf=0.12u 

wf=1.8u 

nf=16 

M=1 

wt=28.8u 

ref 

lf=0.12u 

wf=1.8u gnd_vco 

nf=16 

M=1 

wt=28.8u 

0 

bias_isrc 

vdd_vco 

p_12_rf 

gnd_vco 

gnd_vco 

tst_port 

vdd_vco 

p_12_rf 


vdd_vco 

lf=0.12u 

lf=0.12u 

wf=2.4u 

wf=2.4u 

gnd_vco nf=32 

nf=32 

M=1 

M=1 


wt=76.8u 

wt=76.8u 

varmis_12_rf 

cox_m=64.1f 

n_12_rf 

lf=0.35u 

wf=2.4u 

nf=12 

M=1 

wt=28.8u 

varmis_12_rf 

cox_m=64.1f 

vminus vplus 

vtune_in0 

M=1 

w=30u 

l=30u 

vtune_in1 


mimcaps_rf 

vtune_in2 

vtune_in3 

vtune_in4 

vtune_in5 

vtune_in6 

M=1 

w=99.7u 

l=99.7u 

vtune_in7 

c_tot_m=10.114p 

mimcaps_rf 

M=1 

w=30u 

l=30u 


mimcaps_rf 

vdd_vco 

rnnpo_rf 


l=10u 

w=1u 

m=1 

gnd_vco 

vdd_vco 

p_12_rf 

n_12_rf 

vdd_vco 

lf=0.12u 

wf=1.8u 

nf=14 

M=1 

wt=25.2u 

gnd_vco 

M=1 

w=30u 

l=30u 


mimcaps_rf 

gnd_vco 

vctrl 

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

VCO Circuit Using 

HFSS Post-Layout Extraction 

142 Ports 

6 Adaptive Passes 

301,556 Tetrahedra 

Interpolating Freq. Sweep 

2.15 Gbyte RAM 

9 Hours 21 Minutes 

Dual Processor PC

� Before Extraction 

� Resonates @ 4.4GHz 

� Sources energy 

� S11 > 0dB 

� After Extraction 

� No longer resonates 

� S11 < 0dB 

Small Signal Test for VCO 

Oscillator negative 

resistance generator 

S 11 must be greater 

than 0dB for 

oscillation—circuit 

with full extraction 

fails to oscillate!

Enlarge the Size of Negative Generator to Recover Oscillation 

n_12_rf 

n_12_rf 

1 2 M0_G 

3 

M1_G 

gnd_vco lf=0.12u 

wf=1.8u 

nf=16 ref 

lf=0.12u 

wf=1.8u 

nf=16 

gnd_vco 

M=1 

wt=28.8u 

M=1 

wt=28.8u 

0 

bias_isrc 

vdd_vco 

M0_D M1_D 

M0_S 

M8_d 

M1_S 

gnd_vco 

Original Circuit 

M=1 

w=30u 

l=30u 

2.7um 

gnd_vco 


mimcaps_rf 

n_12_rf 

R613 

lf=0.35u 

wf=2.4u 

nf=12 

M=1 

w t=28.8u 

tst_port 

0.001 

vdd_vco 

M=1 

w=99.7u 

l=99.7u 

C25_PLUS 


c_tot_m=10.114p 

mimcaps_rf 

vdd_vco 

mimcaps_rf 

_tot_m=0.952p 

New Circuit With Larger Active Devices 

p_12_rf 

vdd_vco 

p_12_rf 

lf=0.12u 

lf=0.12u 

wf=2.4u 

wf=2.4u 

gnd_vco nf=32 

nf=32 

gnd_vco 

M=1 

M=1 

wt=76.8u 

wt=76.8u 

R616 

M2_S M3_S 

M2_B M2_G 

M3_G 

M3_B 

0.001 

3.6um 

M2_D M3_D 

vdd_vco 

M=1 

w=30u 

l=30u 

vdd_vco vdd_vco 

gnd_vco 

l_cr20k_rf 

mimcaps_rf 

p_ls=1.15n 


C3_MINUS C4_MINUS 

C4 

V582 

R619 

0.001

Enlarge the Size of Negative Generator to Recover Oscillation 

Oscillation is 

recovered using 

larger active 

devices.

Exposed Die 

Paddle 

Die 

Vias 

Package Effects on Receiver 

Port2 

Port4 

Ports 

Port1 

Port3 

Gold Wire 

Cu Leadframe 

Input Return Loss (S11) 

Blue: No Ground/Supply Inductance 

Red: TRswitch Ground/Supply Inductance 

Added 

Green: TRswitch & LNA Ground/Supply 

Inductance Added 

Instability caused mainly by ground 

inductance. 

ANT 


U37 

TRswitch 

AVDD1 AVDD2 

Rx 

ANT 

Tx 

RxTx 

AGND1 AGND2 AGND3 

TRsw_GND1 

TRsw_GND2 

TRsw_GND3 

RxTx 

Tx 

V 

LNA_PD 

LNA_GND 

LNA_GND1 

LNA_Ibias 

RFin LNA 

PD 

AGND 

LNA_GC 

LNA_VDD 

U2 

LNA 

Ibias AVDD 

GC AGND1 

RFout 

V 

RFin 

Balun_PD 

Balun_VDD 

AVDD 

U53 

ActBal 

RFout 

RFoutn 

PD AGND 

Balun_GND 

V 

V 

0 0 

Ibias_mxi Ibias_mxq RxMx_VDD 

RxMx_PD 

U166 

RxMx 

Ibias_mxi Ibias_mxq AVDD 

PD 

LOi 

E1648 

RF 

RFN 

LOi LOib LOq LOqb 

LOib 

LOq 

LOqb 

V 

AGND 

IFi 

IFin 

IFq 

IFqn 

RxMx_GND 

LPF_Tun BB_AVDD BB_Ibias 

LPF_Vtun AVDD 

BBIp 

BBIn 

BBqp 

BBqn 

E1657 

Vctrl_1p Vctrl_1n 

U85 

AGND 

GNDdump 

Vctrl_1p Vctrl_1n Vctrl_2p Vctrl_2n 

V 

HFSS Model UWB T/R Switch + LNA 

E1664 

BB_AGND 

BB 

PD 

IOutp 

Vctrl_2p Vctrl_2n 

0 

V 

IOutn 

QOutp 

Qoutn 

VoutI 

VoutIn 

VoutQ 

VoutQn

Full-chip Verification 

System Test Bench 

� Initial Concepts & Specifications 

� Verification of behavioral models 

� Co-simulation to include initial circuit impact 

� Design modifications early for cost savings 

BSRC 

RANDOM 

BERP 

PRE802153A 

HDR802153A 

PHY 

MA C SCR 

PAY802153A 

DATA 

3 

SCR802153A CCOD802153A PUNCT802153A INT802153A 

10 

SCR802153A 

CCOD802153A PUNCT802153A INT802153A 

3 

10 

BSRC 

RANDOM 

VDEC 

ptn 

Baseband Transmitter / Receiver RF Transmitter / Receiver 

TX802153A 

PRE 

HDR COD INT MODIFFT 

PAYSCRCOD INT MODIFFT 

100 10 

100 10 

Sx 

x 

( ) f 

MPSKMOD802153a 

SPR802153A ADDPILOT802153A 

01 11 

I x x 

Q 

x* x* 

00 10 

MPSKMOD802153a 

01 11 

I 

Q 

00 10 

SP 

SPR802153A ADDPILOT802153A 

x x 

x* x* 

3 

10 

10 00 

Q 

I 

x* x* 

x 

x x 

100 10 

DPUNCT802153A DINT802153A 

11 01 

MPSKDEM802153a 

DSPR802153A REMPILOT802153A 

IFFT 

IFFT 

FFT 

SINK 

PRE 

HDR 

PAY 

CDMUX 

SP 

CYCLIC_PREFIX 

SINK 

CYCLIC_REMOVE 

Sx x( 

f ) 

SP 

CDMUX 

U20 

DAC1 

DAC 

TFCOD802153A 

TFCOD802153A 

U25 

ADC 

ADC 

( ) f 

x 

Sx 

Sx ( ) f x 

AVGPP 

AVGPP 

FC=1GHz 

U22 

Synthesizer1 

DIV 

U24 

Synthesizer1 

DIV 

MIXER3P 

IN OUT 

LO 

FL=1GHz 

FU=2GHz 

AGC 

LO 

OUT IN 

AMP 

MIXER3P 

FC=1GHz 

0 

0 

50 

50 

1 

2 

1 

2 

FL=1GHz 

FU=2GHz 

FL=1GHz 

FU=2GHz 

U36 

Antenna 

U37 

Antenna 

U1 

DFF2 

D I 

Db 

phi 

phib 

NSAMP=sample_num 

SAMPLE_RATE=20g 

F=4.224g 

Amplitude=0.4V 

OFFSET=0.5V 

Phase=0deg 



F=4.224g 


OFFSET=0.5V 

Phase=180deg 

RCONST 

CONSTANT=0.5V 



RCONST 

CONSTANT=0.5V 



Ib 

U154 

polyphase_1stage4 

in1 

in2 

in1b 

in2b 

Channel 

CAWGN 

N/2 0 

Indoor 

U114 

Sw_Gm9 

RF 

Rfb 

LO 

LO 

LOb 

LOb 

IF 

U17 

DFF2 

D I 

Db 

phi 

phib 

IFb 

f_if_var=f_if 

w_gm=tune_w_gm 

U124 

Sw_Gm10 

RF IF 

Rfb IFb 

f_if_var=f_if 



f_if_var=f_if 

RF 

Rfb 

U134 

Sw_Gm11 

RF IF 

Rfb IFb 

LO 

LOb 

Iout 

Ioutb 

Qout 

Qoutb 

R1=1/2/3.14159/C1/pole 

C1=1p 

pole=4.224g 

f_if_var=f_if 


LOb 

LO 

IF 

IFb 

Sw_Gm12 

U144 

Ib 

U33 

DFF_iq2 

D I 

Ib 

Q 

Db 

Qd 

phi 

phib 

Qb_528MHz 

SP 

Q_528MHz 

SP 

Ib_528MHz 

SP 

I_528MHz 

SP 

PNUM=1 

RZ=50Ohm 

IZ=0Ohm 

SP 

I_synthout 

SP 

Ib_synthout 

SP 

Q_synthout 

SP 

Qb_synthout 

UMC 0.13um 1.2V/3.3V 


U53 

DFF_iq2 

D I 

Ib 

Q 

Db 

Qd 

phi 

phib 












rnhr_case=typ 






l_cr20k_rf 

I_264MHz 

SP 

LO 

LOb 

SP 

Q_264MHz 

SP 

SP 

U73 

Sw_Gm9 

RF IF 

Rfb IFb 

f_if_var=792meg 

w_gm=6u 

U83 

Sw_Gm10 

RF IF 

Rfb IFb 


w_gm=6u 

LO 

LOb 

w_gm=6u 


RF 

Rfb 

U93 

Sw_Gm11 

RF IF 

Rfb IFb 

LO 

LOb 


w_gm=6u 

C346 

LOb 

LO 

IF 

IFb 

Sw_Gm12 

U103 

SP 

I_swout 

SP 

Ib_swout 

vdd 

0 

l_cr20k_rf 

do=150u 

w=2.29u 

s=1.8u 

nt=2.5 

vdd 

SP 

Q_swout 

SP 

Qb_swout 

dev_m=4 

in1_I 

in1_Ib 

in1_Q 

in1_Qb 

SP 

I_792MHz 

out_I 

out_Ib 

out_Q 

out_Qb 

SP 

Ib_792MHz 

SP 

Q_792MHz 

SP 

in2_I 

in2_Ib 

Qb_792MHz 

in2_Q 

in2_Qb 

U113 

switches1 

vdd vdd 

lf=0.12u 

wf=3u 

0nf=16 

M=1 

RCONST 

CONSTANT=phi1 



RCONST 

phi1 

phi1b CONSTANT=-phi1+1.2 

phi2 



phi2b 

RCONST 

CONSTANT=phi2 



RCONST 

CONSTANT=-phi2+1.2 



U156 

diff_amp1 

in 

out 

inb 

outb 

in 

out 

inb 

outb 

U193 

diff_amp1 

do=150u 

do=150u 

0 

w=5.35u 

1.18pF 

1.18pF 

w=5.35u 

s=1.8u 0 

s=1.8u 0 

nt=2.5 nt=2.5 

vdd 

vdd 

0 

l_cr20k_rf 

0 

V187 

C349 

0.88pF 

R181 

400 

C347 

n_12_rf 

R258 

0 0 

10000 

l_cr20k_rf 

vdd 

vdd 

l_cr20k_rf 

do=150u 

w=1.8u 

s=1.8u 0 

nt=4.5 

vdd 

do=75u 

w=10u 

s=1.8u 

nt=2.5 

C348 

0 

10pF 

Port2

BSRC 

RANDOM 

NB=112*2*symbols/2.5 

BR=data_rate*2 

SEED=1 

SP 

Circuit / System / EM Co-Simulation 

� Block Level 

� Verification of Circuits in System test benches 

� Circuit details analyzed under non-ideal conditions 

� Combined System Level 

tx_bits 

BMEN 

0110/6 

NB=2 

M=4 

I 

Q 

� Integration of multiple circuit blocks 

� Incorporation of Extracted Parasitics 

R 

I 

RITOC 

U1 

DAC2 

DAC 

papr=9 

expand=40 

fcutoff=256MHz 

flength=1024 

fbeta=0.02 

CSCALE 

GAIN=1/sqrt(2) 

� Electromagnetic Simulations 

� Die, Package and Board 

CTORI 

R 

I 

CDMUX 

TYPE=0 

NS1=56 

NS2=56 

REAL_CONST=0V 

IMAG_CONST=0V 

NSAMP=symbols 

SAMPLE_RATE=data_rate 

CCONST 

CCONST 

MIXER3P 

IN OUT 

LO 

MIXER3P 

IN OUT 

LO 

REAL_CONST=0V 

IMAG_CONST=0V 

NSAMP=15*symbols 


CMUX 

CMUX 

TYPE=0 

NS1=1 

NS2=56 

TYPE=0 

NS1=15 

NS2=56 

tx_freq 

CMUX 

TYPE=0 

NS1=57 

NS2=71 

SP 

AMP 

REAL_CONST=0V 

IMAG_CONST=0V 



CCONST 

IFFT 

FFTL=128 

MS21=15 

SP 

tx_time 

CTORI 

TYPE=0 TYPE=0 

NS1=32 NS1=160 

NS2=128 NS2=5 

CMUX 

CMUX 

CCONST 

REAL_CONST=0V 

IMAG_CONST=0V 



R 

I 

40 

SP 

mod_out 

Sx x( 

f ) 

final_tx 

FFTL=8192*2 

TYPE=1 

WINDOW_TYPE=1 

INITSAMP=0 

bbtx 

SP 

Hata 

MNCH 

TYPE=0 

NS1=32 

NS2=133 

bbrx 

CDMUX 

SP 

rx_in 

SINK 

SP 

rx_rfin 

TYPE=0 

NS1=128 

NS2=5 

CDMUX 

U2 

UWB_Rx 

SP 

SINK 

rx_time 

Vsupply=1.2 

LNA_PD=0 

Balun_PD=0 

RxMx_PD=0 

LNA_LG=0 

flo=4g 

rxlo_amp=800m 

txrx=0 

RxBB_PD=0 

Vctrl1=-0.145 

Vctrl2=-0.11 

VcmOut=0.68 

Ibias_lna=0 

Ibias_mx=0 

FFT 

FFTL=128 

SP 

rx_freq 

CDMUX 

TYPE=0 

NS1=57 

NS2=71 

rx_out_I 

rx_out_Q 

TYPE=0 

NS1=1 

NS2=56 

CDMUX 

CDMUX 

TYPE=0 

NS1=15 

NS2=56 

CTORI 

R 

I 

R 

I 

SRDC 

RITOC 

DF=40 

SINK 

SINK 

CMUX 

I 

Q 

EVMP 

I ref 

Qref 

CDMUX 

NS1=time_sync_drop 

NS2=2^20 

EVM 

CSCALE 

TYPE=0 

NS1=56 

NS2=56 

CSCALE 

SINK 

GAIN=sqrt(2) 

SP 

timing_recov_rx 

CTORI 

R 

I 

rx_in 

I 

Q 

V 

0 

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 


UMC 0.13um 1.2V/3.3V 


M=4 

V2819 

0 

0 












rnhr_case=typ S 

rnnpo_case=typ error=1 





C2861 

1p 

V2854 V2855 

C2862 

1p 

V2852 

R2821 

R2823 

0 

V2836 

MBEN 

6/0110 

NB=2 

0.2 

0.2 

V2831 

SP 

0.15n 

L2824 

C2822 

0 

rx_bits 

L2820 

L2847 

0.6n 

C2863 

V2832 

1p 

0 

100p 

BERP 

3.5n 

V2833 

R2865 

200 

LNA_GC 

ANT 

0 

I2783 

RxTx 

LNA_PD 

Balun_PD 

RxMx_PD 

V2835 

0 

V2837 

I2784 

0 

I2785 

V2834 

V 

V 

V V 

E2857 

R2866 

200 

E2858 

R2867 

200 

E2859 

1.2n 

L2825 

0.6n 

L2786 

R2793 

R2794 0.02 

E2860 

V2869 

0 

0 

V2776 

0 

V2777 

V2778 

0 

V2779 

L2826 

1.2n 

L2827 

1.2n 

L2828 

1.2n 

L2829 

1.2n 

L2830 

1.2n 

V2780 

L2787 

0.6n 

L2788 

0.6n 

L2789 

0.4n 

L2790 

0.4n 

L2791 

1.2n 

L2792 

1.2n 

R2795 0.02 

R2868 

200 

R2796 0.02 

C2864 

1p 

U6 

RX_TOP 

R2797 0.01 

0.2n 

L2800 

V2853 

R2798 0.01 

R2799 0.2 

V2781 

0.2 

0 

V2809 V2810 

0 

0 

A 

LNA_Ibias Ibias_mxq Ibias_mxi BB_Ibias 

TRsw_VDD1TRsw_VDD2 LNA_VDD Balun_VDDRxMx_VDD 

BB_AVDD LPF_Tun 

Tx LOq LOqb LOi LOib TRsw_GND1 TRsw_GND2TRsw_GND3LNA_GND 

LNA_GND1 Balun_GND RxMx_GND BB_AGND Vctrl_1p Vctrl_1n Vctrl_2p Vctrl_2n 

V2782 

E2811 E2812 

V2813 

VoutI 

VoutIn 

VoutQ 

VoutQn 

0 

V2856 

R2801 

10k 

R2803 

10k 

V 

C2802 

C2804 

1e-012 

1e-012 

E2806 

E2816 E2817 

V2818 

V 

V2814 V2815 

0 

0 

0 

V V 

-0.145(min gain)

UWB Receiver Co-Simulation Results 

� Transient Co-Simulation of UWB Receiver 

� Baseband and RF waveforms 

� UWB OFDM Frame 

� Transient and Spectral display 

� Demodulated symbol Constellation

IFFT 

FFTL=128 

FFT 

FFTL=128 

I 

Q 

M=4 

RITOC 

R 

I 

BSRC 

RANDOM 

NB=112*2*symbols/2.5 

BR=data_rate*2 

SEED=1 

SP 

tx_freq 

BMEN 

0110/6 

NB=2 

CMUX 

TYPE=0 

NS1=1 

NS2=56 

CCONST 

REAL_CONST=0V 

IMAG_CONST=0V 

NSAMP=symbols 


CDMUX 

TYPE=0 

NS1=56 

NS2=56 

CMUX 

TYPE=0 

NS1=15 

NS2=56 

CCONST 

REAL_CONST=0V 

IMAG_CONST=0V 



CMUX 

TYPE=0 

NS1=57 

NS2=71 

SP 

tx_time 

SP 

rx_freq 

SP 

tx_bits 

CSCALE 

GAIN=1/sqrt(2) 

CMUX 

TYPE=0 

NS1=32 

NS2=128 

CMUX 

TYPE=0 

NS1=160 

NS2=5 

CCONST 

REAL_CONST=0V 

IMAG_CONST=0V 



CCONST 

REAL_CONST=0V 

IMAG_CONST=0V 



CDMUX 

TYPE=0 

NS1=32 

NS2=133 

SP 

rx_time 

SINK 

CDMUX 

TYPE=0 

NS1=128 

NS2=5 

SINK 

CDMUX 

TYPE=0 

NS1=57 

NS2=71 

CDMUX 

TYPE=0 

NS1=1 

NS2=56 

CDMUX 

TYPE=0 

NS1=15 

NS2=56 

SINK 

SINK 

CMUX 

TYPE=0 

NS1=56 

NS2=56 

I 

Q 

M=4 

CTORI 

R 

I 

MBEN 

6/0110 

NB=2 

CSCALE 

GAIN=sqrt(2) 

SP 

rx_bits 

BERP 

EVMP 

I 

Q 

I ref 

ref 

Q 

EVM 

CTORI 

R 

I 

CTORI 

R 

I 

RITOC 

R 

I 

SINK 

SRDC 

DF=40 

SP 

bbrx 

CTORI 

R 

I 

SP 

bbtx 

DAC 

U1 

DAC2 

papr=9 

expand=40 

fcutoff=256MHz 

flength=1024 

fbeta=0.02 

CDMUX 

NS1=time_sync_drop 

NS2=2^20 

CSCALE 

MIXER3P 

IN OUT 

LO 

MIXER3P 

IN OUT 

LO 

SP 

timing_recov_rx 

rx_in 

rx_out_I 

rx_out_Q 

U2 

UWB_Rx 

Vsupply=1.2 

LNA_PD=0 

Balun_PD=0 

RxMx_PD=0 

LNA_LG=0 

flo=4g 

rxlo_amp=800m 

txrx=0 

RxBB_PD=0 

Vctrl1=-0.145 

Vctrl2=-0.11 

VcmOut=0.68 

Ibias_lna=0 

Ibias_mx=0 

40 

AMP 

MS21=15 

SP 

mod_out 

S x ( ) 

f 

x 

final_tx 

FFTL=8192*2 

TYPE=1 

WINDOW_TYPE=1 

INITSAMP=0 

MNCH 

Hata 

SP 

rx_rfin 

Vector Signal Generator 

Vector Signal Analyzer 

Receiver Chip 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

rx_in 

rx_out_I 

rx_out_Q 

V2776 

V2777 

V2778 

V2779 

V2780 

V2781 

V2782 

I2783 

I2784 

I2785 

0.6n 

L2786 

0.6n 

L2787 

0.6n 

L2788 

0.4n 

L2789 

0.4n 

L2790 

1.2n 

L2791 

1.2n 

L2792 

0.02 

R2793 

0.02 

R2794 

0.02 

R2795 

0.01 

R2796 

0.01 

R2797 

0.2 

R2798 

0.2 

R2799 

0.2n 

L2800 

10k 

R2801 

1e-012 

C2802 

10k 

R2803 

1e-012 

C2804 

V 

E2806 

V 

E2808 

V2809 V2810 

E2811 E2812 

V2813 

V2814 V2815 

E2816 E2817 

V2818 

V2819 

3.5n 

L2820 

0.2 

R2821 

100p 

C2822 

0.2 

R2823 

0.15n 

L2824 

1.2n 

L2825 

1.2n 

L2826 

1.2n 

L2827 

1.2n 

L2828 

1.2n 

L2829 

1.2n 

L2830 

V2831 

V2832 

V2833 

V2834 

V2835 

V2836 

V2837 

A 

UMC 0.13um 1.2V/3.3V 


mos_corner=tt 


UMC 0.13um 1.2V/3.3V 











rnhr_case=typ 








UMC 0.13um 1.2V/3.3V 


mos_corner=tt 

V 

V 

V 

V 

V 

0.6n 

L2847 

V 

V 

V V 

V2852 

V2853 

V2854 V2855 

V2856 

E2857 

E2858 

E2859 

E2860 

1p 

C2861 

1p 

C2862 

1p 

C2863 

1p 

C2864 

200 

R2865 

200 

R2866 

200 

R2867 

200 

R2868 

V2869 

S 

error=1 

ANT 

LNA_PD 

LNA_GND LNA_GND1 

LNA_GC 

LNA_VDD 

LNA_Ibias 

Tx 

RxTx 

TRsw_GND1 

TRsw_GND2TRsw_GND3 


Balun_GND 

Balun_VDD 

Balun_PD 

Ibias_mxi 

Ibias_mxq RxMx_VDD 

RxMx_PD 

LOi LOib 

LOq LOqb RxMx_GND 

BB_AVDD LPF_Tun 

BB_Ibias 

VoutI 

VoutIn 

VoutQ 

VoutQn 

Vctrl_2n 

Vctrl_2p 

Vctrl_1n 

Vctrl_1p 

BB_AGND 

U6 

RX_TOP 

-0.145(min gain)

RFIC Design Flow Whitepaper 

� UMC and Ansoft Co-author new Design 

Flow for RFIC 

� Whitepaper Details: 

� Design Capture 

� Circuit Simulation 

� On-chip Passive Simulation 

� Layout Extraction 

� Packaging 

� Full-chip Verification 

� Available at UMC and Ansoft Website

Conclusion 

� UMC and Ansoft teamed to develop a design solution for complex RFICs that 

include custom RF, analog, and mixed-signal circuits. 

� On-chip passive modeling 

� Circuit design and simulation 

� Full-chip verification 

� UWB radio project has been transformed from initial circuit designs to 

production-ready circuits and layout. 

� Expect test chips back from fabrication in October 

� RFIC Design flow provides platform for developing advanced RFICs: 

� UMC’s advanced RF CMOS semiconductor process 

� Electronic design automation (EDA) tools from Ansoft and other established 

vendors 

� Design Flow leverages UMC’s production-proven 0.13 um RFCMOS process and 

advanced circuit simulation and electromagnetic extraction tools from Ansoft. 

� Additional fidelity in modeling, simulation, and verification coverage can be 

gained by following this advanced design flow.

Appendix – Circuit Block Modification 

Summary 

� Details on the circuit modifications to make layout- and 

production-ready circuits for: 

� T/R Switch 

� LNA 

� I/Q Mod/Demod. 

� Synthesizer 

� Baseband

Previous Work for 

UWB T/R Switch

UWB T/R Switch from Previous Work 

0 

0 

vdd_sw 

0 

gnd_sw 

Port1 

Port2 

Port3 

ps_filt 

rx 

tx 

ctrl 

U1 

TRswitch3 

V50 

DC=if(sw==1, 1.2, 0) 

V53 

DC=1.2 

V58 

DC=0 

UMC 0.13um 1.2V/3.3V 


PMOS 

STI 

STI 

STI 

NMOS 

p-type 










rnhr_case=typ 








vdd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

gnd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

gnd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

gnd_sw 

vdd_sw 

gnd_sw 

ps_filt 

rx 

tx 

ctrl 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=1.8u 

M=3 

wt=28.8u 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=1.8u 

M=3 

wt=28.8u 

l=5u 

w=1u 

m=1 

rnhr_rf 

r_zbt=4.816k 

l=5u 

w=1u 

m=1 

rnhr_rf 

r_zbt=4.816k 

n_12_rf 

nf=16 

lf=0.12u 

wf=1.8u 

M=1 

wt=28.8u 

p_12_rf 

nf=16 

lf=0.12u 

wf=2.4u 

M=1 

wt=38.4u 

l=20u 

w=1u 

m=1 

rnhr_rf 

r_zbt=20.636k 

l=20u 

w=1u 

m=1 

rnhr_rf 

r_zbt=20.636k 

l_cr20k_rf 

do=136.01u 

w=6u 

s=1.8u 

nt=4.5 

p_ls=2.3n 

l=21.68u 

w=21.68u 

mimcaps_rf 

M=1 


l=20.27u 

w=20.27u 

mimcaps_rf 

M=1 


index=8 

l=80.8u 

w=74.2u 

c_pad=38.6f 

l_cr20k_rf 

do=149.12u 

w=1.9u 

s=1.8u 

nt=6.5 

p_ls=7.9n 

vdd_sw 

gnd_sw 

gnd_sw


UWB T/R Switch from Previous Work


UWB T/R Switch from Previous Work

Modifications 

for 

UWB T/R Switch

UMC 0.13um 1.2V/3.3V 


STI 

NMOS 

PMOS 

STI 

STI 

p-type 












rnhr_case=typ 






vdd_sw 

0 

index=8 

l=80.8u 

w=74.2u 

c_pad=38.6f 

V53 

DC=1.2 

gnd_sw 

ps_f ilt 

gnd_sw 

0 

V58 

DC=0 

vdd_sw 

Port3 

gnd_sw 

l=c1_len 

w=c1_len 

M=1 

ps_filt 

gnd_sw 

U2 

TRswitch2 

ctrl 

0 

V50 

rx 

tx 

Final Circuit for UWB T/R Switch 

Port1 

Port2 

DC=if(sw==1, 1.2, 0) 

do=Ls_do 

w=Ls_w 

s=Ls_s 

nt=Ls_nt 

mimcaps_rf 


vdd_sw 

l_cr20k_rf 

p_ls=1.8n 

gnd_sw 

vdd_sw 

gnd_sw 

l=c2_len 

w=c2_len 

M=1 

gnd_sw 

mimcaps_rf 


vdd_sw 

gnd_sw 

gnd_sw 

n_bpw_12_rf 

lf=0.12u 

wf =7.2u 

nf =16 

M=1 

wt=115.2u 

rnhr_rf 

r_zbt=4.816k 

wt=86.4u 

M=1 

nf=16 

wf=5.4u 

lf=0.12u 

gnd_sw 

gnd_sw 

l=5u 

w=1u 

m=1 

l=5u 

w=1u 

m=1 

vdd_sw 

n_bpw_12_rf 

vdd_sw 

rnhr_rf 

r_zbt=4.816k 

gnd_sw 

gnd_sw 

vdd_sw 

ctrl 

p_12_rf 

lf=0.12u 

wf =2.4u 

nf =16 

M=1 

wt=38.4u 

n_12_rf 

vdd_sw 

lf=0.12u 

wf =1.8u 

nf =16 

M=1 

wt=28.8u 

gnd_sw 

gnd_sw 

rnhr_rf 

r_zbt=20.636k 

rnhr_rf 

r_zbt=20.636k 

l=20u 

w=1u 

m=1 

l=20u 

w=1u 

m=1 

tx 

rx 

vdd_sw 

gnd_sw 

vdd_sw 

gnd_sw


Final Result for UWB T/R Switch


Final Result for UWB T/R Switch

Modification Summary for T/R Switch 

� Achieved improved input match and insertion loss on receive 

channel with slight sacrifice of transmit characteristics. 

� Eliminate the one of inductors in the matching circuit, since 

this inductor has large size. 

� Reducing the size of the T/R switch. 

� Improved the receiving characteristics.

Layout for UWB T/R Switch

Previous Work 


UWB LNA

UMC 0.13um 1.2V/3.3V 


STI 

NMOS 

STI 

PMOS 

STI 

p-type 












rnhr_case=typ 






U2 

LNA6 

Port1 Port2 

in out 

vdd_lna 

mimcaps_rf 

c_tot=10.349p 

in 

gnd_lna 

UWB LNA from Previous Work 

l=50u 

w=50u 

M=4 

vdd_lna 

do=93.34u 

w=2.7u 

s=1.8u 

nt=3.5 

vdd_lna 

V56 

DC=1.2 

gnd_lna 

0 0 

gnd_lna 

vdd_lna 

l_cr20k_rf 

p_ls=1.43n 

gnd_lna 

C136 

vdd_lna 

V59 

DC=0 

1.5pF 

nt=3.5 

s=1.8u 

w=2.7u 

do=111.08u 

gnd_lna 

vdd_lna 

vdd_lna 

gnd_lna 

p_ls=1.9n 

l_cr20k_rf 

R35 

n_bpw_12_rf 

gnd_lna 

400 

lf=0.12u 

wf =3u 

nf =16 

M=1 

C139 

C142 

1.5pF 

0.88pF 

R145 

10k 

vdd_lna 

do=93.34u 

w=2.7u 

s=1.8u 

nt=3.5 

l_cr20k_rf 

p_ls=1.43n 

gnd_lna 

vdd_lna 

gnd_lna 

vdd_lna 

nt=3.5 

s=1.8u 

w=2.7u 

do=149.1u 

n_bpw_12_rf 

lf =0.12u 

wf =3u 

nf =16 

M=4 

n_bpw_12_rf 

lf =0.12u 

wf =3u 

nf =16 

M=4 

L143 

0.35n 

p_ls=3n 

l_cr20k_rf 

gnd_lna 

gnd_lna 

vdd_lna 

vdd_lna 

C52 

10p 

out

UWB LNA from Previous Work

UWB LNA from Previous Work

Modifications 


UWB LNA_v1

Final UWB LNA_v1 

0 0 

0 

0 

0 

Port1 Port2 

LNA 

RFin 

RFout 

GC 

AVDD 

AGND AGND1 

PD 

Ibias 

U1 

LNA1 

V2691 

DC=LNA_LG*Vsupply 

V2695 

DC=Vsupply 

V2700 

DC=LNA_PD*Vsupply 

I2705 

UMC 0.13um 1.2V/3.3V 


PMOS 

STI 

STI 

STI 

NMOS 

p-type 

mos_corner=ss 

res_case=res_max 

UMC 0.13um 1.2V/3.3V 


PMOS 

STI 

STI 

STI 

NMOS 

p-type 

coremos_corner=ss 

iomos_corner=ss 








rnhr_case=min 


rnnpo_case=min 

rnppo_case=min 





UMC 0.13um 1.2V/3.3V 


PMOS 

STI 

STI 

STI 

NMOS 

p-type 

mos_corner=ss 

RFin 

RFout 

GC 

AVDD 

AGND 

AGND1 

PD 

Ibias 

AGND1 

Ibias 

PD 

AVDD 

AGND1 

U18 

Nexxim6 

l=25.6u 

w=25.6u 

mimcaps_rf 

M=1 

c_tot_m=0.7p 

l_cr20k_rf 

do=150u 

w=6.2u 

s=2.5u 

nt=6.5 

p_ls=3.29n 

l=34.8u 

w=34.8u 

mimcaps_rf 

M=1 


l=20u 

w=2u 

m=1 

rnhr_rf 

r_zbt_m=9.96k 

l_cr20k_rf 

do=150u 

w=3.2u 

s=2.5u 

nt=7.5 

p_ls=6.44n 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=3u 

M=4 

wt=48u 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=3u 

M=4 

wt=48u 

l_cr20k_rf 

do=75u 

w=6.3u 

s=1.79u 

nt=2.5 

p_ls=0.37n 

l_cr20k_rf 

do=149u 

w=5.2u 

s=1.8u 

nt=4.5 

p_ls=3.06n 

l=26.6u 

w=26.6u 

mimcaps_rf 

M=1 


l=100u 

w=100u 

mimcaps_rf 

M=1 

c_tot_m=10.174p 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=3u 

M=4 

wt=48u 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=3u 

M=4 

wt=48u 

l_cr20k_rf 

do=75u 

w=5.6u 

s=2.5u 

nt=2.5 

p_ls=0.38n 

l_cr20k_rf 

do=150u 

w=2.7u 

s=2.5u 

nt=7.5 

p_ls=7.13n 

l_cr20k_rf 

do=149u 

w=5.2u 

s=1.8u 

nt=6.5 

p_ls=4.34n 

l=20u 

w=2u 

m=1 

rnhr_rf 

r_zbt_m=9.96k 

l=26.6u 

w=26.6u 

mimcaps_rf 

M=1 


n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=1.8u 

M=1 

wt=28.8u 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=1.8u 

M=1 

wt=28.8u 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=1.8u 

M=1 

wt=28.8u 

l=20u 

w=2u 

m=1 

rnhr_rf 

r_zbt_m=9.96k 

l=99.77u 

w=99.77u 

mimcaps_rf 

M=1 

c_tot_m=10.128p 

varmis_12_rf 

w=10u 

nf=8 

l=2u 

m=1 

cox_m=1710.5f 

12mA 12mA 

2mA

Final Result for UWB LNA_v1 

FF, 1.3v, 0cel, max_res 

TT, 1.2v, 27cel, typ_res 

SS, 1.1v, 125cel, min_res

Final Result for UWB LNA_v1 

FF, 1.3v, 0cel, max_res 

TT, 1.2v, 27cel, typ_res 

SS, 1.1v, 125cel, min_res

Modification Summary for LNA_v1 

� Used non-ideal components, such as capacitors and resistor. 

� Q-optimization for all of spiral inductors used in LNA_v1 

� Bias circuit added 

� Gain controlled circuit added 

� Source follower added at the output 

� Output matching improved 

� Change the input matching/filter from BPF type to HPB 

� Gain improved 

� Input matching improved 

� Noise figure improved (compared with original one with real 

component replaced) 

� Cascading the one stage to boost gain

Layout for UWB LNA_v1

Addition for UWB Active Balun 

(no previous work )

Broadband Active Balun Added 

Conventional Active Balun 

Proposed Active Balun 

vdd_bln 

gnd_bln 


gnd_bln 

vdd_bln 

gnd_bln 


gnd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

gnd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

vdd_bln 



gnd_bln 


gnd_bln 

vdd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

vdd_bln 

vdd_bln 

gnd_bln 

gnd_bln 

vdd_bln 

vdd_bln 

gnd_bln 

vdd_bln 

gnd_bln 

vg_cs 

out outb 

n_bpw_12_rf 

nf=10 

lf=0.12u 

wf=7.2u 

M=1 

wt=72u 

n_bpw_12_rf 

nf=nf1_cg 

lf=0.12u 

wf=wf1_cg 

M=m1_cg 

wt=115.2u 

n_12_rf 

nf=8 

lf=0.12u 

wf=1.8u 

M=1 

wt=14.4u 

n_12_rf 

nf=4 

lf=0.12u 

wf=1.8u 

M=1 

wt=7.2u 

n_bpw_12_rf 

nf=nf2_cg 

lf=0.12u 

wf=wf2_cg 

M=m2_cg 

wt=115.2u 

l=5u 

w=2u 

m=3 

rnnpo_rf 


l_cr20k_rf 

do=100u 

w=1.5u 

s=2u 

nt=5.5 

p_ls=3.43n 

l=100u 

w=100u 

mimcaps_rf 

M=1 

c_tot_m=10.174p 

l=100u 

w=100u 

mimcaps_rf 

M=1 

c_tot_m=10.174p 

l=74.8u 

w=48.5u 

mimcaps_rf 

M=1 


l=100u 

w=100u 

mimcaps_rf 

M=1 

c_tot_m=10.174p 

l=100u 

w=100u 

mimcaps_rf 

M=1 

c_tot_m=10.174p 

l=5u 

w=2u 

m=3 

rnnpo_rf 


l=6.9u 

w=2u 

m=3 

rnnpo_rf 


l=7u 

w=2u 

m=3 

rnnpo_rf 


l=79u 

w=71u 

mimcaps_rf 

M=2 


l_cr20k_rf 

do=120u 

w=5u 

s=2u 

nt=2.5 

p_ls=1.02n 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

vg_cs 

v_div1 

v_div2 

vg2_cg 

vg1_cg 

vdd_bln 

gnd_bln 

0 0 

Port1 

Port2 

Port3 

vg_cs 

out 

outb 

U1 

Act_Balun1 

UMC 0.13um 1.2V/3.3V 


PMOS 

STI 

STI 

STI 

NMOS 

p-type 










rnhr_case=typ 








V68 

DC=1.2 

V72 

DC=0 

l=100u 

w=100u 

mimcaps_rf 

M=1 

c_tot_m=10.174p 

gnd_bln 

vdd_bln

Broadband Active Balun Added 

Phase 

Imbalance 

Amplitude 

Imbalance

Layout for UWB Active Balun

Previous work & Modifications 


UWB IQ Modulator 

Please use the slide show to see the animation of previous vs 

modification work and corresponding improving performance.

gnd_mix 

DC=0 

Design w/ Parasitic for I-V BPF: 

Bias 

only! 

V464 

DC=0.75 

0 0 

V302 

0 

DC=1.2 

vdd_mix 

Bias 

only! 

V497 

DC=0.75 

0 

0 0 

V467 

DC=0.75 

V303 

RF 

Rfb 

V498 

DC=0.75 

ctrl1 

ctrl2 

LO 

LOb 

ctrl1 

ctrl2 

RF 

Rfb 

LO 

U1 

Sw_Gm_trk2 

IF 

IFb 

U2 

Sw_Gm_trk2 

IF 

IFb 

V470 

DC=0.5 

0 0 

V473 

DC=0.5 

Capacitance in Capacitor 

Array should be changed 

(reduced) to fit desired 

pass-band! 

LOb 

IQ Modulator Refinement 

0 

V438 

DC=if (sw>=2, 1.2, 0) 

I474 

0 0 

UMC 0.13um 1.2V/3.3V 













rnhr_case=typ 






out 

ACMAG=1 

ACPHASE=0 

V 

0 

I477 

V439 

DC=if (sw>=1, 1.2, 0) 

V 

ACMAG=1 

ACPHASE=180 

ctrl2 ctrl1 

n_bpw_12_rf 

lf=0.12u 

wf=0.9u 

nf=8 

M=1 

mimcaps_rf 

Differential 

AC current 

excitation! 

vdd_mix 

gnd_mix 

l=20u 

w=20u 

M=1 

n_bpw_12_rf 

lf=0.12u 

wf=0.9u 

nf=8 

M=1 

mimcaps_rf 

l=20u 

w=20u 

M=1 

to_bias 

vdd_mix 

gnd_mix 

RF 

R65 

R_if 

vdd_mix 

gnd_mix 

gnd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

IF IFb 

ctrl1 ctrl2 

vdd_mix 

V V 

to_drain 

mimcaps_rf 

l=22u 

w=30u 

M=1 

vdd_mix 

n_bpw_12_rf 

lf=0.12u 

wf=w_gm 

nf=16 

M=1 

gnd_mix 

do=97u 

w=5u 

s=2u 

nt=4.5 

l_cr20k_rf 

U13 

swC_tank2 

to_bias 

to_drain 

ctrl1 

ctrl2 

n_bpw_12_rf 

p_12_rf 

n_bpw_12_rf 

lf=0.12u 

wf=w_gm 

nf=16 

M=1 

lf=0.12u 

wf=2.5u 

nf=14 

M=1 

lf=0.12u 

wf=1.25u 

nf=14 

M=1 

vdd_mix 

LO LOb 

gnd_mix gnd_mix 

Rfb 

U12 

swC_tank2 

to_drain to_bias 

n_bpw_12_rf 

lf=0.12u 

wf=w_gm 

nf=16 

M=1 

p_12_rf 

lf=0.12u 

wf=2.5u 

nf=14 

M=1 

ctrl2 

n_bpw_12_rf 

lf=0.12u 

wf=1.25u 

nf=14 

M=1 

ctrl1 

do=97u 

w=5u 

s=2u 

nt=4.5 

vdd_mix 

gnd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

l_cr20k_rf 

vdd_mix 

gnd_mix 

R70 

R_if 

n_bpw_12_rf 

lf=0.12u 

wf=w_gm 

nf=16 

M=1


vdd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

to_drain 

to_bias 

ctrl2 ctrl1 

l=22u 

w=30u 

mimcaps_rf 

M=1 

l=20u 

w=20u 

mimcaps_rf 

M=1 

l=20u 

w=20u 

mimcaps_rf 

M=1 

n_bpw_12_rf 

nf=8 

lf=0.12u 

wf=0.9u 

M=1 

n_bpw_12_rf 

nf=8 

lf=0.12u 

wf=0.9u 

M=1 

vdd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

vdd_mix 

gnd_mix 

to_drain 

to_bias 

ctrl2 ctrl1 

l=23u 

w=30u 

mimcaps_rf 

M=1 


l=20u 

w=20u 

mimcaps_rf 

M=1 

c_tot_m=0.43p 

l=21u 

w=21u 

mimcaps_rf 

M=1 


n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=3.6u 

M=1 

wt=57.6u 

n_bpw_12_rf 

nf=16 

lf=0.12u 

wf=3.6u 

M=1 

wt=57.6u

Conversion 

Conversion 

Gain 

Gain 

=-1.53 

=-0.93 

dB 

dB 


Conversion 

Conversion 

Gain 

Gain 

Conversion 

Conversion 

Gain 

Gain 

=-2.44 

=-5.03 

dB 

dB 

=-2.92 

=-6.72 

dB 

dB

Modification Summary for IQ 

Modulator 

� Enlarged the size of transistors in the tracking filter 

� Flatten the frequency response 

� Improve the impedance level of tracking filter 

� Reduce the conversion loss. 

� Improve frequency selectivity of the tracking filter thus improving 

the spurious response of the IQ modulator.

Layout for IQ Modulator

Original work 

of 

UWB Synthesizer

phib 

phi 

Db 

D I 

Ib 

U1 

DFF2 

phib 

phi 

Db 

D I 

Ib 

U17 

DFF2 

phib 

phi 

Db 

D I 

Ib 

Q 

Qd 

U33 

DFF_iq2 

phib 

phi 

Db 

D I 

Ib 

Q 

Qd 

U53 

DFF_iq2 

NSAMP=s ample_num 


F=4.224g 


OFFSET=0.5V 

Phase=0deg 

NSAMP=s ample_num 


F=4.224g 


OFFSET=0.5V 

Phase=180deg 

SP 

I_528MHz 

SP 

I_264MHz 

SP 

Ib_528MHz 

SP 

Q_528MHz 

SP 

Qb_528MHz 

SP 

SP 

Q_264MHz 

SP 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U73 

Sw_Gm9 


w_gm=6u 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U83 

Sw_Gm10 


w_gm=6u 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U93 

Sw_Gm11 


w_gm=6u 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U103 

Sw_Gm12 


w_gm=6u 

SP 

I_792MHz 

SP 

Ib_792MHz 

SP 

Qb_792MHz 

SP 

Q_792MHz 

out_I 

out_Ib 

out_Q 

out_Qb 

phi1 

phi1b 

in1_I 

in1_Ib 

in1_Q 

in1_Qb 

phi2 

phi2b 

in2_I 

in2_Ib 

in2_Q 

in2_Qb 

U113 

switches1 

dev_m=4 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U114 

Sw_Gm9 

f_if_var=f_if 


LO 

LOb 

RF 

Rfb 

IF 

IFb 

U124 

Sw_Gm10 

f_if_var=f_if 


LO 

LOb 

RF 

Rfb 

IF 

IFb 

U134 

Sw_Gm11 

f_if_var=f_if 


LO 

LOb 

RF 

Rfb 

IF 

IFb 

U144 

Sw_Gm12 

f_if_var=f_if 


Qout 

Iout 

Qoutb 

Ioutb 

in2 

in1 

in1b 

in2b 

U154 


R1=1/2/3.14159/C1/pole 

C1=1p 

pole=4.224g 

RCONST 

CONSTANT=0.5V 



RCONST 

CONSTANT=0.5V 



SP 

I_synthout 

SP 

Ib_synthout 

SP 

Q_synthout 

SP 

Qb_synthout 

RCONST 

CONSTANT=phi1 



RCONST 




RCONST 

CONSTANT=phi2 



RCONST 




SP 

I_swout 

SP 

Ib_swout 

SP 

Q_swout 

SP 

Qb_swout 

in 

inb 

out 

outb 

U156 

diff_amp1 

in 

inb 

out 

outb 

U193 

diff_amp1 

phib 

phi 

Db 

D I 

Ib 

U15 

DFF3 

phib 

phi 

Db 

D I 

Ib 

U16 

DFF3 

phib 

phi 

Db 

D I 

Ib 

Q 

Qd 

U1 

DFF_iq3 

phib 

phi 

Db 

D I 

Ib 

Q 

Qd 

U2 

DFF_iq3 



F=4.224g 


OFFSET=0.5V 

Phase=0deg 



F=4.224g 


OFFSET=0.5V 

Phase=180deg 

SP 

I_528MHz 

SP 

I_264MHz 

SP 

Ib_528MHz 

SP 

Q_528MHz 

SP 

Qb_528MHz 

SP 

Ib_264MHz 

SP 

Q_264MHz 

SP 

Qb_264MHz 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U3 

Sw_Gm13 


w_gm=6u 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U4 

Sw_Gm14 


w_gm=6u 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U5 

Sw_Gm15 


w_gm=6u 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

U6 

Sw_Gm16 


w_gm=6u 

SP 

I_792MHz 

SP 

Ib_792MHz 

SP 

Qb_792MHz 

SP 

Q_792MHz 

out_I 

out_Ib 

out_Q 

out_Qb 

phi1 

phi1b 

in1_I 

in1_Ib 

in1_Q 

in1_Qb 

phi2 

phi2b 

in2_I 

in2_Ib 

in2_Q 

in2_Qb 

U7 

switches3 

dev_m=4 

Qout 

Iout 

Qoutb 

Ioutb 

in2 

in1 

in1b 

in2b 

U12 


R1=1/2/3.14159/C1/pole 

C1=1p 

pole=4.224g 

RCONST 

CONSTANT=0.5V 



RCONST 

CONSTANT=0.5V 



SP 

I_synthout 

SP 

Ib_synthout 

SP 

Q_synthout 

SP 

Qb_synthout 

RCONST 

CONSTANT=phi1 



RCONST 




RCONST 

CONSTANT=phi2 



RCONST 




SP 

I_swout 

SP 

Ib_swout 

SP 

Q_swout 

SP 

Qb_swout 

in 

inb 

out 

outb 

U13 

diff_amp2 

in 

inb 

out 

outb 

U14 

diff_amp2 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

ctrl1 

ctrl2 

U8 

Sw_Gm_trk3 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

ctrl1 

ctrl2 

U201 

Sw_Gm_trk4 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

ctrl1 

ctrl2 

U224 

Sw_Gm_trk4 

LO 

LOb 

RF 

Rfb 

IF 

IFb 

ctrl1 

ctrl2 

U247 

Sw_Gm_trk4 

Synthesizer Refinement

Complex Signal Spectrum for Synthesizer output (dB) 

( φφ 

) = ( 0 , 0 ) 

1 , 2 

Synthesizer Refinement 

φφ Band1: 4224-792=3424


( φφ 

φφ 

) = ( 1 , 0 ) 

1 , 2 


Band2: 4224-264=3960


( φφ 

φφ 

) = ( 1 , 1 ) 

1 , 2 


Band3: 4224+264=4488

gnd_mix 

V397 

VO=0.5 

VA=0.4 

FREQ=4.224g 

THETA=180 

0 

V1005 

DC=0 

0 

0 

vdd_mix 

0 0 

V927 

DC=0.5 

U1 

DFF4 

D I 

Db 

phi 

V398 

VO=0.5 

VA=0.4 

FREQ=4.224g 

THETA=0 

V1006 

DC=1.2 

LOinb 

0 

phib 

V928 

DC=0.5 

Ib 

LOin 

in1 

in2 

in1b 

in2b 

V 

U8 


U2 

DFF4 

D I 

Db 

phi 

phib 

UMC 0.13um 1.2V/3.3V 













rnhr_case=typ 






Iout 

Ioutb 

Qout 

Qoutb 

R1=1/2/3.14159/C1/pole 

C1=1p 

pole=4.224g 

V 

V 

V 

Ib 

I_4224M 

Ib_4224M 

Q_4224M 

Qb_4224M 

V 

Synthesizer Settling 

V 

U3 

DFF_iq4 

D I 

Ib 

Q 

Db 

phi 

V 

V 

V 

V 

RF_I 

RF_Ib 

RF_Q 

RF_Qb 

Qb_528MHz 

phib 

Q_528MHz 

LO_I 

Qd 

Ib_528MHz 

LO_Ib 

LO_Q 

I_528MHz 

ctrl1 ctrl2 

LO_Qb 

IF_I 

IF_Ib 

IF_Q 

IF_Qb 

I_synthout 

Ib_synthout 

Q_synthout 

Qb_synthout 

U147 

Complex_Mixer_bpfout 

f_if=285meg 

tune_w_gm=2.5u 

U4 

DFF_iq4 

D I 

Ib 

Q 

Db 

phi 

phib 

Qd 

RF_Qb 

RF_Q 

RF_Ib 

RF_I 

I_264MHz 

LO_Ib 

LO_I 

V V V V 

Ib_264MHz 

LO_Qb 

LO_Q 

V V V V 

IF_Qb 

IF_Q 

IF_Ib 

IF_I 

in1_I 

in1_Ib 

in1_Q 

in1_Qb 

in2_I 

in2_Ib 

U6 

Complex_Mixer1 I_792MHz Q_792MHz 

tune_w_gm=2.5u out_I 

Ib_792MHz Qb_792MHz 

f_if=792meg 

I_swout 

Q_264MHz 

V 

V V V 

V V V V 

Ib_swout 

Qb_264MHz 

Q_swout 

Qb_swout 

out_Ib 

in2_Q 

in2_Qb 

out_Q 

out_Qb 

UMC 0.13um 1.2V/3.3V 

Twin, Tripple W ell Mixed_Mode 

U7 

switches4 

phi1 

phi1b 

phi2 

phi2b 

mos_corner=tt 


gnd_fs 

V429 

DC=0 

vdd_fs 

0 0 

V430 

DC=1.2 

V V V V 

phi2 

phi1 

R1143 

V971 

V970 

V969 

V968 

V1=1.2 

V1=0 

V1=1.2 

V1=0 

V2=0 

V2=1.2 

V2=0 

V2=1.2 

TD=50n 

TD=50n 

TD=0 

TD=0 

TR=1n 

TR=1n 

TR=1n 

TR=1n 

TF=1n 

TF=1n 

TF=1n 

TF=1n 

PW=100n PW=100n PW=100n PW=100n 

PER=200n PER=200n PER=200n PER=200n 

0 0 0 0 

0.05 

R1148 

0.05 

R1147 

0.05 

R1149 

0.05 

gnd_mix 

vdd_mix

Synthesizer Settling

Spectrum Directly from Nexxim 

Ch1


Ch2


Ch3

Modifications 


UWB Synthesizer

Synthesizer Schematic

Synthesizer Schematic

UMC 

TT 

Ch1 Spectrum

UMC 

TT 

Ch2 Spectrum

UMC 

TT 

Ch3 Spectrum

Simulation Results 

TT: MOS=tt, res=res_typ, cap=typ, ind=typ, temp=25 deg, Vdd=1.2 

SS: MOS=ss, res=res_min, cap=max, ind=min, temp=125 deg, Vdd=1.1 

FF: MOS=ff, res=res_max, cap=min, ind=max, temp=-25 deg, Vdd=1.3 

After removing the inclkbuff 

TT SS FF 

Ch1 carrier amp (dBv) -26.45 -36.847 -23.645 



Current Consumption (mA) 120 106 140 

TT SS FF 

Ch1 largest spur (dBc) -30.45 at fc + 2*df -15.5451 at fc + 2*df -28.52 at fc - 2*df 

Ch2 largest spur (dBc) -28.33 at fc + 2*df -24.58 at fc + 2*df -26.73 at fc - df 

Ch3 largest spur (dBc) -22.83 at fc - 2*df -26.36 at fc - 2*df -17.1 at fc - 2*df 

TT SS FF 

Ch1 largest adj spur (dBc) -35.85 at fc - df -30.14 at fc + df -40.13 at fc - df 

Ch2 largest adj spur (dBc) -31.85 at fc - df -39.04 at fc - df -30.3 at fc - df 

Ch3 largest adj spur (dBc) -34.31 at fc - df -40.57 at fc + df -35.23 at fc - df

Modification Summary for 

Synthesizer 

� A fixed frequency filter and tracking filter were added at 

output of the 1st and 2nd complex mixer for better spur 

rejection. 

� CML frequency divider has been changed to one that is 

silicon validated. 

� Input source of the synthesizer has been changed to real 

striped-band switching VCO. 

� Some of I/Q imbalance issues have been addressed. 

� The divider output into complex mixers has been de-coupled 

with buffers and RC filters.

Layout for Synthesizer

Original work 


UWB Analog Basband Filter and 

Gain Controlled Stage

0 

V240 

0 0 0 0 0 

0 

in 

inb 

U MC 0.13um 1.2V /3.3V 

Tw in, Tripple W ell Mixed_Mode 

mos_corner=tt 


0 

R216 

C1 C2 C3 C4 C5 

R217 

1k 

1k 

0 

0 0 

M215 

N_12_MML130E 

L= 0.12u 

W= 10u 

M=5 

M=5 

W= 10u 

L= 0.12u 

N_12_MML130E 

M218 

0 

in 

inb 

gnd_bbrx 

gnd_bbrx 

C1 

C2 

C3 

C4 

C5 

DC=if(ctrl==1, 1.2, 0) DC=if(ctrl==2, 1.2, 0) DC=if(ctrl==3, 1.2, 0) D C =if(c trl==4, 1.2, 0) DC=if(ctrl==5, 1.2, 0) 

V706 

DC=if(av1_ctrl== 1, 1.2, 0) 

V707 

V243 

DC=if(av1_ctrl== 2, 1.2, 0) 

V708 

V247 

DC=if(av2_ctrl== 1, 1.2, 0) 

V255 

V258 

DC=0.6 

DC=0.6 

ACMAG=0.5 ACMAG=0.5 

ACPHASE=1 ACPHASE=180 

V709 

V248 

DC=if(av2_ctrl== 2, 1.2, 0) 

V710 

V251 

DC=if(av2_ctrl== 3, 1.2, 0) 

CMOS Analog Baseband Filter & AGC 

Full Circuit Verification 

0 

V711 

DC=if(av2_ctrl== 4, 1.2, 0) 

0 

R207 

R208 

Av1_c1 

Av1_c2 

V712 

DC= if(av3_ctrl= =1, 1.2, 0) 

1k 

1k 

Av2_c1 

Av2_c2 

Av2_c3 

Av2_c4 

0 

V713 

DC= if(av3_ctrl= =2, 1.2, 0) 

M206 

N_12_MML130E 

L= 0.12u 

W= 10u 

M=5 

M=5 

W= 10u 

L= 0.12u 

CT_AnaFilt_DC_cut2 

N_12_MML130E 

M209 

Av3_c1 

Av3_c2 

Av3_c3 

Av3_c4 

0 

V714 

DC=if(av3_ctrl== 3, 1.2, 0) 

gnd_bbrx 

gnd_bbrx 

Av4_c1 

Av4_c2 

Av4_c3 

0 

V715 

Av4_c4 

DC= if(av3_ctrl= =4, 1.2, 0) 

R203 

R204 

Av5_c1 

Av5_c2 

Av5_c3 

Av5_c4 

1k 

1k 

0 

V716 

DC=if(av4_ctrl== 1, 1.2, 0) 

out 

outb 

M202 

N_12_MML130E 

L= 0.12u 

W= 10u 

M=5 

M=5 

W= 10u 

L= 0.12u 

N_12_MML130E 

M205 

0 

V717 

out 

outb 

DC=if(av4_ctrl= = 2, 1.2, 0) 

0 

gnd_bbrx 

gnd_bbrx 

V V 

Control 

Voltage 

V718 

DC=if(av4_ctrl== 3, 1.2, 0) 

R190 

R191 

0 

V719 

DC= if(av4_ctrl= =4, 1.2, 0) 

1k 

1k 

gnd_bbrx V263 

M189 

N_12_MML130E 

L= 0.12u 

W= 10u 

M=5 

M=5 

W= 10u 

L= 0.12u 

N_12_MML130E 

M192 

0 

0 

DC=0 

V720 

DC= if(av5_ctrl= =1, 1.2, 0) 

vdd_bbrx 

0 

V583 

DC=1.2 

0 

V721 

DC=if(av5_ctrl== 2, 1.2, 0) 

gnd_bbrx 

gnd_bbrx 

0 

V722 

DC= if(av5_ctrl= =3, 1.2, 0) 

R178 

R179 

1k 

1k 

0 

V723 

DC=if(av5_ctrl== 4, 1.2, 0) 

M177 

N_12_MML130E 

L= 0.12u 

W=10u 

M=5 

M=5 

W= 10u 

L= 0.12u 

N_12_MML130E 

M182 

gnd_bbrx 

gnd_bbrx 

in 

inb 

R158 

C156 

C157 

R159 

1k 

0.1p 

0.1p 

1k 

R235 

R236 

U4 

Diif_Amp3 

outb 

out 

1k 

1k 

in 

inb 

Av1_c1 

Av1_c2 

Av1_c1 

Av1_c2 

C222 

outb 

out 

C223 

10p 

U5 

Diif_Amp3 

10p 

Av2_c1 

Av2_c2 

Av2_c1 

Av2_c2 

in 

inb 

Av2_c3 

Av2_c4 

Av2_c3 

Av2_c4 

R226 

R231 

Av3_c1 

Av3_c2 

Av3_c1 

500k 

500k 

Av3_c2 

U3 

CT_AnalogFilter4 

Av3_c3 

Av3_c4 

Av3_c3 

Av3_c4 

Av4_c1 

Av4_c2 

Av4_c3 

Av4_c1 

Av4_c2 

Av4_c4 

Av4_c3 

Av4_c4 

Av5_c1 

Av5_c2 

Av5_c3 

Av5_c1 

Av5_c2 

Av5_c3 

Av5_c4 

Av5_c4 

out 

outb 

out 

outb

inb 

in 

Av1_c1 

Av1_c2 

i 

VCR_1stage1 

U21 

Av1_C1 

Av1_ C1 

Av1_c2 

Av1_ c2 

o 

i o 

U22 

VCR_1stage1 

R6 

C7 

in 

inb 

R_filt 

C_filt 

U6 

Diif_Amp4 

C13 

R10 

C_filt 

R_filt 

outb 

out 


Full Circuit Verification 

i 

i 

U29 VCR_2stage_b1 

Av2_c1 

Av2_c2 

i o 

Av2_c1 Av2_c2 Av2_c3 Av2_c4 

Av2_ c1 

Av2 _c2 

Av2 _c1 

U12 VCR_2stage_a1 

Av2_c2 

Av2_c1 

Av2_c3 

Av2_c4 


Av2_ c2 

Av2 _c4 

Av2 _c3 

Av2_c4 

Av2_c3 

Av2_ c3 

Av2_ c4 

o 

i o 


o 

Av2_c1 

L=0.12u 

W=10u 

M=5 

Av2_c2 

L=0.12u 

W=10u 

M=5 

gnd_bbrx 

gnd_bbrx 

C29 

C_filt 

U7 

Diif_Amp4 

in 

outb 

inb 

out 

i o 

Av2_c3 

L=0.12u 

W=10u 

M=5 

Av2_c4 

L=0.12u 

W=10u 

M=5 

gnd_bbrx 

gnd_bbrx 

M313 

N_12_MML130E 

M314 

N_12_MML130E 

M319 

N_12_MML130E 

M324 

N_12_MML130E 

C30 

R312 

R315 

C_filt 

R_0dB 

R_0dB/(10^(step_db/20)) 

R320 

R_0dB/(10^(2*step_db/20)) 

R325 

R_0dB/(10^(3*step_db/20)) 

i 

i 


Av2_c2 

Av2_c1 

Av2_c2 

Av2_c1 

Av2_c4 

Av2_c3 


Av2_c1 

Av2_c2 

Av2_c4 

Av2_c3 

Av2_c3 

Av2_c4 


o 

o 

i o 


Av2_ c1 

Av2_ c2 

Av2_ c3 

Av2_ c4 

i o 


R446 

v dd_bbrx 

30k 

M444 

N_12_MML130E 

gnd_bbrx 

L=0.24u 

W=2u 

M=1 

C46 

in 

inb 

C_filt 

U8 

Diif_Amp4 

C47 

C_filt 

outb 

out 

i 

i 


Av2_c2 

Av2_c1 

Av2_c2 

Av2_c1 

Av2_c4 

Av2_c3 


Av2_c1 

Av2_c2 

Av2_c4 

Av2_c3 

Av2_c3 

Av2_c4 

o 

o 

i o 


C_filt 

U9 

Diif_Amp4 

Av4_c1 Av4_c2 


Av5_c3 Av5_c4 

Av2_ c1 

Av2_ c2 

Av2_ c3 

Av2_ c4 

i o 


v dd_bbrx v dd_bbrx 

M428 

M431 

in 

N_12_MML130E 

N_12_MML130E 

inb 

L=0.12u 

W=2.4u 

M=5 

M495 

P_12_MML130E 

L=0.12u 

W=4u 

M=1 

gnd_bbrx gnd_bbrx 

M437 

N_12_MML130E 

L=0.24u 

W=5u 

M=5 

gnd_bbrx 

M492 

P_12_MML130E 

L=0.12u 

W=4u 

M=1 

L=0.12u 

W=2.4u 

M=5 

C64 

in 

inb 

C65 

C_filt 

outb 

out 

M502 

N_12_MML130E 

L=0.12u 

W=2.4u 

M=5 

i 

i 


Av2_c2 

Av2_c1 

Av2_c2 

Av2_c1 

Av2_c4 

Av2_c3 


Av2_c1 

Av2_c2 

Av2_c4 

Av2_c3 

Av2_c3 

Av2_c4 

o 

o 

i o 


Av2_ c1 

Av2_ c2 

Av2_ c3 

Av2_ c4 

i o 


gnd_bbrx gnd_bbrx 

gnd_bbrx 

R83 

C84 

R_filt 

C_filt 

U10 

Diif_Amp4 

in 

inb 

v dd_bbrx v dd_bbrx 

M506 

P_12_MML130E 

L=0.12u 

W=4u 

M=1 

M504 

N_12_MML130E 

L=0.24u 

W=5u 

M=5 

M505 

P_12_MML130E 

L=0.12u 

W=4u 

M=1 

C85 

R86 

C_filt 

R_filt 

M503 

N_12_MML130E 

L=0.12u 

W=2.4u 

M=5 

outb 

out 

outb out 

outb 

out


Full Circuit Verification

Modifications 


UWB Analog BB filter 

& Gain Control Stage

HPF, LPF and 

VGA I & Q 

Stages 

UWB Analog BB filter & Gain Control Stage 

LPF_Vtun 

AGND 

AVDD 

BBIp 

BBIn 

BBqn 

BBqp 

AVDD 

LPF_Vtun 

U8 

HPF7 

VDD I250u 

Inp 

Outp 

Inn 

Inp 

PD 

VDD 

Outn 

GND 

PD GND 

Inn Outn 

HPF7 

V1560 V1563 V1564 V1565 V1566 V1567 

Outp 

I250u 

U15 

PD 

U9 

LPF3 

Vtun VDD 

Inp Outp 

Inn 

Vctrl_1p 

Vctrl_1n 

Inn 

Inp 

Vtun 

LPF3 

U5 

Outn 

GND 

GND 

Outn 

Outp 

VDD 

I350u 

Vin 

Vctrlp 

Vinn 

Vctrlp 

Stg8 

Vctrln 

Vctrln 

VDD 

Vout 

Voutn 

GND 

GND 

VDD 

U10 

Vinn Voutn 

GNDdump 

I50u_cm1 I350u_stg2i 

AVDD 

I250u_EFI I350u_Stg1II50u_CMamp1 

I350u_Stg2I I500u_tia1 I300u_TRAI 

PD U12 

BB_Bias2 

I250u_EFQ I350u_Stg1QI50u_CMamp3I350u_Stg2Q 

I500u_tia2I350u_TRAQ 

AGND 

Vin 

Stg8 

Vout 

I350u 

I50u_cm3 

I350u_stg2q 

GNDdump 

U6 

Vbias 

Vcm_ref 

V 

U13 

VDD 

Inp Outp 

HPF6 

Inn Outn 

Bias 

Bias 

Inn Outn 

Inp 

HPF6 Outp 

VDD 

V 

U7 

E1921 

Vctrl_2p 

0 

Vctrl_2n 

I50u_cm1 

I350u_stg2i 

U14 

I50u_cm I350u VDD 

Vin Ioutp 

Stg9 

Vinn Ioutn 

Vctrlp 

Vctrln 

CMref 

V 

GND 

GND 

CMref 

Vctrln 

Vctrlp 

Vinn Ioutn 

GNDdump 

Stg9 

Vin Ioutp 

I50u_cm I350u VDD 

I50u_cm3 

I350u_stg2q 

V 

GNDdump 

U11 

V 

E1897 

V 

0 

I500u_tia I300u VDD 

Iinp 

OpStg8 

Voutp 

Iinn Voutn 

PD GND 

PD 

Iinn 

OpStg8 Iinp 

V 

U16 

GND 

Voutn 

Voutp 

I500u_tia I300u VDD 

U17 

E1910 

0 

V 

IOutp IOutn GNDdump 

Qoutn QOutp 

V

In p 

In n 

Ioutn 

Ioutp 

Vinp 

Vinn 

GND 

Vtune 

Vtune 

GND 

U55 

Gm_Nauta5 

Vdd 

U54 

Gm_Nauta5 

Vdd 

Vinp 

Vinn 

Ioutn 

Ioutp 

UWB Analog BB filter (LPF portion) 

mimcaps_rf 


250MHz Cutoff 5 th Order Chebychev 

Low Pass Gm-C Filter 

M=1 

w=48u 

l=48u 


mimcaps_rf 

l=48u 

w=48u 

M=1 

Vinp 

Vinn 

GND 

Vtune 

Ioutn 

Ioutp 

U42 

Gm_Nauta5 

Vdd 

Vdd 

Vtune 

GND 

Ioutn 

Ioutp 

U41 

Gm_Nauta5 

Vinp 

Vinn 

mimcaps_rf 


M=2 

w=25u 

l=30u 


mimcaps_rf 

l=30u 

w=25u 

M=2 

Cinductor Cpole 

Ioutn 

Ioutp 

Vinp 

Vinn 

GND 

Vtune 

Vdd 

Vtune 

GND 

U38 

Gm_Nauta5 

U53 

Gm_Nauta5 

Vdd 

Vinp 

Vinn 

Ioutn 

Ioutp 

VDD 

mimcaps_rf 


GND 

M=2 

w=50u 

l=50u 


mimcaps_rf 

l=50u 

w=50u 

M=2 

Cinductor2 

Vtun 

Final Design 

Cpole = 1.7pF 

Cinductor = 1.2pF 

Cinductor2 = 3pF 

Vtun=1.18V 

gml=0.25um 

gmw=5um 

count=1 

Vinp 

Vinn 

GND 

Vtune 

Ioutn 

Ioutp 

U57 

Gm_Nauta5 

Vdd 

Vdd 

Vtune 

GND 

Ioutn 

Ioutp 

U56 

Gm_Nauta5 

Vinp 

Vinn 

mimcaps_rf 

c_ to t_ m=1.6 0 2 p 

M=2 

w=2 5 u 

l=3 0u 


mimcaps_rf 

l=3 0u 

w=2 5 u 

M=2 

Ioutn 

Ioutp 

Vinp 

Vinn 

GND 

Vtune 

Vtune 

GND 

U44 

Gm_Nauta5 

Vdd 

U47 

Gm_Nauta5 

Vdd 

Vinp 

Vinn 

Ioutn 

Ioutp 

mimcaps_rf 


M=1 

w=48u 

l=48u 


mimcaps_rf 

l=48u 

w=48u 

M=1 

Cpole Cinductor 

Vinp 

Vinn 

GND 

Vtune 

Ioutn 

Ioutp 

U43 

Gm_Nauta5 

Vdd 

Vdd 

Vtune 

GND 

Ioutn 

Ioutp 

U45 

Gm_Nauta5 

Vinp 

Vinn 

rnhr_rf 


rnhr_rf 


l=10.3u 

w=2u 

m=4 

l=10.3u 

w=2 u 

m=4 

Outp Outn

Gm Cell used in UWB Analog BB LPF filter 

Vinp 

Vtune Vdd 

Vinn 

GND 

M328 

P_12_MML130E 

L=0.25u 

W=10u 

M=1 

M327 

N_12_MML130E 

L=0.25u 

W=5u 

M=1 

M330 

P_12_MML130E 

L=0.25u 

W=10u 

M=1 

M329 

N_12_MML130E 

L=0.25u 

W=5u 

M=1 

Vdd 

GND 

Vdd 

GND 

Gm Unit Cell 

M332 

P_12_MML130E 

L=0.25u 

W=10u 

M=1 

M331 

N_12_MML130E 

L=0.25u 

W=5u 

M=1 

Vdd Vtune Vtune Vdd 

M334 

P_12_MML130E 

L=0.25u 

W=10u 

M=1 

M333 

N_12_MML130E 

L=0.25u 

W=5u 

M=1 

M338 

P_12_MML130E 

L=0.25u 

W=10u 

M=1 

M337 

N_12_MML130E 

L=0.25u 

W=5u 

M=1 

GND GND GND GND 

M336 

P_12_MML130E 

L=0.25u 

W=10u 

M=1 

M335 

N_12_MML130E 

L=0.25u 

W=5u 

M=1 

Ioutn 

Ioutp

1 st Stage of Gain Control 

VDD 

Vctrlp 

Vctrln 

Vin Vinn 

Voutn 

Vout 

GNDdump GNDdump 

GND 

I350u 

n_12_rf 

nf=16 

lf=0.2u 

wf=7.2u 

M=2 

wt=115.2u 

n_12_rf 

nf=16 

lf=0.2u 

wf=7.2u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=1 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=1 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=2 

wt=115.2u 

n_12_rf 

nf=8 

lf=0.2u 

wf=7.2u 

M=2 

wt=57.6u 

n_12_rf 

nf=8 

lf=0.2u 

wf=7.2u 

M=2 

wt=57.6u 

n_12_rf 

nf=8 

lf=0.2u 

wf=7.2u 

M=1 

wt=57.6u 

n_12_rf 

nf=8 

lf=0.2u 

wf=7.2u 

M=2 

wt=57.6u 

rnhr_rf 


rnhr_rf 


rnhr_rf 


Bias 

Bias 

1 st VGA Stage

UWB Analog BB filter (HPF portion) 

Passive 2 nd High Pass Filter 

Inp 

Inn 

l=100u 

w=60u 

M=2 

M=2 

w=60u 

l=100u 

mimcaps_rf 



mimcaps_rf 

rnhr_rf 

r_zbt_m=9.96k 

rnhr_rf 

r_zbt_m=9.96k 

l=20u 

w=2u 

m=1 

l=20u 

w=2u 

m=1 

Bias 

m=1 

w=2u 

l=20u 

m=1 

w=2u 

l=20u 

r_zbt_m=9.96k 

rnhr_rf 

r_zbt_m=9.96k 

rnhr_rf 

Outp 

VDD Outn

2 nd Stage of Gain Control 

VDD 

Vctrlp 

Vctrln 

Vin Vinn 

Ioutn 

GNDdump GNDdump 

GND 

Ioutp 

CMref 

I350u 

I50u_cm 

n_12_rf 

nf=16 

lf=0.2u 

wf=7.2u 

M=2 

wt=115.2u 

n_12_rf 

nf=16 

lf=0.2u 

wf=7.2u 

M=2 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.15u 

wf=9.6u 

M=1 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.15u 

wf=9.6u 

M=1 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.15u 

wf=9.6u 

M=7 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.15u 

wf=9.6u 

M=7 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.3u 

wf=9.6u 

M=14 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.3u 

wf=9.6u 

M=14 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=10 

wt=115.2u 

p_12_rf 

nf=12 

lf=0.2u 

wf=9.6u 

M=10 

wt=115.2u 

n_12_rf 

nf=10 

lf=0.2u 

wf=7.2u 

M=2 

wt=72u 

n_12_rf 

nf=10 

lf=0.2u 

wf=7.2u 

M=2 

wt=72u 

n_12_rf 

nf=10 

lf=0.2u 

wf=7.2u 

M=1 

wt=72u 

n_12_rf 

nf=8 

lf=0.2u 

wf=7.2u 

M=2 

wt=57.6u 

n_12_rf 

nf=16 

lf=0.3u 

wf=7.2u 

M=4 

wt=115.2u 

n_12_rf 

nf=16 

lf=0.3u 

wf=7.2u 

M=4 

wt=115.2u 

l=5.3u 

w=2u 

m=20 

rnhr_rf 


Vsense 

Vref 

GND 

Vout 

VDD 

I50u_s 

U91 

CMamp5 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

l=10u 

w=1u 

m=1 

rnhr_rf 

r_zbt_m=10.089k 

V 

Bias 

Bias 

Vfb Vfb 

net_cm 

net_cm 

2 nd VGA Stage

PD 

GND 

VDD 

INV 

VSS 

U276 

INV8 

A Y 

VDD 

I500u_tia 

Iinp 

Output stage of VGA 

Output Transimpedance Stage 

p_12_rf 

lf=0.2u 

wf=3.84u 

nf=16 

M=1 

wt=61.44u 

VDD 

INV 

VSS 

U275 

INV8 

A Y 

2.75mA 

p_12_rf 

lf=0.2u 

wf=9.6u 

nf=16 

M=2 

wt=153.6u 

n_12_rf 

lf=0.2u 

wf=4u 

nf=16 

M=4 

wt=64u 

n_12_rf 

lf=0.2u 

wf=5u 

nf=16 

M=1 

wt=80u 

n_12_rf 


rnhr_rf 

lf=0.2u 

wf=5u 

nf=16 

M=1 

wt=80u 

w=2u 

l=6.4u 

m=4 

n_12_rf 

lf=0.2u 

wf=2u 

nf=8 

M=2 

wt=16u 

n_12_rf 

lf=0.2u 

wf=5u 

nf=16 

M=2 

wt=80u 

Voutn 

Rin = 73 Ohms 

Rt = 63dB 

I300u 

Voutp 

n_12_rf 

lf=0.2u 

wf=5u 

nf=16 

M=2 

wt=80u 

n_12_rf 

lf=0.2u 

wf=5u 

nf=16 

M=1 

wt=80u 

m=4 

w=2u 

l=6.4u 


rnhr_rf 

n_12_rf 

lf=0.2u 

wf=2u 

nf=8 

M=2 

wt=16u 

n_12_rf 

lf=0.2u 

wf=5u 

nf=16 

M=1 

wt=80u 

p_12_rf 

lf=0.2u 

wf=9.6u 

nf=16 

M=2 

wt=153.6u 

n_12_rf 

lf=0.2u 

wf=4u 

nf=16 

M=4 

wt=64u 

I500u_tia 

Iinn 

n_12_rf 

lf=0.2u 

wf=5u 

nf=16 

M=1 

wt=80u 

I1dB = 330uApk 

I1dB limited by input stage 

I300u

Bias Circuitry 

Baseband Bias Block 

AVDD 

AGND 

I50u_CMamp1 I500u_tia1 I50u_CMamp3 I500u_tia2 

Vbias 

Vcm_ref 

I250u_EFI I250u_EFQ I350u_Stg1I I350u_Stg1Q I350u_Stg2I I350u_Stg2Q I300u_TRAI I350u_TRAQ 

PD 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

n_bpw_12_rf 

nf=16 

lf=0.2u 

wf=2u 

M=1 

wt=32u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

l=7.7u 

w=2u 

m=2 

rnhr_rf 


p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

l=7.7u 

w=2u 

m=2 

rnhr_rf 


Vsense 

Vref 

Vout 

U213 

BuffAmp2 

Vsense 

Vref 

Vout 

U214 

BuffAmp2 

l=6.1u 

w=2u 

m=2 

rnhr_rf 


p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=5 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=7 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=7 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=6 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=5 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=7 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=7 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=6 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=1u 

M=1 

wt=4u 

n_bpw_12_rf 

lf=0.2u 

wf=1u 

n_bpw_12_rf 

lf=0.2u 

wf=1u 

n_bpw_12_rf 

lf=0.2u 

wf=1u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

INV 

VD D 

VSS 

U223 

INV4 

INV 

VD D 

VSS 

U224 

INV4 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

p_12_rf 

nf=4 

lf=0.3u 

wf=1.6u 

M=2 

wt=6.4u 

PDbb 

PDb 

100u +/-30% 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u 

n_bpw_12_rf 

nf=4 

lf=0.2u 

wf=2u 

M=1 

wt=8u

Common Mode Aux. Amplifier 

GND 

VDD 

Common Mode Aux. Amplifier 

Vref 

Vsense 

I50u_src 

n_12_rf 

lf=0.3u 

wf=7.2u 

nf=16 

M=1 

wt=115.2u 

n_12_rf 

lf=0.3u 

wf=7.2u 

nf=8 

M=1 

wt=57.6u 

p_12_rf 

lf=0.3u 

wf=9.6u 

nf=16 

M=1 

wt=153.6u 

n_12_rf 

lf=0.3u 

wf=7.2u 

nf=16 

M=2 

wt=115.2u 

p_12_rf 

lf=0.3u 

wf=9.6u 

nf=16 

M=1 

wt=153.6u 

Gv=40dB 

3dB BW=1.8MHz 

GM=15dB 

PM=79deg 

m=3 

w=1.5u 

l=5u 


rnhr_rf 

n_12_rf 

lf=0.3u 

wf=7.2u 

nf=8 

M=1 

wt=57.6u 

M=1 

w=30u 

l=30u 

p_12_rf 

lf=0.25u 

wf=9.6u 

nf=16 

M=1 

wt=153.6u 


mimcaps_rf 

l=10u 

w=2u 

m=1 

rnhr_rf 

r_zbt_m=4.87k 

Vout

Section 3: Results 

Analog Baseband


Analog Baseband 

Nominal Signal Level = 707uVrms for this gain setting 

This means that a peak-to-average of 16dB can be tolerated.



Nominal Signal Level = 22mVrms for this gain setting (assuming 20dB LNA gain step) 

This means that a peak-to-average of 12dB can be tolerated.



This plot corresponds to the case where the LNA is in low gain and the RF 

Input power is -30dBm



This plot corresponds to the case where the LNA is in high gain and the RF 

Input power is -74dBm



NOTE: Rise in Group Delay at Low Frequencies is due to High Pass Filtering

Modification Summary for Analog BB 

Filter 

� Divide previous one stage arrangement into multiple stages 

in cascade 

� Filter topology has been changed to ladder type with Gm-C 

implementation 

� Change the digital control scheme into analog voltage 

controlled one 

� Change the low frequency rejection from servo-loop to RC 

high-pass filter.

Layout for Analog Gm-C Filter

Full-Chip Verification for Mboa-compliant UWB Radio

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