Full-Chip Verification for Mboa-compliant UWB Radio

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RFIC Design Flow Whitepaper � UMC and Ansoft Co-author new Design Flow for RFIC � Whitepaper Details: � Design Capture � Circuit Simulation � On-chip Passive Simulation � Layout Extraction � Packaging � Full-chip Verification � Available at UMC and Ansoft Website
Conclusion � UMC and Ansoft teamed to develop a design solution for complex RFICs that include custom RF, analog, and mixed-signal circuits. � On-chip passive modeling � Circuit design and simulation � Full-chip verification � UWB radio project has been transformed from initial circuit designs to production-ready circuits and layout. � Expect test chips back from fabrication in October � RFIC Design flow provides platform for developing advanced RFICs: � UMC’s advanced RF CMOS semiconductor process � Electronic design automation (EDA) tools from Ansoft and other established vendors � Design Flow leverages UMC’s production-proven 0.13 um RFCMOS process and advanced circuit simulation and electromagnetic extraction tools from Ansoft. � Additional fidelity in modeling, simulation, and verification coverage can be gained by following this advanced design flow.
Page 1 and 2: Full-chip Verification for MBOA-com
Page 3 and 4: UMC - Ansoft UWB Project � Circui
Page 5 and 6: Circuit Modification Summary* � T
Page 7 and 8: index=8 l=80.8u w=74.2u c_pad=38.6f
Page 9 and 10: Layout for UWB T/R Switch
Page 11 and 12: � UMC and Ansoft provide referenc
Page 13 and 14: RFIC Design Challenges � Time- an
Page 15 and 16: Monolithic ICs are Produced Using C
Page 17 and 18: HFSS - 3D Electromagnetics Industry
Page 19 and 20: System Design and Behavioral Modeli
Page 21 and 22: � Spiral Design Kit Contents: Ans
Page 23 and 24: HFSS/Nexxim Dynamic Link
Page 25 and 26: UMC 0.13um 1.2V/3.3V Twin, Tripple
Page 27 and 28: UMC 0.13um 1.2V/3.3V Twin, Tripple
Page 29 and 30: VCO Circuit Using HFSS Post-Layout
Page 31 and 32: Enlarge the Size of Negative Genera
Page 33 and 34: Exposed Die Paddle Die Vias Package
Page 35 and 36: BSRC RANDOM NB=112*2*symbols/2.5 BR
Page 37: IFFT FFTL=128 FFT FFTL=128 I Q M=4
Page 42 and 43: Previous Work for UWB T/R Switch
Page 44 and 45: sw=0, Receiving UWB T/R Switch from
Page 46 and 47: Modifications for UWB T/R Switch
Page 48 and 49: sw=0, Receiving Final Result for UW
Page 50 and 51: Modification Summary for T/R Switch
Page 52 and 53: Previous Work for UWB LNA
Page 54 and 55: UWB LNA from Previous Work
Page 56 and 57: Modifications for UWB LNA_v1
Page 58 and 59: Final Result for UWB LNA_v1 FF, 1.3
Page 60 and 61: Modification Summary for LNA_v1 �
Page 62 and 63: Addition for UWB Active Balun (no p
Page 64 and 65: Broadband Active Balun Added Phase
Page 66 and 67: Previous work & Modifications for U
Page 68 and 69: IQ Modulator Refinement vdd_mix gnd
Page 70 and 71: Modification Summary for IQ Modulat
Page 72 and 73: Original work of UWB Synthesizer
Page 74 and 75: Complex Signal Spectrum for Synthes
Page 76 and 77: Complex Signal Spectrum for Synthes
Page 78 and 79: Synthesizer Settling
Page 80 and 81: Spectrum Directly from Nexxim Ch2
Page 82 and 83: Modifications for UWB Synthesizer
Page 84 and 85: Synthesizer Schematic
Page 86 and 87: UMC TT Ch2 Spectrum
Page 88 and 89:
Simulation Results TT: MOS=tt, res=
Page 90 and 91:
Layout for Synthesizer
Page 92 and 93:
0 V240 0 0 0 0 0 0 in inb U MC 0.13
Page 94 and 95:
CMOS Analog Baseband Filter & AGC F
Page 96 and 97:
HPF, LPF and VGA I & Q Stages UWB A
Page 98 and 99:
Gm Cell used in UWB Analog BB LPF f
Page 100 and 101:
UWB Analog BB filter (HPF portion)
Page 102 and 103:
PD GND VDD INV VSS U276 INV8 A Y VD
Page 104 and 105:
Common Mode Aux. Amplifier GND VDD
Page 106 and 107:
Section 3: Results Analog Baseband
Page 108 and 109:
Page 110 and 111:
Page 112:
Layout for Analog Gm-C Filter
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Full-Chip Verification for Mboa-compliant UWB Radio

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