Counter & 7-Seg. Disp. Decoder

LAB-III
1. Write a VHDL code to implement the circuit shown in Figure1.
CLK
D0
S0
S1
7- Segment LED
Counter
D1
D2
LED
Decoder
S2
S3
S4
S5
S2
S3
S4
S1
D3
S5
S6
S0
Figure 1: High level diagram of Counter Implemented on the 7-Segment Display
2. Write the VHDL code for LED decoder and verify your code using the
Simulation tool.
3. Create a schematic symbol for LED Decoder using the “Create Schematic
Symbol” option in the synthesize design step.
4. Write Behavioral VHDL code for a 28 bit counter with clock as the input and the
most significant 4 bits as the outputs.
5. Verify your code using the simulation tool and then create a schematic symbol for
the counter.
6. Open the Schematic editor and then make a design using the LED decoder and
the counter symbols. The input to the counter should be given using an input
buffer (IBUFG). The output of the decoder is passed through and output buffer
(OBUF). Using the symbols, create the complete model for an Up-counter to be
displayed on a seven segment LED display.
Hint: The truth table for the LED decoder is given below
S6

For example: To display the Hex number 0, the bits S6S5S4S3S2S1S0= 11101112 .