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Logic Implementation Using Programmable ROMs

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<strong>Logic</strong> <strong>Implementation</strong><br />

<strong>Using</strong> <strong>Programmable</strong> <strong>ROMs</strong><br />

CSET 4650<br />

Field <strong>Programmable</strong> <strong>Logic</strong> Devices<br />

Dan Solarek


<strong>Programmable</strong> Read Only Memory<br />

A ROM is a memory device<br />

that holds a fixed, addressable<br />

data set<br />

A PROM may be programmed<br />

by the designer<br />

UV erasable<br />

PROM<br />

2


<strong>Programmable</strong> Read Only Memory<br />

Typical uses include:<br />

Code converters<br />

Character generators<br />

Data storage tables<br />

Program stores<br />

Loaded with tabular data –<br />

not Boolean equations<br />

e.g., a truth table<br />

3


Conceptual PROM Architecture<br />

32x8 PROM<br />

5-to to-32 32<br />

decoder<br />

8 OR gates<br />

with 32 inputs<br />

32x8 internal<br />

programmable<br />

connections<br />

k = 5 2 k = 32<br />

programmable OR connections<br />

output word (8-bits)<br />

4


Conceptual PROM Architecture<br />

A PROM has a fixed AND array (that<br />

decodes the memory address) followed by<br />

a programmable OR array (outputs)<br />

For each of a given set of input<br />

combinations (address), it generates a<br />

multi-bit multi bit value which has been<br />

programmed into the device<br />

5


<strong>Using</strong> P<strong>ROMs</strong> as PLDs<br />

The output functions need to be expressed<br />

in canonical minterm form for PROM<br />

implementation<br />

every input variable appears in each product<br />

term in its true or inverted form<br />

Each minterm is used to represent an<br />

address<br />

Each address generates a multi-bit multi bit output<br />

6


Realistic PROM Architecture<br />

A PROM has a fixed AND<br />

array and a programmable<br />

OR array<br />

Remember, we are only<br />

programming the<br />

CONNECTIONS to the<br />

OR gates<br />

AND gate connections are<br />

all possible combinations<br />

decoder logic<br />

7


Simplified PROM Architecture<br />

Inputs A and B<br />

true and inverted<br />

Outputs Y and Z<br />

e.g., two functions<br />

<strong>Programmable</strong><br />

connections to OR<br />

gates<br />

0 0<br />

0 1<br />

1 0<br />

1 1<br />

8


Example 7-11 7 11 from Sandige<br />

Binary to hex character<br />

generator<br />

<strong>Using</strong> a seven-segment<br />

seven segment<br />

display device and the<br />

character scheme at right<br />

OE<br />

OF<br />

OC<br />

OA<br />

OG<br />

OD OB<br />

9

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