Post Synthesis Simulation Using NCLaunch(NC ... - DAIICT Intranet

Work station access through NFS :
Open the terminal:
cd /mnt
mkdir cadence
mount 10.100.57.201:/opt/Cadence /mnt/cadence
Post Synthesis Simulation Using NCLaunch(NC-Sim):
cd mnt/cadence/Cadence/project/vtvtsoc/
mkdir netlist_simulate
cd netlist_simulate
For this tutorial you will need a few extra files, please download the following files in the
netlist_simulate directory : counter_synth.v , counter_test.v, osu018_stdcells.v(these files are
available on the server at /mnt/cadence/Cadence/project/vtvtsoc/netlist_simulate)
From the netlist_simulate directory type: nclaunch &
The command nclaunch & starts NCSim in the background and you should get the NCLaunch
startup window.

Now we need to set the work directory and create a work library (to contain your circuits) so go
to File -> Set Design Directory from the File menu of the Menu Bar.
First set the design directory to the netlist_simulate directory that you just created (this should
be automatic if you started NCLaunch from the tutorial directory as described here): then click
on Create cds.lib File and click Save (you should only need to do this once when you run the
tool for the first time).
and finally click OK to Include default libraries.
Finally, making sure that worklib has appeared for Work Library click OK on the Set Design
Directory pop-up window. Please notice that the Library Browser window (right side) of
NCLaunch has become populated now.

There are 3 steps that we need to perform now (remember we chose multistep):
Compile (ncvlog)
Elaborate (ncelab)
Simulate (ncsim)
1. In order to compile you first need to select the various files in the File Browser (left side) by
clicking on the mouse left button (simultaneously press on shift for multiple selections), then click
on the corresponding buttons in the Menu Bar (in this case the ncvlog button) or explicitly go to
Tools -> Verilog Compiler.
You can edit the verilog files from File -> Edit.
2. In order to elaborate first click on the + in front of the worklib on the Library Browser
window in order to see its contents:

Now select the top file under worklib (counter_test) then click on the NCElab button in the
Menu (by right click on counter_test you will get a option NCElab), or go to Tools ->
Elaborator NCElab.

3. To simulate click on the + sign in front of the Snapshots library to expand its contents, then
select worklib.counter_test:module and click on NCsim (by right click on
worklib.counter_test:module you will get a option NCsim) or go to Tools -> Simulator. This
will launch the Simvision Design Browser and Console windows:
4. To see the results of your simulation right click on counter_test and choose send
waveforms to browser as option.

After running the simulation you will get the wave form something like this.
References:
http://www.ee.virginia.edu/~mrs8n/soc/sim_tutorial.html.