Chapter 5

CSIT 255 Computer Organization & Architecture by Dr. Ali Hakan ULUSOY 


Eastern Mediterranean University 

School of Computing and Technology 

CSIT 255 

Computer Organization & Architecture 

INTERNAL MEMORY 

Types of Random-Access Semiconductor Memory 

ULUSOY 

Hakan Ali Dr. by Architecture & Organization Computer 255 

o No refresh is needed to retain data. 

o Generally faster than dynamic RAM. 3 

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Random-Access Memory (RAM) 

• It is possible both to read data from memory and to write new data into 

memory easily and rapidly. 

• Both reading and writing are accomplished through use of electrical 

signals. 

• It is volatile. RAM can only be used for temporary storage with a 

constant power supply. 

• Types of RAM are 

Dynamic RAM (DRAM) 

o Stores data as charge on capacitors. 

o Tend to discharge over time. 

o Require periodic charge refreshing to maintain data storage. 

o More dense and less expensive than static RAM. 

Static RAM (SRAM) 

o Stores data in traditional flip-flop gates. 

o Holds its data as long as power is supplied to it. 

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Semiconductor Main Memory: Organization 

All semiconductor memory cells: 

• Exhibit 2 stable (or semi-stable) which can represent binary 1 or 0. 

• Are capable of being written into (at least once) to set states. 

• Are capable of being read to sense states. 

Most commonly cell has three functional terminals capable of carrying an 

electrical signal. 

• Select terminal. Selects a memory cell for a read or write operation. 

• Control terminal. Indicates read or write. 

• Other terminal 

For writing. Provides an electrical signal that sets state of cell to 1 or 0. 

For reading. That terminal is used for output of cell’s state. 


• Dynamic RAM (DRAM). Is used for main 

memory. 

• Static RAM (SRAM). Is faster, more expensive 

and less dense than DRAM. It is used for cache 

memory. 

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Structure of Dynamic RAM (DRAM) 

ULUSOY 

Address line is activated when bit value 

from this cell is to be read or written. 

Hakan Ali Dr. 

Transistor acts as a switch that is 

by 

• closed (allowing current to flow) if a 

voltage is applied to address line. 

• open (no current flows) if no voltage is 

present on address line. 

Architecture & 

For write operation, a voltage signal is applied to bit line (high 

voltage=1 and low voltage=0). A signal is then applied to address line, 

allowing a charge to be transferred to capacitor. 

Organization 

For read operation, when address line is selected, transistor turns on 

and charge stored on capacitor is fed out onto a bit line and to a sense 

Computer 

amplifier. Sense amplifier compares capacitor voltage to a reference 

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value and determines if cell contains logic 1 or o. Read out from cell 

discharges capacitor, which must be restored to complete operation. 5 

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Read-Only Memory (ROM) 

Read-Only Memory (ROM) 

• Contains a permanent pattern of data which can not be 

changed. 

• Is nonvolatile. No power source is required to maintain 

bit values in memory. 

• While it is possible to read a ROM, it is not possible to 

write new data into it. 

• Data is actually wired in to chip as part of fabrication 

process. This presents two problems: 

Data insertion step has a large fixed cost. 

No room for error. If one bit is wrong, whole set of 

ROMs must be thrown out. 

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Structure of Static RAM (SRAM) 

Four transistors (T 1, T 2, T 3, T 4) produces a 

stable logical state. 

In logic state 1, point C 1 is high and point C 2 

is low; in this state, T 1 and T 4 are off and T 2 

and T 3 are on. 

In logic state 0, point C 1 is low and point C 2 

is high; in this state, T 1 and T 4 are on and T 2 

and T 3 are off. 

Both state are stable as long as direct current (dc) voltage is applied. 

Address line is used to open or close a switch. Address line controls two 

transistors (T 5 and T 6). When a signal is applied to this line, two transistors 

are switched on. Allowing a read or write operation. 

For a write operation, desired bit value is applied to line B forcing T1, T2, T3, T4 to proper states. For a read operation, bit value is read from line B. 

Types of Read-Only Memory (ROM) 


• Programmable ROM (PROM) 

• Erasable programmable ROM (EPROM) 

• Electrically erasable programmable 

(EEPROM) 

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Programmable Read-Only Memory (PROM) 

• Writing process is performed 

Electrically. 

By a supplier or customer after chip 

fabrication. 

• Special equipment is required for writing or 

programming process. 

• Is nonvolatile and may be written into only once. 


Electrically Erasable Programmable Read-Only 

Memory (EEPROM) 

• Any part of memory can be written at any time 

without erasing prior contents. 

• Updateable in place using ordinary bus control, 

address and data lines. 

• Is nonvolatile. 

• Writing takes much longer than reading. 

• More expensive and less dense than EPROM. 

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Erasable Programmable Read-Only Memory 

(EPROM) 

• Read and write electrically, as with PROM. 

• Before a write, all cells must be erased by exposure 

to ultraviolet radiation (erasure takes about 20 

minutes). 

• Writing uses different electronics than normal 

memory writes. 

• Is nonvolatile. 

• Errors can be corrected by erasing and starting 

over. 

• More expensive than PROM. 


Flash Memory 

• Uses electrical erasing technology. 

• Much faster erasure than EPROM. 

• Same density as EPROM. 

• Allows individual blocks to be erased rather than 

an entire chip. 

• Gets its name because microchip is organized so 

that a section of memory cells are erased in a single 

action or “flash”. 

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Typical 16M DRAM (4M × 4) 

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Semiconductor Main Memory: Chip Logic 

Each chip contains an array of memory cells. 

For semiconductor memories, one of key design issues is number of bits 

of data that may be read/written at a time: 

• Physical organization is same as logical organization is one extreme. 

Array is organized into W words of B bits each. 

• Other extreme is 1-bit-per-chip. Data is read/written one bit at a time. 

Typical organization of a 16Mbit DRAM 

• 4 bits are read/written at a time. 

• Logically, memory array is organized as 4 square arrays of 2048×2048 

elements. 

• Horizontal lines connect to Select terminal of each cell in its row. 

• Vertical lines connect to Data-In/Sense terminals of each cell in its 

column. 

• 11 address lines are needed to select one of 2048 rows and 11 address 

lines are needed to select one of 2048 columns (2 11 = 2048). 

• Multiple DRAMs must be connected to memory controller to 

read/write an 8 bit word. 

Semiconductor Main Memory: Chip Packaging 

An integrated circuit is mounted on a package that contains pins for 

connection to outside world. 

Typical pinouts of EPROM package, which is 

an 8-Mbit chip organization as 1M × 8: 

• A0-A19: Address of word being accessed. For 

1M words, 20 pins are needed (2 20 = 1M). 

• D0-D7: Data to be read out. 

• Vcc: Power supply to chip. 

• Vss: A ground pin. 

• CE: Chip enable which is used to indicate 

whether or not address is valid for this chip. 

• Vpp: Program voltage which is used for 

writes to (programming) an EPROM. 

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Semiconductor Main Memory: Chip Packaging 

Typical pinouts of DRAM for a 16-Mbit chip 

organized as 4M × 4: 

• A0-A10: Address of word being accessed. 

DRAM is accessed by row and column and 

address is multiplexed, only 11 pins are 

needed to satisfy 4M row/column 

combinations (2 11 ×2 11 = 2 22 =4M). 

• D1-D4: Data to be read out. 

• Vcc: Power supply to chip. 

• Vss: A ground pin. 

• RAS: Row address select. 

• CAS: Column address select. 

• W or WE: Write enable for write operation. 

• OE: Output enable for read operation. 

• NC: No connection. 

Module Organization 

In case in which larger memory is required, an array of chips is needed. 

Example shows possible organization of a memory consisting of 1M word by 8 

bits per word. In this case, we have four columns of chips, each column 

containing 256K words arranged as follows: 

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Module 

Organization 

If a RAM chip contains only 1 

bit per word, then clearly we 

will need at least a number of 

chips equal to number of bits 

per word. 

Example shows how a 

memory module consisting of 

256K 8-bit words can be 

organized. 

For 256K words, an 18-bit 

address is needed. 

Error Correction 

A semiconductor memory is subject to errors. 

These errors can categorized as 

• Hard Failure. Is a permanent physical defect so that 

memory cell or cells affected cannot reliably store data. 

• Soft Error. A random, nondestructive event that alters 

contents of one or more memory cells, without damaging 

memory. Soft errors can be caused by: 

Power supply problems. 

Alpha particles which result from radioactive decay. 

Both hard and soft errors are clearly undesirable and most 

modern main memory systems include logic for both 

detecting and correcting errors. 

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When data are to be read into memory, a calculation (f) is 

performed on data to produce a code. 

Both code and data are stored. 

For M-bit word and K-bit code, actual size of stored word is 

M+K. 

When previously stored word is read out, code is used to 

detect and possibly correct errors. 

A new set of K code bits is generated from M data bits and 

compared with fetched code bits. 


ULUSOY 

An error-correcting code is 

characterized by number of bit 

Hakan Ali 

errors in a word that it can correct 

and detect. 

Dr. by 

The simplest of error-correcting 

codes is Hamming code. 

Architecture & 

For example, a hamming code for 4 

data bits (1110) requires 3 parity 

bits (100), as shown (to make 

number of 1s in a circle even). 

Organization 

Note that the parity bits (10) are 

now incorrect, and their 

Computer 

intersection identifies the data bit in 

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error, which can be 

corrected back to (1) by negation. 23 

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21 



Comparison yields one of three results: 

• No errors are detected. Fetched data bits are sent out. 

• An error is detected and it is possible to correct error. 

• An error is detected, but it is not possible to correct it. 

Codes that operate in this fashion are referred to as errorcorrecting 

codes. 


To clarify concepts involved, we will develop a code that 

can detect and correct single-bit errors in 8-bit word. 

Determine how long code must be by 

2 K -1 ≥ M + K 

where M: length of data. 

K: length of check bits. 

For example, for a word of 8 data bits (M=8), we have 

• K=3: 2 3 -1 < 8+3 

• K=4:2 4 -1 > 8+4 

8 data bits require 4 check bits. 

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Following table shows number of bits required for 

various data word lengths: 


Check bits are calculated as follows, where symbol ⊕ 

designates exclusive-or operation: 

C1= 

C2= 

C4= 

C8= 

D1⊕ 

D1⊕ 

D2⊕ 

D2⊕ 

D3⊕ 

D3⊕ 

D4⊕ 

D4⊕ 

D4⊕ 

D5⊕ 

D5⊕ 

D6⊕ 

D6⊕ 

D7⊕ 

D8 

D8 

Each check bit operates on every data bit whose position 

number contains a 1 in same bit position as position number 

of that check bit. 

For example data bit positions 3, 5, 7, 9 and 11 (D1, D2, D4, 

D5, D7) all contain a 1 in the least significant bit of their 

position number as does C1; bit positions 3, 6, 7, 10 and 11 

all contain a 1 in second bit position, as does C2 and so on. 

D7 

D7 

P 

0 

0 

1 

1 

Q 

0 

1 

0 

1 

P XOR Q 

0 

1 

1 

0 

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To find position of error and correct it, data and bits are 

arranged into a 12-bit word. 

Bit positions are numbered from 1 to 12. 

Those bit positions whose position numbers are powers 

of 2 are designated as check bits. 

Bit position 

Position number 

Data bit 

Check bit 

12 

1100 

D8 

11 

1011 

D7 

10 

1010 

D6 

9 

1001 

D5 


8 

1000 

C8 

New and old check bits are compared by exclusive or 

operation: 

• If result contains all zero, no error has detected. 

• If result contains one and only one bit set to 1, then an 

error has occurred in one of the check bits. No correction 

is needed. 

• If result contains more then one bit set to 1, then 

numerical value of result indicates position of data bit in 

error. This data is inverted for correction. 

7 

0111 

D4 

6 

0110 

D3 

5 

0101 

D2 

4 

0100 

C4 

3 

0011 

D1 

2 

0010 

C2 

1 

0001 

C1 

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Example: Assume that 8-bit input word is 00111001, with data bit D1 in rightmost 

position. Calculations are as: 

Bit position 

Data bit 

Input word 

8 

D8 

0 

7 

D7 

0 

6 

D6 

1 

5 

D5 

1 

4 

D4 

1 

3 

D3 

0 

2 

D2 

C1=D1 ⊕ D2 ⊕ D4 ⊕ D5 ⊕ D7 =1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1 

C2=D1 ⊕ D3 ⊕ D4 ⊕ D6 ⊕ D7 =1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1 

C4=D2 ⊕ D3 ⊕ D4 ⊕ D8 =0 ⊕ 0 ⊕ 1 ⊕ 0=1 

C8=D5 ⊕ D6 ⊕ D7 ⊕ D8 =1 ⊕ 1 ⊕ 0 ⊕ 0=0 

Suppose that data bit 3 sustains an error and is changed from 0 to 1. When check 

bits are recalculated, we have 

C1=D1 ⊕ D2 ⊕ D4 ⊕ D5 ⊕ D7 =1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1 

C2=D1 ⊕ D3 ⊕ D4 ⊕ D6 ⊕ D7 =1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 0 =0 

C4=D2 ⊕ D3 ⊕ D4 ⊕ D8 =0 ⊕ 1 ⊕ 1 ⊕ 0=0 

C8 C4 C2 C1 

C8=D5 ⊕ D6 ⊕ D7 ⊕ D8 =1 ⊕ 1 ⊕ 0 ⊕ 0=0 

0 1 1 1 

New check bits are compared with old check bits: 

Result is 0110, indicating that bit position 6 is in error. 

0 


ULUSOY 

Hakan 

Assume a 4-bit data word. 

Ali Dr. by 

Sequence shows that if 2 

errors occur (c). 

Architecture 

Wrong bit mistakenly 

& 

corrected (e). 

To overcome problem, an eight bit is added that is set so that 

Organization 

total number of 1s in diagram is even. 

Extra parity bit catches error (f). 

Computer 255 

So detect bit is changed to 0, indicating error. 31 

CSIT 

1 

D1 

1 

⊕ 

0 

0 

0 

1 

0 

1 

1 

0 

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Code just described is known as a single-error-correcting 

(SEC) code. 

More commonly, semiconductor memory is equipped with a 

single-error-correcting, double-error-detecting (SEC-DED) 

code. 

Note that an error of more than a single bit cannot be 

corrected with the previous method. 

Instead, we can add an additional bit to make total number of 

1’s (in both data and parity bits) even. If this bit compares 

differently, we know that a double error has been detected 

(although we cannot correct it). 

Advanced DRAM Organization 

In recent years, a number of enhancements to basic DRAM 

architecture have been explored: 

• Synchronous DRAM (SDRAM) 

Standard DRAM is asynchronous. 

o Processor presents addresses and control levels to 

memory for read and write. 

o After a delay, access time, DRAM either writes or reads. 

o Processor must wait through this delay, slowing system 

performance. 

SDRAM moves data in and out in a set number of clock 

cycles, synchronized with system clock, just like processor. 

CPU does not have to wait, it can do something else. 

An enhanced version of SDRAM is known as double data 

rate SDRAM (DDR-SDRAM) which can send data to CPU 

twice per clock cycle. 

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• Rambus DRAM (RDRAM) 

Vertical package, all pins on one side, designed to 

plug into RDRAM bus (a special high-speed bus just 

for memory). 

After initial 480 ns access time, provides burst 

speeds of 500 Mbps (compared with about 33Mbps 

for asynchronous DRAMs). 


• Cache DRAM (CDRAM) 

Integrates a small SRAM cache (16 Kb) onto a 

basic DRAM chip. 

SRAM on CDRAM can be used in two ways: 

o Used as a true cache which is effective for 

ordinary random access to memory. 

o Used as a buffer to support serial access of a 

block of data. 

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RDRAM Structure 

Review 

Questions 

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Review Question 1 

Suppose an 8-bit word stored in memory is 00111101 with the 

data bit D1 in right most position. Using the Hamming algorithm, 

determine what check bits would be stored in memory with the 

data word. 


Suppose that initial check bits are C1=0, C2=1, C4=1 and C8=1. 

When check bits are recalculated for the 8-bit word stored in 

memory, we have C1=1, C2=1, C4=0 and C8=1. Is there any 

error in the 8-bit world stored in memory? If there is, which bit 

position is in error? 

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Solution 

D8 

0 

D7 

0 

D6 

1 

D5 

1 

D4 

1 

D3 

1 

D2 

0 

D1 

1 

Length of Hamming code (K) should satisfy: 2 K -1 ≥ M + K where M =8 (length of 

data). Thus K=4. Total length of data and code is 8+4=12. 

Bit positions 

Position number 

Data bit 

Check bit 

12 

1100 

D8 

1011 

D7 

1010 

D6 

1001 

D5 

1000 

C8 

C1=D1⊕D2⊕D4⊕D5⊕D7=1⊕0⊕1⊕1⊕0=1 

C2=D1⊕D3⊕D4⊕D6⊕D7=1⊕1⊕1⊕1⊕0=0 

C4=D2⊕D3⊕D4⊕D8=0⊕1⊕1⊕0=0 

C8=D5⊕D6⊕D7⊕D8=1⊕1⊕0⊕0=0 

Solution 


11 

10 


0111 

D4 

0110 

Initial check bits: C1=0, C2=1, C4=1, C8=1. 

Final check bits: C1=1, C2=1, C4=0, C8=1. 

⊕ 

C8 

1 

1 

0 

C4 

1 

0 

1 

C2 

1 

1 

0 

9 

C1 

0 

1 

1 

8 

7 

6 

D3 

5 

0101 

D2 

4 

0100 

Yes, there is an error in 8-bit world stored in memory. 

0101 = 5. Thus, data bit in position 5 is in error. 

C4 

3 

0011 

D1 

2 

0010 

C2 

1 

0001 

C1 

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