Analog Circuit Design Laboratory Report - MyWeb at WIT ...

EVALUATING OPERATIONAL AMPLIFIERS INCLUDING BASIC
CHARACTERISTICS, USE AS VOLTAGE COMPARATORS, CLOSED LOOP AND
DIFFERENTIAL AMPLIFIERS AND IN SIGNAL CONDITIONING DESIGN
1
Whitney Brown
Portia Lane
Adam Ysasi
October 21, 2005

Objectives
• Measure basic op-amp characteristics including ± VSAT, Iload, Isupply, and shortcircuit
current ±ISC
• Simulate op-amp characteristic measurements using PSpice
• Generate VO versus time graph and transfer function of non-inverting voltage
comparator
• Design and test voltage comparator with bipolar voltage reference
• Connect LED’s to voltage comparator output to identify output current direction
• Design and analyze inverting and non-inverting amplifiers with negative feedback
• Simulate measurements of three op-amp configurations using PSpice
• Measure closed-loop voltage gain ACL and phase shift θ between input and output
voltages for inverting and non-inverting amplifiers
• Measure and calculate basic characteristics of differential amplifier including
differential gain ADIFF, common mode gain ACM, and common mode rejection
ratio CMRR
• Build and test discrete three-op-amp instrumentation amplifier
• Add offset voltage to reference terminal of instrumentation amplifier
• Test characteristics of AD620 instrumentation amplifier from Analog Devices,
Inc.
• Generate system equation for weight measurement system
• Generate linear performance equation for commercial load cell
• Generate SCC design equation to convert load cell output for input into
microcontroller
• Build, test, and calibrate complete weight measurement system
Discussion of Theory
Operational amplifiers or op-amps were originally built with discrete transistors and
resistors, and were named after their first uses of mathematical operations (add, subtract,
multiply, divide, integrate, differentiate etc.) Today they are built as integrated circuits
(IC) and are used for applications that encompass the spectrum of electronics from signal
conditioning to signal generation. One reason for their high usage in circuit design is the
tendency of op-amp characteristics to act at levels quite close to those predicted
theoretically, that is the characteristics of an op-amp perform close to the assumed ideal. 1
1 Smith, Sedra. Microelectronic CIRCUITS. Oxford University Press, New York, 1982. Pg. 63-64.
2

The ideal op-amp generally has 5 terminals, two input terminals (pins 2 and 3),
one output terminal (pin 6), and two power supply terminals (pins 7 and 4), see Figure 1.
Pin 2 is the inverting input terminal while pin 3 is the non-inverting input terminal. The
power supply terminals are typically connected to a positive voltage, VCC= 15V and to a
negative voltage, VEE= -15V, pins 7 and 4 respectively. The characteristics of an ideal
op-amp are that it has an infinite open-loop gain (AOL), an infinite bandwidth (Bwl),
infinite input impedance (Rin), zero output impedance (RO) and zero common-mode gain
(ACM).
When operating in its simplest form, displayed in Figure 1, with RL equal to 10-
kΩ (typ), the voltage output of the op-amp is equivalent to the positive or negative
saturation voltage. The saturation voltage (Vsat) can be calculated by:
+ sat = CC −1
V V or 1 + = sat EE V V Eq. (1)
The supply current (Isupply), at pins 7 and 4 is determined by the supply manufacturer’s
specification and ranges from a few milliamps for older products to mega-amps for
today’s new technology. Using Kirkoff’s current law Isupply(+) is equal to Isupply(-) plus the
output current of the op-amp read c′-c, see Figure 1.
I +
sup ply = I ply − I
( + ) sup ( ) o
Eq. (2)
3

Figure 1- Basic Op-amp
When a load resistor value is connected to the output terminal of the op-amp, as
displayed in Figure 1, the op-amp can either be “sourcing” or “sinking” current. When
the op-amp is sinking current, this output current is being delivered by the negative
power supply (VEE) and the output voltage will be -Vsat. The op-amp sinks a load current
when the direction of the current is from c′ to c and RL has a negative voltage drop across
it. The op-amp is sourcing current when the supply current is being delivered by the
positive power supply (VCC) and the output voltage will be a +Vsat. When the op-amp
sources a load current the direction of the current is from c to c′ and RL has a positive
voltage drop across it. When the load resistor is very small, a few hundred Ω, the op-amp
goes into short-circuit protection. The typical value of short-circuit current, ISC, for the
741 op-amp is 25mA.
One characteristic of an ideal op-amp is that it has an infinite open-loop gain
(AOL). The typical value for a 741 op-amp is AOL equals 200,000 (200k). The single-
4

ended output voltage Vo is equal the product of the open-loop gain and the differential
voltage, Ed, between pins 2 and 3. The differential voltage, Ed, is equal to the positive
input voltage minus the negative input voltage and it controls the polarity of the output
VO. When Ed is positive VO is positive, and when Ed is negative VO is negative.
V = A E
Eq. (3)
O
OL
5
d
Ed = V ( + ) ⊥ −V
( −)
⊥
Eq. (4)
One function of the op-amp is as a voltage comparator, see Figure 2.
When an AC voltage source, Ei, is connected to the positive input, pin 3, the op-amp is
working as a non-inverting voltage comparator. If the negative input, pin 2, is connected
directly to ground, the reference voltage Vref is equal to 0V.
Figure 2- Voltage Comparator
As Ei crosses Vref, going from positive to negative, the polarity of VO reverses and
VO changes from +Vsat to –Vsat. When Ei again crosses Vref, negative to positive, VO goes
from –Vsat to +Vsat. When the voltage source is connected to the negative input, pin 2,

the op-amp is working as an inverting comparator where when Ei crosses Vref, negative to
positive, VO is inverted and goes from +Vsat to –Vsat. When Ei crosses Vref, positive to
negative, VO is inverted and goes from –Vsat to +Vsat. Voltage comparators can be used in
many applications such as zero-crossing detectors.
Another important function of the op-amp is as a voltage amplifier. There are
three main circuits that define many of the amplification uses of the op-amp. They are an
inverting amplifier, non-inverting amplifier, and a voltage follower. All of these circuits
work off of the of the ideal circuit function of an op-amp. 2
As previously discussed, the basic circuit function of the ideal op-amp is to sense
a differential voltage, Ed, between the voltage inputs signals applied to the op-amp’s two
input terminals 3 . These two inputs have the characteristic of infinite resistance ideally,
meaning that there is no current entering their terminals. The voltage output is the
product of the differential voltage multiplied by the open loop gain, AOL, which for an
ideal op-amp is considered to be infinite.
These two main circuit functions of AOL and Ed combine to be known as a
differential-input single-ended-output amplifier. However, the idea of an infinite gain is
not practical and the op-amp will never be used alone for this reason. The op-amp is
combined with additional passive components in a feedback circuit to provide a finite
gain, known as the closed-loop gain, ACL. The finite gain can be manipulated to
ultimately produce a variety of applicable functioning circuits, specifically the inverting
amplifier, the non-inverting amplifier and the voltage follower.
2 Ibid Pg. 65
3 Ibid Pg.65
6

Negative feedback occurs when the output is returned to the negative input. It
can be used to reverse the direction of change. In amplifiers when the output is fed back
to the negative input, the inverted distortions cancel out the distortions produced by the
amplifier itself. In an op-amp circuit negative feedback exists if a connection is between
the output terminal (pin 6) and the inverting input terminal (pin 2). This connection can
be may be made with anything that supports a DC current including a wire, resistor, or
battery. Three basic assumptions are used when explaining the effects of negative
feedback. First, the bias current for both the inverting and non-inverting inputs is equal
to zero. Second, the differential voltage Ed is approximately 0V. Finally, the voltage on
the non-inverting input with respect to ground is equal to the voltage on the inverting
input with respect to ground.
The inverting amplifier produces an output voltage, see Equation 5, which is
equal to the input voltage Vin times by the closed-loop gain, ACL, given in Equation 5. The
ACL is derived from Equation 5 on principals of Ohm’s Law, see Equation 6. A voltage
source is connected to the op-amp’s inverting input, (pin 2) and is grounded at the non-
inverting input (pin 3), see Figure 3.
V out ACL
∗VDIFF
. Input
1
= Eq. (5)
V = I ∗ R
Eq. (6)
1
7
1

Figure 3- Inverting Amplifier
The closed loop finite gain, ACL, is possible when the input resistance and the
negative feedback resistance are connected between the output and the inverting voltage
source. From a virtual ground created by the sensed difference between the op-amp’s
inputs, a node equation can be made based on Kirchoff’s Current Law, as stated below:
All currents entering a node equal the sum of currents leaving a node.
From this equation, the feedback resistor, Rf, acquires a current with equal and opposite
value of the current across the input resistor, Rin, driven by the input source. Only these
two currents are involved in the node equation because the inverting input pin takes no
current due to its ideally infinite resistance. The current across Rin and Rf must then be
equal. Because of the virtual ground VO is equal to the voltage drop across Rf. Therefore
the ACL can be written as shown in Equation 7. The gain is a result of negative feedback.
A
− R
= Eq. (7)
f
CL Rin
8

The non-inverting amplifier works similarly to the inverting amplifier. The non-
inverting amplifier has a different negative feedback loop by removing the source at the
inverting pin. Thus changes the direction of the current across Rf, see Figure 4.
Figure 4- Non-inverting Amplifier
The inverting pin, now grounded, allows for Rin current and Rin voltage to be determined
since a virtual ground is created with respect to Vin and an Ed of zero. This is also due to
the inverting pin taking on no current due to its infinite resistance. The Rf current can
then be found from Kirchoff’s Current Law because it is the only other current involved
with the known current at Rin meeting at the virtual ground node. The direction of current
flow there shows RF supplying the current to Rin. The gain equation for the non-inverting
9

amplifier is given in Equation 8 and is now based on the non-inverting amplifier negative
feedback loop.
R f A = + 1
Eq. (8)
CL Rin
The voltage follower circuit is an exploitation of the inverting and non-inverting
amplifiers’ characteristics. It specifically dwells on the non-inverting amplifier’s ability
to source a voltage with infinite resistance and the idea of negative feedback to the
inverting input. The voltage follower, also known as a buffer or isolation amplifier, is
shown in Figure 5.
Figure 5- Voltage Follower Amplifier
The buffer amplifier is capable of delivering a voltage, with out loss or gain, to a
previously non-excepting load. The buffer must be present to condition the high
impedance voltage source for the load.
10

In association with the non-inverting amplifier characteristics, VO is equal to the
Vin since Ed is equal to zero. This configuration further allows VO to equal Vin since the
inverting pin source, the Rin and the Rf are not present, allowing non-inverting negative
feedback and an ACL equal to 1.
Another op-amp configuration is the differential amplifier as shown in Figure 6.
In this configuration the common mode voltage ECM is rejected by the op-amp.
Figure 6– Differential Amplifier
The differential gain, ADIFF, is equal to ratio of the resistances R and mR as shown in
equation 9, and the output voltage is equal to this gain times the input differential voltage
as given in equation 10.
ADIFF = mR / R Eq. (9)
VO = ADIFF * (E1 – E2) Eq. (10)
11

One characteristic of differential amplifiers is the common mode gain ACM. Ideally, the
output voltage should be zero when E1 and E2 are connected to the same terminal, so ACM
should also be zero. This value is a measure of the op-amp quality and is equal to the
common mode output voltage VOCM divided by the common mode voltage ECM as given
in equation 11.
ACM = VOCM / ECM Eq. (11)
Determining the common mode voltage gain is necessary to calculate the common mode
rejection ratio CMRR. CMRR is the differential voltage gain ADIFF divided by the
common mode voltage gain ACM as given in equation 12 and ideally should be infinite.
Because the value is so large the CMRR is generally given in decibels (dB). CMRR can
be converted to CMRR(dB) using equation 13.
CMRR = ADIFF / ACM Eq. (12)
CMRR(dB) = 20 log CMRR Eq. (13)
An amplifier similar to the differential amplifier is the instrumentation amplifier
shown in Figure 7. The pin configuration for this amplifier is like that of am op-amp
except that the differential voltage gain, ADIFF, is determined by the ratio of the resistance
Rg connected between pins 1 and 8 and the internal resistance. Also a reference voltage
can be connected through pin 5.
12

Figure 7– Instrumentation Amplifier
The ratio of the resistances, referred to as “a,” is given in Equation 14. This value is then
used the calculate ADIFF using Equation 15.
a = aR / R = Rg / R Eq. (14)
ADIFF = 1 + 2 / a Eq. (15)
Output voltage VO for the instrumentation amplifier, given in Equation 16, is equal to the
differential voltage gain ADIFF times the voltage difference across the input terminals plus
the reference voltage.
VO = ADIFF *(E1 – E2) + Vref Eq. (16)
The op-amp with its many configurations can be combined and used in several
applications of signal conditioning circuit design. Some applications that use a
combination of op-amp functions are a microprocessor-based data acquisition system,
13

which converts pressure into a single ended voltage, a semiconductor diode based sensor
system to measure an input temp and output a voltage, and a human engineered weight
measurement system that accepts an input weight and outputs a single-ended voltage.
The system design process incorporates first describing mathematically, from the
statement of the problem, the system to be designed in the standard form 4 :
y = mx + b
Eq. (17)
The linear performance equation of the property being measured is calculated using data
measured from the device and put into the standard form of Equation 17. The signal
condition circuit equation is then determined by the desired output verse the input
calculated from the performance equation of the device, and put in the standard form of
Equation 17. Its characteristics and wide range of functions make the op-amp one of the
fundamental building blocks of circuit design.
Measuring ± VSAT:
Using the LM741 op-amp, whose package can be seen in Figure 1, a configuration is
wired with two DC power supplies and no output load. One supply power source of
+15V was connected to pin 7 and the second supply power source of -15V was connected
to pin 4. The total potential across these power supplies was measured at 30V. Pin 3, also
known as the non-inverting input, was wired to the positive power supply of +15V.
The ±Vsat was expected to measure ± 14V; see Equation 1. The + Vsat was
measured at +14.3V and – Vsat was measured at -13.63V. This measured loss compares
4 Villanucci, Robert. Wentworth Institute of Technology, Electromechanical Engineering. Laboratory
Exercise Five Handouts.
14

favorably both voltages being within 10% of expected; where the positive supply had a
percent difference of 2.14% and the negative supply had a percent difference of 2.64%.
Input pins 2 and 3, were shorted by connecting them both to ground. From the
data sheet of the op-amp, the AOL is 200, 000 typically. This was then used to calculate
the Vout based on Equation 3, where Ed is equal to the voltage differential across the
inputs. Here, since the inputs have been shorted, Ed is equal to 0V. However, when VOUT
was measured a reading of 14.3V.
This exercise was simulated in PSpice. This was devised with simulated
components and adjacent voltage supplies connected by assigning the same name of the
source at the inputs.
Figure 8- Positive Vsat
15

Figure 9- Negative Vsat
Positive Vsat was obtained almost matching the measured values from the
experiment, seen in Figure 8. Negative Vsat was similarly taken from PSpice with an
acceptable value, see Figure 9.
Measuring Both Load and Supply Current:
The second circuit configuration was wired as shown in Figure 1 with no load resistance.
The supply currents are from the two separate power sources. Isupply(+) was measured at
0.66mA and Isupply(-) was measured at 0.662mA. These values were well within the data
sheet typical Isupply value of 1.7mA. The difference in ± Isupply is acceptable because the
op-amp is still within manufacturer’s specifications and the op-amp running at this lower
current will run cooler than it would if equal to the specifications.
16

The next configuration, with a 10-kΩ load resistor connected to pin 6, illustrates
sourcing current. Sourcing current used the positive supply to feed the output and an
additional source is connected to the non-inverting pin 3. Isupply(+) is equal to the sum of
the negative supply current and the current; see Equation 2. This satisfied Kirchoff’s
Current Law.
Isupply(+) enters into the op-amp, and I supply(-) and the load current, IL, exit the op-
amp. The circuit was broken so that current measurements could be taken for Isupply(-), Iout
and Isupply(+). The sum of Isupply(-) equal to 0.6mA and IL equal to 1.44mA was within 1.4%
of the direct measurement of Isupply(+) equal to 2.13mA. The polarity of the source current
proved that the op-amp was sourcing current to the load as it was positive and equal to
+Vsat.
Next, the circuit was configured to sink current. With the 5V source at the
connected to the inverting pin 2, the output became -Vsat, since voltage follows from
higher to lower potential, the load current is drawn into the op-amp. The op-amp was
then sinking an IL equal to 1.37mA and using the measured value Isupply(+) at 0.6mA from
this circuit, to calculate an Isupply(-) equal to 2.31mA from Equation 2.
Based on the sum of Isupply(+) and Iout when compared to the direct current reading
of Isupply(-) provided a percent difference of 12.26%, which is not within the excepted
10%. Sinking current to the load did provide a –Vsat.
This exercise was also simulated on PSpice, see Figure 10. This was devised with
simulated components and adjacent voltage supplies connected by assigning the same
name of the source at the inputs. The results of PSpice were close to those measured in
17

the lab and clearly demonstrate the principal of Equation 2; values are noted on Figure
10.
Short-Circuit Current Measurements:
Figure 10- Iload and Isupply
The data sheet gave a typical value for short circuit current of ± 25mA. The circuit was
wired to source current to the load of very small resistance. The small resistance triggers
the short circuit protection so that the op-amp is not damaged. Positive Isc was achieved at
an acceptable value of 29mA. When configured for sinking current a negative Isc acted
across the load and was measured at an acceptable value of -23.9mA.
This was also done in a PSpice simulation, see Figure 11. This was devised with
simulated components and adjacent voltage supplies connected by assigning the same
name of the source at the inputs.
18

Figure 11- Positive Isc at approximately maximum
PSpice used the maximum data sheet characteristics for short circuit current, where
Isc(MAX) was approximately 40mA for temperatures above room temperature. Here it also
demonstrated the principal that Vo can be brought down lower that saturated voltage
when load resistance is very low and Isc protection is turned on.
VO vs. Time and VO vs. Ei for Non-inverting Zero-Crossing Detector:
Using the 741 op-amp, the circuit is setup as shown in Figure 12. VCC of 15V and VEE of
-15V are applied to the op-amp prior the applying the voltage Ei. Ei is then set to a ± 10V
(peak) triangle wave at a frequency of 50 Hz on the waveform generator.
19

Figure 12 – Non-inverting zero-crossing detector
Channel 1 of the oscilloscope is used to read Ei and channel 2 to read VO. The
oscilloscope is set to dc coupling mode. Figure 13 displays the plot of VO versus time.
+Vsat measures 13.13V and –Vsat measures -13.44V. Since the negative input (pin 2) is
connected directly to ground, the reference voltage Vref is equal to 0V. As Ei crosses Vref,
going from positive to negative, the polarity of VO reverses and VO changes from +Vsat to
–Vsat. When Ei again crosses Vref, negative to positive, VO goes from –Vsat to +Vsat.
20

Figure 13– Plot of Ei versus time and VO versus time
After grounding both oscilloscope channels and zeroing the electron beam to the center
of the scope face, the oscilloscope is set to display the transfer function for the voltage
comparator as shown in Figure 14.
Figure 14– Plot of VO versus Ei
21

+Vsat measures 14.06 V and –Vsat measures -12.66 V. These values differ slightly than
recorded previously because of the channels being grounded. This transfer function is
indicative of a non-inverting comparator. The polarity of Ei and VO are always equal.
Design and Testing of a Voltage Comparator:
Figure 15 is the transfer function for an inverting voltage comparator. From this plot
+Vsat, -Vsat, VCC, VEE, + Ei (peak), - Ei (peak), and Vref can all be determined. +Vsat
equals 12.5V. –Vsat equals -12.5V. Because Vsat is approximately 1V less than the
power supply voltage, VCC is 13.5V and VEE is -13.5V. +Ei is 7.5V and -Ei is -7.5V.
Because the output polarity changes at 0V, Vref is 0V.
Figure 15 – Transfer Function
22

Using the information derived from Figure 5, an inverting voltage comparator is designed
as shown in Figure 16. After applying dc power, Ei is adjusted to a ±7.5 V, 50Hz triangle
wave.
Figure 16 – Inverting voltage comparator
Using the oscilloscope, channel 1 is set to measure the input voltage at pin 2. Channel 2
measures the voltage across the load resistance RL. Figure 17 displays these voltages
versus time. +Vsat measures +12.50V and –Vsat measures -11.44V.
23

Figure 17 - Plot of Ei versus time and VO versus time
In Figure 7, VO and Ei cross paths at a value of 0V. Therefore Vref has a value of 0V. As
Ei crosses Vref and goes above it, the VO polarity reverses and it switches from +Vsat to –
Vsat. The opposite occurs when Ei again crosses Vref going below it. The polarity again
reverses, changing from –Vsat to +Vsat. By changing the oscilloscope’s time base to XY,
the plot of VO versus Ei is created as shown in Figure 18.
Figure 18 - Plot of VO versus Ei
24

The output voltage can be altered so that it is not always ±Vsat. VO can be reduced to
approximately 5V by reducing the load resistance RL. If the load resistance is low
enough the op-amp will enter a state of short circuit protected in which the current ISC is
typically ±25mA. If the 10-kΩ load resistor is replaced by a 220-Ω resistor, VO equals
3.75V as shown on Figure 19.
Figure 19 - Plot of Ei versus time and VO versus time
Adding LEDs to the output Terminal of an Op-amp:
The comparator test circuit is wired as shown in Figure 20. R2 is a potentiometer with a
range of 0 to 10-kΩ . R2 is adjusted so that the green LED is in the “on” position and the
red LED is in the “off” position.
25

Figure 20 – Test Circuit
VO, VLED(F) (green), and VLED(R) (red) are measured using the DMM. All three voltages
are equal and measure 2.08V. The output current IO of the op-amp is measured to be
16.8mA. This current indicates that the op-amp is in short-circuit protection. The
direction of the current indicates that the op-amp is sourcing current in this configuration.
The maximum reverse voltage that can occur across the LED before damage occurs is
5V. The “off” LED is protected since the voltage across it was only 2.08V. R2 is then
adjusted until the red LED is in the “on” position and the green LED in the “off” position.
VO, VLED(F) (green), and VLED(R) (red) equal -1.625V. IO equals -14.8mA. The circuit is
again in short-circuit protection. The recommended forward current across the “on” LED
is from 10mA to 25mA. The measured current is therefore acceptable. Damage is not
likely to occur to the LED because current is limited by the op-amp short circuit
protection current.
26

Analysis of an Inverting Amplifier and Measuring its ACL and Phase Shift:
First, construction of the circuit seen in Figure 3 was done using color coded resistor
values of 33-kΩ for Ri and 100-kΩ for Rf. The resistance of Ri was measured to be
32.7-kΩ and Rf was measured to be 99.27-kΩ . A load resistor was added, and proved to
have no effect on the output voltage. The circuit was wired to an input voltage of ±2V at
100Hz from the function generator and source voltages of VCC= +15V and VEE= -15V.
The closed loop gain for the inverting amplifier could then be calculated based on its gain
equation, see Equation 7. The ACL was calculated to be -3.036.
An oscilloscope was used with channel 1 monitoring the input voltage and
channel two monitoring the output voltage. A picture was taken of the results, see Figure
19. The graph illustrates that when Vi goes positive, VOUT is negative, or vise versa. VOUT
is equal to ± Vsat, with its polarity dependant on the polarity of Vi.
Figure 19- Oscilloscope picture of inverting amplifier
27

The experiment was then conducted with the input voltage changed from a peak voltage
of 2V to 5V. This change in voltage caused VOUT to be distorted, note the flat toped
wave, see Figure 20. The distortion was due to the voltage being over amplified; being
that the supplied Vi was too high and was producing an output voltage above Vsat. Vsat is
the maximum output voltage possible from the source voltages of +15V and -15V, the
supply voltage for op-amps. This means that the circuit designer does have limitations
and its chosen available ±Vsat must be considered.
Figure 20- Distortion of output voltage inverting amplifier
Graphical representation of the inverting amplifier was achieved through PSpice
simulation, see Figure 22. The simulation consisted of virtual components and virtual
voltage sources connected through virtual wire and part name, see Figure 21. The input
voltage was modeled by a sin wave with amplitude equal to an absolute value of Vi. The
output voltage can be seen with an amplified voltage of an absolute value of 5.97V and a
28

180º phase shift from the Vin. The output voltage was within 2% of the calculated value
of an absolute value of 6.07V and the phase shift was measured at the expected value of
180˚. Based on the measured input and output voltages, the A CL was calculated using
Equation 7. The measured ACL value was -2.97. This was within 2.16% of our expected
ACL of -3.03.
Figure 21- Analysis of inverting amplifier circuit
29

Voltage (mV)
8
6
4
2
0
-2
-4
-6
-8
Figure 22- Graphical analysis of inverting amplifier
Analysis of a Non-inverting Amplifier and Measuring its ACL and Phase Shift:
First, construction of the circuit seen in Figure 4 was done using color coded resistor
values of 15-kΩ for Ri and 120-kΩ for Rf. The resistance of Ri was measured to be
14.8-kΩ and Rf measured to be 117 -kΩ. A load resister was placed at the terminal of the
output voltage, which proved to have no effect on the value of the output voltage. The
circuit was hooked to an input voltage of ±1V at 100Hz from the function generator, and
source voltages of VCC= +15V and VEE= -15V. The closed loop gain for the non-
inverting amplifier was then calculated using the gain equation, Equation 8. The gain for
the non-inverting amplifier was calculated to 8.905.
The experiment was conducted with the input voltage changed from a peak
voltage of 2V to 5V. This voltage change caused distortion of the Vout wave as previously
seen with the Inverting Amplifier.
Inverting Amplifier Analysis
Voltage Output
30
Voltage Input

The oscilloscope had the input voltage monitored by channel one and seen
modeled by a sin wave with an amplitude equal to Vin. The output voltage was monitored
by channel 2. Pictures were taken of the results, see Figure 23 and Figure 24.
Figure 23- oscilloscope picture of non-inverting amplifier
Figure 24-Distorted voltage output oscilloscope picture
31

Graphical representation of the non-inverting amplifier was achieved through
PSpice simulation as seen with the inverting amplifiers. A phase shift of zero was noted
and expected. Vout had a peak voltage of an absolute value of 7.94V. This did not
compare favorably and was calculated to be within 10.8% of our expected peak output
voltage of 8.905V. PSpice was repeated for the distortion of the output voltage, see
Figure 25. The graphical representation of the distorted non-inverting amplifier output
can be seen in Figure 26 with the same specifications as the non-distorted non-inverting
amplifier except having too high of an output voltage value.
Figure 25- Analysis of non-inverting amplifier circuit
32

Voltage (V)
8
6
4
2
0
-2
-4
-6
-8
Figure 26- Graphical analysis of distorted output of non-inverting amplifier
Based on the measured input and output voltages, the ACL was calculated from Equation
8 for a measured ACL value was 7.94, comparing within 10.8% of our expected ACL,
which is an unacceptable percent error of 10%.
Voltage Follower Circuit and Measuring its ACL and Phase Shift:
The voltage follower circuit was wired as shown in Figure 5. The Vin was set to ±5V at
100Hz by the function generator. An ACL of 1 was expected because the voltage output is
equal to the input voltage for the voltage follower circuit. The ACL was measured at 1.007
comparing favorably to the expected value.
Distorted Vout of Non-inverting Amplifier
The oscilloscope monitored the input voltage on channel 1 and the output voltage
on channel 2. A picture was taken of the results, see Figure 27.
33
Voltage Output
Input Voltage

Figure 27 - Voltage follower oscilloscope picture, adjusted to separate graphs
A PSpice simulation was conducted to test the results. The configuration can be
seen in Figure 28, and a graphical representation of the voltage follower can be seen in
Figure 29. The graph emphasizes the overlapping voltage waves by having a display that
appears as one wave form but is actually the waveform of the input voltage and the
waveform of the output voltage overlapping it.
34

Voltage (V)
6
4
2
0
-2
-4
-6
Figure 28- Analysis of a voltage follower circuit
Voltage Follower Analysis
Figure 29- Graphical analysis of voltage follower
35
Output Voltage
Input Voltage

Differential Voltage Gain:
The circuit was setup as shown in Figure 30 and E1 and E2 were measured with respect to
ground using the DMM. E1 measured 458mV and E2 measured 448mV. The differential
voltage across the 10-Ω resistor (E1-E2) was calculated to be 10mV. The common mode
voltage ECM for this circuit was equal to E2, or 448mV.
Figure 30 – Test circuit to measure ADIFF
With resistors mR and R equal to 100-kΩ and 20-kΩ respectively, the differential voltage
gain, ADIFF, was calculated using Equation 9. Using Equation 10, expected output
voltage VO was calculated to be 50 mV. Using the DMM VO was measured as 48.39mV.
The percent error between the calculated and measured values was 3.6%.
The differential voltage gain can be altered by simply changing the values of the
resistors. To increase ADIFF to 100, resistor mR could be increased to 2-MΩ, or resistor R
36

could be reduced to 1-kΩ. To decrease ADIFF to 1, resistor mR could be decreased to 20-
kΩ, or resistor R could be increased to 100-kΩ.
Measuring Both ACM and CMRR:
The circuit shown in Figure 30 was modified to include a common-mode adjustment as
shown in Figure 31. The positive and negative inputs were both connected to E2. E2 was
then the common-mode voltage, ECM. ECM was then measured as 449.7mV.
Figure 31– Test circuit to measure ACM and CMRR
The DMM was connected to the output of the differential amplifier and the 50-kΩ
potentiometer was adjusted until the smallest output voltage was displayed. This output
voltage was recorded as the VOCM and equal to 0.01mV. The common mode voltage gain
37

ACM was then calculated using Equation 11. ACM equaled 2.23 x10 -5 . The common
mode rejection ratio CMRR was then calculated using Equation 12, and determined to be
225,529. The circuit shown in Figure 31 could be altered to increase and improve the
CMRR by increasing ADIFF as previously discussed.
AD620 Instrumentation Amplifier:
The circuit was setup with the AD620 instrumentation amplifier as shown in Figure 32.
The differential gain ADIFF was set to 10 by adjusting the 10-kΩ potentiometer.
Figure 32 – AD620 Instrumentation Amplifier
E1 was measured as 461mV with respect to ground. E2 was measured as 451mV with
respect to ground. Using Equation 10 output voltage VO was predicted to be 100mV. VO
was then measured to be 98.2mV.
38

The 10-kΩ potentiometer was then adjusted for a differential gain ADIFF of 100.
Again using Equation 10 VO was predicted to be 1.0 V. VO was measured as 970 mV,
which is within 3% of the predicted value.
The circuit was then modified as shown in Figure 33 to determine the common-
mode voltage gain ACM with both input being connected to E2. ECM, equal to E2, was
then measured to be 452mV. VOCM was then measured as 0.12mV.
Figure 33 – Measurement of CMRR
Using Equation 11 ACM was calculated to be 6.64 x 10 -6 . CMRR was calculated a using
Equation 12 to be 150,666. CMRR was then converted to dB units using Equation 13.
CMRR(dB) equals 103.5, which is significantly lower than the typical data sheet value.
The typical data sheet value shows CMRR(dB) to be 130 when ADIFF is equal to 100.
39

Three-Op-Amp Instrumentation Amplifier:
The circuit was setup as shown in Figure 34. This circuit is a three-op-amp
instrumentation amplifier and acts similarly to the AD620. Op-amps A1 and A2 act as
buffered inputs used to increase input impedance. The differential gain is adjusted by the
aR resistor. VO responds only to EDIFF, (E1- E2).
Figure 34 – Three-Op-Amp Instrumentation Amplifier
Initially the aR resistor was equal to 20-kΩ. Using Equation 14 it was calculated to be 1.
Using Equation 15 ADIFF was calculated to be 3. The 10-Ω resistor in the circuit was
actually measured to be 11.7-Ω. From Equation 10 the differential output voltage of the
40

input stage VO’ was calculated to be 35mV. The differential gain of the output stage was
equal to 1, so the overall circuit was equal to ADIFF and VO was calculated to be 35mV.
VO was measured to be 34.9mV. E1 and E2 were measured as 458.9mV and
447.7mV, respectively. Using Equation 15 ADIFF was equal to 3.12. Both VO and ADIFF
were within 4% of the calculated values.
Resistor aR was then changed to a 100-kΩ resistor to increase the instrumentation
amplifiers differential gain. Using Equation 14, a, equals 5, VO’ equals 16.4 mV, and VO
equals 16.4 mV. Using the DMM, VO’ was measured as 15.75 mV, and VO was
measured as 17.0 mV. The DMM was then used to measure E1 and E2. Their values
were 458.9 mV and 447.7 mV, respectively. Using Equation 15 ADIFF was calculated to
be 1.52. Both VO and ADIFF were within 10% of the calculated values.
The differential gain for this circuit could be adjusted to any value by changing
aR. The actual resistor value was determined using Equation 14 and Equation 15. To
achieve an overall circuit gain of 100, aR must be equal to 404-Ω.
Adding a Voltage to the Reference Terminal:
The reference terminal of the instrumentation amplifier was modified to provide an offset
voltage. This was done by constructing the circuit shown in Figure 35. This circuit was
then connected to the reference terminal of the circuit shown in Figure 35. The
connection between the reference terminal and ground was removed.
41

Figure 35 – Adjustable Reference Voltage, Vref
Power was applied and the 10-kΩ potentiometer was adjusted until reference voltage Vref
equaled 0V. Because the potentiometer only used “one turn,” an exact value of 0V could
not be achieved. Vref was set to 1.5 mV. VO was measured as 18.09 mV. This value
was acceptable to continue.
If Vref were set to any other value, VO would change by the same amount. Vref
was set to 3V. Using Equation 16 VO was predicted to be 3.012V. VO was then
measured as 3.0195V. This was within 1% of the calculated value. Vref was then
changed to -4V, and VO was again predicted using Equation 16 to be 3.988V. VO then
equaled -3.972V. This value was also within 1% of the calculated value.
42

Adding Vref to an instrumentation amplifier could be useful in a variety of
applications. If a pressure sensor produced an output voltage at a pressure considered to
be relative zero, Vref could be used to eliminate that offset.
Weight System Mathematical Design:
The statement of the problem was to design a human engineered weight system around
the PLC-5 laboratory load cells. The design requirements were that it must accept weight
as an input, from 0 to 5 pounds, and output a single-ended voltage that varied from 0 to
5000mV (0 to 5V). The first step in the design process was to graph the system, see
Figure 36, and develop the System Equation (VO vs. W). The System Equation was
determined to be:
V O
= V
Lbs
∗W
1
System Equation
0
0 5
Output Voltage (V)
Figure 36- System Equation
43
6
5
4
3
2
1
W (lbs)
Eq. (18)

The PLC-5 load cell and weights were then used to take data to write the Sensor Equation
(W vs. VDIFF) for the load cell, see Figure 37.
Sensor Equation
0
0 1 2 3 4 5
W (lbs)
Figure 37- Sensor Equation
The load cell was powered with +10.0V (red) and connected to ground (black). The
differential output voltage (VDIFF) between the green (+) and white (-) leads was
measured, and a differential voltage of 3.84 mV was measured to be the offset when the
weight to be measured was 0 lbs. The procedure of placing weights on the load cell and
measuring the differential voltage output continued for the range of weights listed in
Table 1.
Measured Weight (g) Measured Weight (lbs) VDIFF (mV)
0g 0 lbs. 3.84 mV
454g 1 lbs. 7.72 mV
908g 2 lbs. 11.59 mV
1361g 3 lbs. 15.61 mV
44
25
20
15
10
5
Voltage Difference (mV)

1851g 4 lbs. 19.74 mV
2268g 5 lbs. 23.33 mV
Table 1- Weight and Differential Voltage
The Sensor Equation calculated from the end points of 0 and 5 lbs. was determined to be:
V DIFF
= ( 3.
896mV
Lbs
) ∗W
+ 3.
84mV
Eq. (19)
The signal condition circuit (SCC) design was then graphed, see Figure 38. The SCC
Design Equation needed to signal condition the output of the load cell to produce the
System Equation was:
Voltage Output (V)
6
5
4
3
2
1
0
VO DIFF
= 256. 54 ∗V
− 985.
1mV
Eq. (20)
SCC Design Equation
3.84 23.33
Voltage Difference (mV)
Figure 38- SCC Design Equation
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Weight System Hardware Design:
The requirements of the design were that the instrumentation amplifier should have a
differential gain, ADIFF, of approximately 10 with no offset. The design was constructed
using an AD620 instrumentation amplifier and a 741C op-amp, see Figure 39.
Figure 39- Circuit Configuration of the System
The resistor, Rg, connected to pins 1 and 8 of the AD620, was chosen using the
requirements of ADIFF and Eq. 16. Rg was chosen to be a 499Ω and a 4.99-kΩ resistor in
series.
The feedback resistor, Rf, of the op-amp was chosen to be 100-kΩ. The input resistor, Ri,
was calculated using Equation 8, where it was set equal to the remaining gain. Ri was
calculated to be 2.7k resistor and a 5k potentiometer in series. The offset resistor, Roff, of
the 741C op-amp was calculated based on the value of Rf and Vref to satisfy the offset of
the SCC Design Equation, Equation 20. This allowed for Roff to be calculated providing
the desired voltage output.
46

Roff was calculated to be a 1.2-MΩ resistor and a 1-MΩ potentiometer in series with a
Vref of +15V.
After the circuit was constructed the gain and offset adjustments were calibrated
using the potentiometers so that at 5 Lbs the DMM read 5V and at 0 Lbs the DMM read
0V. The circuit was then tested for a weight of 1250 grams. A value of 2.74V was
calculated and a value of 2.74V was measured at this weight.
Conclusion:
In the op amp’s simplest form, the output voltage will be at ±Vsat. The voltage output is
determined by the polarity of the differential voltage across the input terminal. For either
differential voltage polarity, the magnitude of VO will be approximately1V less than the
power supply voltage, either VCC or VEE. This was demonstrated when the VCC of +15V
was connected to pin 3. VO was measured at an acceptable value for +Vsat at +14.3V.
Then, when the VEE of -15V was connected to pin 3, the VO was measured at an
acceptable value for -Vsat at -13.63V. Supply current was measured as 0.66mA. This
was not equal to the typical manufacturer specification of 1.7mA, but this is considered
beneficial as it allows the op amp to operate at a lower temperature. This op amp
configuration was also generated in PSpice having the non-inverting pin take the different
supply voltage sources. This gave values that were similar to the measured values.
With a typical resistance value of 10-kΩ connected to the output terminal of the
op amp, a load current is drawn from op amp. This load current varies with the magnitude
of the load resistance. The maximum load current, known as the short circuit current is
typically 25mA. For the op amp tested, the short circuit current was 27mA. Short circuit
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protection is achieved only with a small resistive load, usually only a few hundred ohms.
Once in short circuit protection, the load resistance can be continually decreased from the
value that caused short circuit protection to give continuously decreasing values for VO
from the ±Vsat.
The op amp as a voltage comparator was practiced and illustrated. The
comparator is defined by the reference voltage and the input taking in the source voltage.
There are two types of comparators; the first is an inverting comparator where the input
source voltage is placed at the inverting pin 2. The other is the non-inverting comparator
where the input source voltage is placed at non-inverting pin 3. In both cases the pin not
connected to the source voltage is considered the reference voltage, whether it is
connected to another voltage or to ground. The VO will have the polarity of the input
differential Ed because it is an open-loop circuit. When the VO is high (at + Vsat) or when
the VO is low (at –Vsat) is determined by the reference voltage. VO is equal to – Vsat when
Ed is negative; VO is equal to + Vsat when Ed is positive.
For the non-inverting zero-crossing detector analyzed in the laboratory, the
oscilloscope displayed a square wave with peak voltages of ± Vsat. With the reference
voltage at ground, the output voltage switched polarity as the input voltage crossed the
reference voltage, which was connected to ground. This was exactly as expected for a
non-inverting zero-crossing detector. The output voltage can be adjusted. This is done
by forcing the op amp into short circuit protection. In this experiment the output voltage
VO was reduced to ±3.75V by replacing the 10-kΩ resistor with a 220-Ω resistor. VO can
be changed to any values within ± Vsat by adjusting the load resistance.
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Through the use of negative feedback, the op amp can be configured so that VO is
not always in a state of saturation, but rather equal to the value in Equation 5. In the
inverting configuration the closed loop gain, given in Equation 7 as the negative ratio of
the feedback and input resistances, was proven correct as the gain -2.97 was within 2% of
the calculated value. Also for the non-inverting and voltage follower configurations, the
closed loop gains were within 1% of the calculated values. Knowing that the op amps so
closely perform according to the theoretical relationships allows for easy design of signal
conditioning circuits. To design the proper circuit, given the desired voltage gain, one
may simply choose the feedback resistor value and solve for the input resistance. For
example, to achieve a gain of -5 the designer chooses an inverting configuration and
feedback resistor of 100-kΩ. The necessary input resistance would be 20-kΩ.
The ADIFF describes the amplification amount of the detected voltage difference
between input terminals. This gain results in an output voltage of the difference amplifier
ready for application. This gain value can be controlled by the four resistors, matching
resistor pair combination at the differential amplifier inputs. For both the differential and
instrumentation amplifiers the calculated and measured values for ADIFF were within
3%.
The ACM is ideally zero since any VCM should have no amplification. This is a
tool used to help portray a real difference amplifier’s accuracy. It is responsible in
determining the CMRR, which for an ideal circumstance is infinite. Therefore, as ACM
becomes finite, the CMRR will decrease from the ideal value. For the differential
amplifier the ACM can be regulated better by using resistor values with much higher
precision. If the CMRR is too low, the differential amplifier will be ineffective since the
49

VDIFF detected will not be accurately represented by its gain at the output if a VCM is
being detected and over amplified.
The CMRR, can be altered by the ADIFF more readily since there is more control
over this that the ACM. This is also reflected in the manufacturer data sheets, as the
CMMR is listed for different circuit gains ranging logarithmically between 1 and 1000.
This further supports that the CMRR and ADIFF are be designated by the designer.
In this experiment one application of signal conditioning circuit design was
attempted. The process of designing and developing a circuit application involves first
setting a system equation, then calculating a sensor equation, and finally developing the
signal conditioning circuit design, SCC, equation. The design process includes solving
for resistor values to satisfy the desired gain and offset for the output.
The signal conditioning circuit developed in this experiment was successful as an
intermittent weight was chosen and the correct voltage was displayed. This process can
likely be applied to many other applications involving circuit design.
50