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Finite-state machine - Wikipedia, the free encyclopedia ... - Ex-ch.com

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<strong>Finite</strong>-<strong>state</strong> <strong>ma<strong>ch</strong>ine</strong> 6<br />

If <strong>the</strong> output function is a function of a <strong>state</strong> and input alphabet ( ) that definition corresponds to<br />

<strong>the</strong> Mealy model, and can be modelled as a Mealy <strong>ma<strong>ch</strong>ine</strong>. If <strong>the</strong> output function depends only on a <strong>state</strong> (<br />

) that definition corresponds to <strong>the</strong> Moore model, and can be modelled as a Moore <strong>ma<strong>ch</strong>ine</strong>. A<br />

finite-<strong>state</strong> <strong>ma<strong>ch</strong>ine</strong> with no output function at all is known as a semiautomaton or transition system.<br />

Optimization<br />

Optimizing a FSM means finding <strong>the</strong> <strong>ma<strong>ch</strong>ine</strong> with <strong>the</strong> minimum number of <strong>state</strong>s that performs <strong>the</strong> same function.<br />

The fastest known algorithm doing this is <strong>the</strong> Hopcroft minimization algorithm. [7] [8] O<strong>the</strong>r te<strong>ch</strong>niques include using<br />

an Implication table, or <strong>the</strong> Moore reduction procedure. Additionally, acyclic FSAs can be optimized using a simple<br />

bottom up algorithm.<br />

Implementation<br />

Hardware applications<br />

In a digital circuit, an FSM may be built using a<br />

programmable logic device, a programmable logic<br />

controller, logic gates and flip flops or relays. More<br />

specifically, a hardware implementation requires a<br />

register to store <strong>state</strong> variables, a block of<br />

<strong>com</strong>binational logic whi<strong>ch</strong> determines <strong>the</strong> <strong>state</strong><br />

transition, and a second block of <strong>com</strong>binational logic<br />

that determines <strong>the</strong> output of an FSM. One of <strong>the</strong><br />

classic hardware implementations is <strong>the</strong> Ri<strong>ch</strong>ards<br />

controller.<br />

Mealy and Moore <strong>ma<strong>ch</strong>ine</strong>s produce logic with<br />

Fig. 8 The circuit diagram for a 4-bit TTL counter, a type of <strong>state</strong><br />

<strong>ma<strong>ch</strong>ine</strong><br />

asyn<strong>ch</strong>ronous output, because <strong>the</strong>re is a propagation delay between <strong>the</strong> flip-flop and output. This causes slower<br />

operating frequencies in FSM. A Mealy or Moore <strong>ma<strong>ch</strong>ine</strong> can be convertible to a FSM whi<strong>ch</strong> output is directly<br />

from a flip-flop, whi<strong>ch</strong> makes <strong>the</strong> FSM run at higher frequencies. This kind of FSM is sometimes called Medvedev<br />

FSM. [9] A counter is <strong>the</strong> simplest form of this kind of FSM.<br />

Software applications<br />

The following concepts are <strong>com</strong>monly used to build software applications with finite <strong>state</strong> <strong>ma<strong>ch</strong>ine</strong>s:<br />

• Automata-based programming<br />

• Event driven FSM<br />

• Virtual FSM (VFSM)<br />

See also<br />

• Abstract <strong>state</strong> <strong>ma<strong>ch</strong>ine</strong><br />

• Artificial Intelligence<br />

• Abstract State Ma<strong>ch</strong>ine Language<br />

• Control System<br />

• Decision tables<br />

• <strong>Ex</strong>tended finite <strong>state</strong> <strong>ma<strong>ch</strong>ine</strong><br />

• <strong>Finite</strong> <strong>state</strong> <strong>ma<strong>ch</strong>ine</strong> with datapath<br />

• Hidden Markov model

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