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<strong>MMI</strong>:<br />
A General Narrow Interface for <strong>Memory</strong> Devices<br />
Judy Chen<br />
Eric Linstadt<br />
Rambus Inc.<br />
Session 106<br />
August 12, 2009<br />
Santa Clara, CA USA<br />
August 2009 1
NOR<br />
S/MDRAM<br />
What is <strong>MMI</strong>?<br />
Baseband<br />
Processor<br />
Cellular<br />
Front End<br />
WLAN BT GPS<br />
GPS<br />
Other<br />
Interfaces<br />
Camera<br />
The Rambus Mobile <strong>Memory</strong> Initiative is focused on high-bandwidth, low-power memory interface<br />
technologies for next-generation mobile memory systems<br />
It is a highly scalable, narrow bus processor-to-memory interface solution with best-in-class powerperformance<br />
• Designed for the handset architecture<br />
• It eases the challenges of having to support a growing diversity of IO’s<br />
It provides a lower risk path to easier integration and cost<br />
• Reduces pin count to avoid pad limitation and reduce cost<br />
• Provides a path to flexible packaging<br />
Apps/Media<br />
Processor<br />
Display<br />
Mobile TV<br />
NAND<br />
MDRAM<br />
In Feb, test silicon demonstrated 4.3Gbps per link with low power and fast power mode transitions<br />
Santa Clara, CA USA<br />
August 2009 2
Future-proof your mobile memory<br />
roadmap with <strong>MMI</strong><br />
<strong>MMI</strong> is an ideal follow-on interface to LPDDR2<br />
• 60% less pin count at equivalent device BW<br />
• Scalable interface across DRAM, NOR, and NAND devices<br />
• 67% less interconnect power at equivalent device BW<br />
Santa Clara, CA USA<br />
August 2009 3
LPDDR2<br />
<strong>MMI</strong><br />
<strong>MMI</strong> Interface Link Innovations<br />
1.2V 0.1V<br />
0.8V/ns 2.4V/ns<br />
Higher BW and Lower Power are achieved by minimizing the effects of ISI, Crosstalk, EMI,<br />
SSO, High-Z Power Distribution Networks and Vref distribution with:<br />
•Bidirectional, very low voltage swing differential signaling<br />
•Series-source termination (transmitter)<br />
•Differential termination (receiver)<br />
•Low C i<br />
Santa Clara, CA USA<br />
August 2009 4
Processor and <strong>Memory</strong> Technologies<br />
are Asymmetric<br />
Faster transistors<br />
Lower Vth<br />
Higher leakage<br />
Lower Vdd<br />
Many metal layers<br />
<strong>Memory</strong> Queue<br />
Data/Cntrl<br />
Slower transistors<br />
Higher Vth<br />
Lower leakage<br />
Higher Vdd<br />
Fewer metal layers<br />
CPHY (interface) MPHY (interface)<br />
Processor <strong>Memory</strong><br />
Santa Clara, CA USA<br />
August 2009 5<br />
CK<br />
Core
<strong>Memory</strong> Queue<br />
<strong>MMI</strong> Optimizes Cost, Complexity, Power-<br />
Performance With An Asymmetric Architecture<br />
All Tx and Rx timing<br />
control is performed<br />
on the<br />
ASIC side<br />
PLL<br />
Ser<br />
Slow-speed<br />
Wider bus<br />
Deser<br />
CA (x2)<br />
DQ (x8)<br />
DM<br />
DRAM or <strong>Flash</strong> side<br />
is kept simple<br />
– no timing<br />
control<br />
CPHY (interface) MPHY (interface)<br />
Processor <strong>Memory</strong><br />
Santa Clara, CA USA<br />
August 2009 6<br />
CK<br />
Ser<br />
Deser<br />
Core
2 CA<br />
16 DQ<br />
2 DM<br />
1 CK<br />
System Configuration Options:<br />
DRAM + A Single <strong>Flash</strong> Device<br />
Option 1<br />
1 x16 DRAM<br />
~6400MB/s DRAM BW<br />
<strong>MMI</strong> – enabled<br />
DRAM<br />
DRAM<br />
PHY<br />
ctrl PHY<br />
<strong>Memory</strong><br />
ctrl<br />
<strong>MMI</strong> – enabled Processor<br />
Option 2<br />
~6400MB/s DRAM BW<br />
~700MB/s NOR/NAND <strong>Flash</strong> BW<br />
2 CA<br />
16 DQ<br />
2 DM<br />
1 CK<br />
<strong>MMI</strong> – enabled<br />
NOR <strong>Flash</strong><br />
NOR<br />
PHY<br />
DRAM<br />
PHY<br />
ctrl PHY<br />
<strong>Memory</strong><br />
ctrl<br />
<strong>MMI</strong> – enabled Processor<br />
2 CA as CA/DQ<br />
1 CK<br />
* x16 PHY Includes 3 redundant links (2 CA and 1 CK)<br />
that are available to support a second DRAM or<br />
Santa Clara, CA USA<br />
additional <strong>Flash</strong> devices<br />
August 2009 7
Option 1<br />
~700MB/s <strong>Flash</strong> BW<br />
~6400MB/s DRAM BW<br />
2 CA<br />
16 DQ<br />
2 DM<br />
1 CK<br />
<strong>MMI</strong> – enabled<br />
NOR <strong>Flash</strong><br />
NOR<br />
PHY<br />
DRAM<br />
PHY<br />
ctrl PHY<br />
<strong>Memory</strong><br />
ctrl<br />
<strong>MMI</strong> – enabled Processor<br />
System Configuration Options:<br />
DRAM + NOR/NAND <strong>Flash</strong> Package<br />
2 CA/DQ<br />
1 CK<br />
Option 2<br />
~3200MB/s <strong>Flash</strong> BW<br />
~3200MB/s DRAM BW<br />
2 CA<br />
8 DQ<br />
1 DM<br />
1 CK<br />
<strong>MMI</strong> – enabled<br />
<strong>Flash</strong> SiP<br />
DRAM<br />
PHY<br />
ctrl PHY<br />
<strong>Memory</strong><br />
ctrl<br />
<strong>MMI</strong> – enabled Processor<br />
Option 3<br />
~2800MB/s <strong>Flash</strong> BW<br />
~3200MB/s DRAM BW<br />
Santa Clara, CA USA<br />
August 2009 8<br />
<strong>Flash</strong><br />
PHY<br />
2 CA<br />
8 DQ<br />
1 DM<br />
1 CK<br />
2 CA<br />
8 DQ<br />
1 DM<br />
1 CK<br />
<strong>MMI</strong> – enabled<br />
Device or SiP<br />
<strong>MMI</strong> – enabled<br />
NOR <strong>Flash</strong><br />
<strong>MMI</strong> – enabled<br />
NOR <strong>Flash</strong><br />
<strong>MMI</strong> – enabled<br />
NOR <strong>Flash</strong><br />
<strong>Flash</strong><br />
PHY<br />
<strong>Flash</strong><br />
PHY<br />
<strong>Flash</strong><br />
PHY<br />
<strong>Flash</strong><br />
PHY<br />
DRAM<br />
PHY<br />
ctrl PHY<br />
<strong>Memory</strong><br />
ctrl<br />
<strong>MMI</strong> – enabled Processor<br />
4<br />
x3 links
<strong>MMI</strong> Matches Native Device Core<br />
and Interface BW<br />
<strong>MMI</strong>’s asymmetric timing easily operates with Low Core BW<br />
or Low Interface Speed <strong>Memory</strong> Devices<br />
SDR, ½DR, ¼DR, etc. Clock and Data streams are created by<br />
bit replication at the controller PHY serializer interface<br />
DM as CK<br />
@ 0.8Gbps<br />
DQ as CA/DQ<br />
@ 0.8Gbps<br />
Santa Clara, CA USA<br />
August 2009 9
High Level Summary<br />
Growing number of different IO’s, processors reaching pad limitations,<br />
lack of BW scalability, higher active power, package design & SI<br />
challenges all hinder current roadmap<br />
<strong>MMI</strong> is ideally suited to extend the mobile memory roadmap<br />
• Scalable general memory interface for all memory devices in the handset<br />
• Fewer pins: 60% less pins than equivalent LPDDR2 solution<br />
• High Bandwidth: 88MB/s-12.8GB/s per <strong>Memory</strong><br />
• Low Power: 67% less active power than equivalent LPDDR2 solution<br />
• Reduced board complexity with much easier PoP design<br />
• Lower cost and lower risk solution than other alternatives<br />
<strong>MMI</strong> can support NOR and NAND <strong>Flash</strong> with no change to the controller<br />
PHY design or pin out<br />
• <strong>MMI</strong> can provide high scalable peak <strong>Flash</strong> BW: 88MB/s to 3.2+GB/s<br />
• <strong>MMI</strong> can support lower <strong>Flash</strong> Device BW at better power efficiency through clock<br />
synthesis<br />
• <strong>MMI</strong> can support high <strong>Flash</strong> capacity: 1 – 4 devices or controllers<br />
Santa Clara, CA USA<br />
August 2009 10
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