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<strong>Memory</strong> Queue<br />
<strong>MMI</strong> Optimizes Cost, Complexity, Power-<br />
Performance With An Asymmetric Architecture<br />
All Tx and Rx timing<br />
control is performed<br />
on the<br />
ASIC side<br />
PLL<br />
Ser<br />
Slow-speed<br />
Wider bus<br />
Deser<br />
CA (x2)<br />
DQ (x8)<br />
DM<br />
DRAM or <strong>Flash</strong> side<br />
is kept simple<br />
– no timing<br />
control<br />
CPHY (interface) MPHY (interface)<br />
Processor <strong>Memory</strong><br />
Santa Clara, CA USA<br />
August 2009 6<br />
CK<br />
Ser<br />
Deser<br />
Core
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