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Processor and <strong>Memory</strong> Technologies<br />
are Asymmetric<br />
Faster transistors<br />
Lower Vth<br />
Higher leakage<br />
Lower Vdd<br />
Many metal layers<br />
<strong>Memory</strong> Queue<br />
Data/Cntrl<br />
Slower transistors<br />
Higher Vth<br />
Lower leakage<br />
Higher Vdd<br />
Fewer metal layers<br />
CPHY (interface) MPHY (interface)<br />
Processor <strong>Memory</strong><br />
Santa Clara, CA USA<br />
August 2009 5<br />
CK<br />
Core
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