2 - Forth Interest Group

Chip Layout
A chip is represented as an array of tiles. For example,
the MuP21 microprocessor die is 2.4 mm square. It is
formatted as a 600 x 600 array of 4- x 4-micron tiles. Each
tile uses four bytes of memory, so the chip uses 1.5 Mbytes.
The present version uses five layers to represent well,
diffusion, polysilicon, metal-1, and metal-2. Each layer
uses four bits of the tile to choose one of 16 patterns:
blank, horizontal, vertical, corner, contact, etc. A tile can
form a transistor by itself. It can also be part of a larger
transistor. It can also provide electrical connections be-
tween transistors and other devices.
A VGA display provides 640 x 480 pixels of 16 colors.
It is formatted into a 20 x 15 array of tiles. Each tile may
be used to represent a 32 x 32 character or a tile containing
patterns in eight colors:
well gold
diffusion green
PO~Y red
metal-1 blue
metal-2 silver
Bright green, red, and blue label nets at 5 volts, as opposed
to ground, as determined by the simulator.
The layers are stacked in their physical order. They may
be peeled off to examine detail otherwise concealed.
Transparent colors are not adequate to look at a design
five layers deep.
The designer works with these tiles. The seven keys are
programmed to provide a variety of actions:
Pan through image
Move cursor through image
Move cursor through layers
Scroll patterns at cursor
Drag trace through image
Copy, reflect, or rotate region of interest.
Display capacitance of net
With these tools, the designer can construct and
connect transistors, compose gates, construct and repli-
cate registers, and finally construct an image of a chip.
With such a layout tool, it is practical to hand craft
chips. The advantage of manual place-and-route is that
you know what you get. If there is no room for a gate, or
if a trace is unfortunately long, you can reconsider the
design. The goal is a clear, compact layout and you can
continually evaluate your progress. Such an approach is
most useful for microprocessor or memory layout, as well
as for random logic.
Layout Display
To view the actual geometry, as well as verify the
rectangle decomposition, keys are defined to:
Display rectangles
Superimpose various layers
Zoom from full chip to tile scale
Pan around chip
The five design layers are expanded to nine output I
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layers:
Well
n+ active
p+ active
Polysilicon
Metal-1
Contacts
Metal-2
Vias
Passivation
It is very reassuring to view these layers and verify the
expansion from the tiled representation of a chip to a
geometrically correct layout.
Net Lists
The first step in verifying a layout is to extract the
transistors and the nets to which they're connected. The
MuP21 is in 1.2-micron CMOS with 6500 transistors
connected to 2500 nets. Each transistor is characterized by
a drive (uA) and each net by a load (P).
To facilitate net identification, the program first traces
the two largest nets, power and ground. It starts at the
input pad and uses a recursive algorithm to follow the
trace through metal-1 and diffusion, branching as re-
quired. It marks each tile with a flag:
01 power
10 ground
00 neither
It then scans the poly layer and locates transistors
where poly crosses diffusion. It measures their size by
following the poly trace. It then identifies the nets for
source, gate, and drain. It can distinguishsource and drain
only when source is power or ground. The result is an
eight-byte table:
Source net index
Gate net index
Drain net index
Drive
To identify a net that is not power or ground, it follows
the trace doing two things:
1. Computing capacitance based on P/tile for each layer:
n-diffusion 13.6 fF
p-diffusion 12.1
gate 7.4
PO~Y .7
metal-1 .6
metal-2 .5
2. Looking for a tile bit indicating the 'owner' of a net. If
it finds an owner, it searches an eight-byte net table to
identify the net:
Location of owner (three bytes)
Load
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