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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 1003 TABLE I EXTRACTED COEFFICIENTS FOR THE R OUR DEVICES AND 1L MODELS FOR Combining the gate bias modulation, temperature and body bias effects, the R TOText () and L e (m) are modeled as R TOText (V SG ;V SB ;T)=aT + b 0 c(V SG 0 V te ) 0 dV SB (3) L e (V SG;V SB;T)=L(m) 0 1L(V SG;V SB;T) (4) 1L(V SG ;V SB ;T)=eT + f 0 g(V SG 0 V te ) 0 hV SB (5) Fig. 3. Dependence of R and 1L on source-body voltage V and temperature (inset). where a; b; c; d; e; f; g; and h are coefficients extracted experimentally, given in Table I. The validity of the proposed R TOText , L e and V te models are verified by applying the modeled values into conventional drain current model expression as in [16]. Fig. 4 demonstrates good agreements between the experimental and modeled drain current characteristics for a wide range of biases and temperatures. IV. CONCLUSIONS The R TOText and L e of scaled hybrid-mode devices have been investigated. Together with a novel V te expression, analytical L e and R TOText models useful for devices operating in a Bi-MOS hybrid-mode environment have been presented. By including the effect of body bias and temperature in the R TOText , L e , and V te models, the drain current characteristics of scaled devices operating in a Bi-MOS hybrid-mode environment can be predicted accurately using conventional drain current expression. ACKNOWLEDGMENT Fig. 4. Prediction of the drive current (solid lines) for different temperatures, gate lengths and body/gate terminal biases. The markers , }, and 4 represent the measurement data for V = 0 V, 0.4 V, and 0.6 V, respectively. [4], a very slight increment in R TOText and 1L with temperature has been observed, as depicted in Fig. 3 (inset). Although applying V SB > 0 V reduces the charge sharing effect [5], [7], narrowing of the depletion width at the source-body and drain-body junctions lengthens the effective channel region, justified by the reduction in 1L with increasing V SB as indicated in Fig. 3. It is interesting to note that this channel lengthening effect appears to increase the numerator of the second term in (1), and hence the channel resistance. However, applying V SB also causes the physical broadening of the channel formation under the gate. In contrast, this phenomenon reduces the intrinsic channel resistance. As mentioned earlier, increasing V SB reduces V te . This effect reduces the channel resistance per unit length and is well represented by utilizing V te in the second term in (1). As compared to V SB =0V condition, I SD increases when the device is biased with V SB > 0 V. For a fixed V SD, R tot = V SD=I SD reduces as a result. From the experimental results, the drop in R tot resulted from the increase in channel carriers collected at the drain region is also reflected in the trend of R TOText, as shown in Fig. 3. Therefore, the results have proven that one important contributing factor to I SD increment for V SB > 0 V is the composite effect between the resultant R TOText , 1L, and V te . The authors would like to acknowledge Chartered Semiconductor Manufacturing Ltd for supplying the test wafers. They are also grateful to the reviewers for their valuable comments. REFERENCES [1] S. S. S. Chung and J. S. Lee, “A new approach to determine the drain-and-source resistance of LDD MOSFETs,” IEEE Trans. Electron Devices, vol. 40, pp. 1709–1711, Sept. 1993. [2] J. Y. C. Sun, M. R. Wordeman, and S. E. Laux, “On the accuracy of channel length characterization of LDD MOSFETs,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1556–1562, Oct. 1986. [3] G. J. Hu, C. Chang, and Y. T. Chia, “Gate-voltage-dependent effective channel length and series resistance of LDD MOSFETs,” IEEE Trans. Electron Devices, vol. ED-34, pp. 2469–2475, Dec. 1987. [4] Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, “A new shift and ratio method for MOSFET channel-length extraction,” IEEE Electron Device Lett., vol. 13, pp. 267–269, May 1992. [5] S. Hong and K. Lee, “Extraction of metallurgical effective channel length in LDD MOSFETs,” IEEE Trans. Electron Devices, vol. 42, pp. 1461–1466, Aug. 1995. [6] Y. S. Jean and C. Y. Wu, “A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs,” IEEE Trans. Electron Devices, vol. 43, pp. 946–953, June 1996. [7] C. M. Wu and C. Y. Wu, “A new method for extracting the channel-length reduction and the gate-voltage-dependent series resistance of counter-implanted p-MOSFETs,” IEEE Trans. Electron Devices, vol. 44, pp. 2193–2199, Dec. 1997. [8] T. H. Chang, J. G. Lo, T. C. Kuo, C. C. H. Hsu, S. Y. Yu, K. F. Tseng, and L. S. Lu, “Effective channel length and source-drain series-resistance determination after electrical gate length verification of metal-oxide-semiconductor field-effect-transistor,” Jpn. J. Appl. Phys., vol. 37, part 1, no. 3A, pp. 796–800, Mar. 1998.
1004 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 [9] K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFETs,” IEEE Trans. Electron Devices, vol. ED-33, pp. 965–972, July 1986. [10] K. Takeuchi, N. Kasai, and K. Terada, “A new effective channel length determination method for LDD MOSFETs,” in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 4, Mar. 1991, pp. 215–220. [11] J. A. M. Otten and F. M. Klaassen, “A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFETs using one single device,” IEEE Trans. Electron Devices, vol. 43, pp. 1478–1488, Sept. 1996. [12] S. S. Liu and S. L. Jang, “Deep-submicron lightly-doped-drain and single-drain metal-oxide-semiconductor transistor drain current model for circuit simulation,” Jpn. J. Appl. Phys., vol. 37, part 1, pp. 64–71, Jan. 1998. [13] S. S. Rofail and K. S. Yeo, “Experimentally-based analytical model of deep submicron LDD MOSFETs in a Bi-MOS hybrid-mode environment,” IEEE Trans. Electron Devices, vol. 44, pp. 1473–1482, Sept. 1997. [14] S. A. Parke, C. H. Hu, and P. K. Ko, “Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs,” IEEE Electron Device Lett., vol. 14, pp. 234–236, May 1993. [15] S. Verdouckt-Vanderbroek, S. S. Wong, J. C. S. Woo, and P. K. Ko, “High-gain lateral bipolar action in a MOSFET structure,” IEEE Trans. Electron Devices, vol. 38, pp. 2487–2496, Nov. 1991. [16] K. Y. Toh, P. K. Ko, and R. G. Meyer, “An engineering model for short-channel MOS devices,” IEEE J. Solid-State Circuits, vol. 23, pp. 950–957, Aug. 1988. [17] B. H. Cheng and J. Woo, “A temperature-dependent MOSFET inversion layer carrier mobility model for device and circuit simulation,” IEEE Trans. Electron Devices, vol. 44, pp. 343–345, Feb. 1997. [18] S. E. Laux, “Accuracy of an effective channel length/external resistance extraction algorithm for MOSFETs,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1245–1251, Sept. 1984. [19] R. V. Booth, M. H. White, H. S. Wong, and T. J. Krutsick, “The effect of channel implants on MOS transistor characterization,” IEEE Trans. Electron Devices, vol. ED-34, pp. 2501–2508, Dec. 1987. Patterning Sub-30-nm MOSFET Gate with Lithography -Line Kazuya Asano, Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu Abstract—We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gate. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput -beam lithography. They provide 25-nm gate pattern with -line lithography and sub-20-nm pattern with -beam lithography. A 40-nm gate channel length nMOSFET is demonstrated. I. INTRODUCTION Currently, MOSFET gate length for advanced research is below 50 nm. Making such a small feature is not an easy task, in general. Although e-beam lithography employing some positive resists such as PMMA has high resolution, its throughput is too low even for research. Manuscript received May 30, 2000; revised October 12, 2000. This work was supported by DARPA AME Program under Contract N66001-97-1-8910. The review of this brief was arranged by Editor R. Singh. K. Asano is with the NKK Corporation, Kanagawa 212-0013, Japan. Y.-K. Choi, T.-J. King, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail: ykchoi@eecs.berkeley.edu). Publisher Item Identifier S 0018-9383(01)03256-7. We will discuss two techniques that provide sub-30-nm line width without using any special equipment or materials. The first technique is resist ashing. This technique was developed for making submicron devices from g-line lithography about ten years ago [1]. Since then, it has been rather widely used to produce smaller features than the resolution limit of optical lithography [2]–[4]. The second technique is an oxide hard mask trimming. Oxide hard mask trimming is relatively straightforward, but we have found no reports that describe it, let alone report on its use in the sub-30-nm regime. A combination of these two techniques makes it possible to fabricate 25 nm line width using i-line lithography. II. EXPERIMENTS AND RESULTS A. Ashing of i-Line Resist Sample wafers were exposed with an i-line stepper. The thickness of the positive i-line resist was 1.1 m and baked at 90 C for 1 min before exposure and 120 C for 1 min after exposure, respectively. The resist patterns after a development were ashed in an oxygen-plasma asher, Technics PE II. Oxygen pressure was 260 mTorr with a flow rate of 51.1 sccm. The ashing rate of the i-line resist without hard baking (120 C) is shown in Fig. 1. The vertical ashing rate is the rate of reduction of the resist thickness, while the horizontal ashing rate is the rate of reduction of the line width. Both ashing rates change linearly with the ashing power and are independent of the initial line width. The ratio of the horizontal ashing rate to the vertical ashing rate is about 1.2:1, which produces isotropic profile. Ashing does not change the edge roughness of the resist as shown in Fig. 2(a). The smoothness of the initial lines is very important for good ashing results. In the case of i-line lithography, line smoothness depends strongly on the mask quality. The taper angle of the narrow resist profile at the top corner increases slightly after ashing. The top of the resist may be rounded in the end. This can happen earlier in narrow lines than in wide patterns. Even if the top of the resist is rounded off, etching does not present a problem as long as the resist is thick enough. B. Ashing e-Beam Resist Two chemically amplified resists, SNR-2000 and SAL601, were evaluated. Ashing of the e-beam resists was done in the same asher, Technics PE II. In the case of e-beam resist patterns, only a small amount of ashing compared to i-line patterns is needed because the initial line width is 100 nm or less. We fixed the ashing power at 5 W, which was the lowest power to sustain stable plasma. The ashing rates of the e-beam resists are 22–30 nm/min at 5 W power. For SAL and SNR, the ashing rates were almost the same. One interesting phenomenon is resist hardening caused by SEM. Since SAL and SNR are negative resists, they are hardened by the exposure to e-beam (energy is less than 1 KeV) during SEM. After SEM, ashing rate of the resist patterns exposed to the e-beam decreased to two-thirds of those not exposed. In Fig. 3(a), the SEM picture of a 17-nm ashed SNR-2000 resist line is shown. This line was originally 80-nm wide after e-beam lithography. C. Oxide Hard Mask Trimming The concept of oxide hard mask trimming is similar to the resist ashing. After the ashing-down of the gate resist patterns, an oxide hard mask pattern is anisotropically etched. A Lam research model 0018–9383/01$10.00 © 2001 IEEE
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