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Author(s)
Citation
Effective channel length and external series resistance
models of scaled LDD pMOSFETs operating in a Bi-MOS
hybrid-mode environment.( Published version )
Seah, Lionel Siau Hing.; Yeo, Kiat Seng.; Ma, Jianguo.;
Do, Manh Anh.
Seah, S. H., Yeo, K. S., Ma, J. G., & Do, M. A. (2001).
Effective channel length and external series resistance
models of scaled LDD pMOSFETs operating in a Bi-MOS
hybrid-mode environment. IEEE Transactions on Electron
Devices, 48(5), 1001-1004.
Date 2001
URL
http://hdl.handle.net/10220/4708
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 1001
reduction can be utilized to improve the low-frequency noise performance
of analog circuits implemented in triple-well CMOS technologies
[15]–[17].
ACKNOWLEDGMENT
The authors are grateful to Dr. G. Bosman for valuable comments
and suggestions.
REFERENCES
[1] F. N. Hooge, “1/f noise,” Physica, vol. 83B, pp. 14–23, 1976.
[2] L. K. J. Vandamme, “Model for 1/f noise in MOS transistors biased in
the linear region,” Solid-State Electron., vol. 23, pp. 317–323, 1980.
[3] A. L. McWhorter, Semiconductor Surface Physics. Philadelphia, PA:
Univ. of Pennsylvania Press, 1957, pp. 207–228.
[4] S. Christensson, I. Lundstrom, and C. Svensson, “Low frequency noise
in MOS transistors—I (Theory),” Solid-State Electron., vol. 11, pp.
797–812, 1968.
[5] , “Low frequency noise in MOS transistors—II (Experiment),”
Solid-State Electron., vol. 11, pp. 813–820, 1968.
[6] F. M. Kaassen, “Characterization of low 1/f noise in MOS transistors,”
IEEE Trans. Electron Devices, vol. ED-18, pp. 887–891, Oct. 1971.
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[8] K. H. Duh and A. van der Ziel, “Flicker noise in MOSFET’s with
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[9] C. Jakobson, I. Bloom, and Y. Nemirovsky, “1/f noise in CMOS transistors
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Electron., vol. 42, no. 10, pp. 1807–1817, 1998.
[10] S. L. Jang, H. K. Chen, and M. C. Hu, “Low frequency 1/f noise model
for short LDD MOS FET’s,” Solid-State Electron., vol. 42, no. 6, pp.
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[11] J. Brini, G. Ghibaudo, G. Kamarinos, and O. Roux-dit-Buisson, “Scaling
down and low frequency noise in MOSFET’s,” Amer. Inst. Phys., pp.
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[12] M. H. Tsai and T. P. Ma, “The impact of device scaling on the current
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[14] M. J. Deen and Y. Zhu, “1/f noise in n-channel MOSFET’s at high
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[15] T. Takayanagi, K. Sawada, T. Sakurai, Y. Parameswar, S. Tanaka,
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[17] W. Muth, “Matrix method for latch-up free demonstration in a
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I, pp. 396–400, Mar. 1992.
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Effective Channel Length and External Series Resistance
Models of Scaled LDD pMOSFETs Operating in a Bi-MOS
Hybrid-Mode Environment
Siau Hing Lionel Seah, Kiat Seng Yeo, Jian Guo Ma, and
Manh Anh Do
Abstract—The effective channel length and total external series
resistance
of deep submicron lightly doped drain (LDD)
pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have
been modeled as functions of bias and temperature. The accuracy of the
device threshold voltage used in the and extraction routine
is discussed. The proposed models have been verified for temperature
ranging from 223 K to 398 K and source-to-body voltage 0 V
conditions.
Index Terms—Deep submicron, effective channel length, external series
resistance, hybrid-mode, lightly doped drain (LDD), temperature-dependent.
I. INTRODUCTION
The L e and R TOText are important parameters needed to accurately
model the I-V characteristics of short-channel LDD MOSFETs
[1]. Most analyses in the literature (e.g., [2]–[12]) either ignore the
body terminal of the devices, assume the body and source terminals
having the same potential, or consider the source-body junction
in reverse biased mode. Recently, hybrid-mode devices employing
lateral p-n-p BJT in a pMOS structure have been brought into attention
due to their high current gain and simple technology [13]–[15].
For a device operating in a Bi-MOS hybrid-mode environment, its
gate and body terminals may be biased independently such that potential
across the source-body junction becomes greater than 0 V,
while maintaining the MOSFET in active mode. This requirement
has prompted the question of whether or not L e and R TOText commonly
extracted from the experimental data remain valid for V SB 0
V. The knowledge of such dependency on the body bias is important
to ensure proper prediction of the device performance in hybrid-mode
operation.
II. DEVICE STRUCTURES AND MEASURING EQUIPMENT
The device structure used in the measurement consists of a series
of silicon p-channel LDD MOSFETs fabricated with a gate oxide
thickness t ox of 5 nm. The channel width W for all devices is 20
m, whereas the gate length L varies from 1 m down to 0.25
m. N-well implantation was formed using phosphorus of 2 2 10 13
cm 02 dosage and an energy level of 600 keV. The drain/source
implantation was carried out using boron with a dose of 3 2 10 15
cm 02 and an energy level of 30 keV. The p 0 LDD implants were
established with a dose of 2 2 10 14 cm 02 and an energy level
of 20 keV. The p + junction depth X j and the p-LDD junction
depth r j are approximately 0.15 m and 0.075 m, respectively. A
channel implant dose of 3 2 10 12 cm 02 and an energy level of 70
keV is added for threshold voltage adjustment. Device measurements
were performed using a semiconductor parameter analyzer and a
TEMPTRONIC system which controls the temperature of the wafer
Manuscript received June 19, 2000; revised September 22, 2000. The review
of this brief was arranged by Editor M. Hirose.
The authors are with the Division of Circuits and Systems, School of Electrical
and Electronic Engineering, Nanyang Technological University, Singapore
639798.
Publisher Item Identifier S 0018-9383(01)03255-5.
0018–9383/01$10.00 © 2001 IEEE

1002 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001
to an accuracy of 6 0.5 K. Measurements were done and repeated
on a vibration-free table with the CASCADE MICROTECH probing
station enclosed in a light-shield box.
III. R TOText AND L e EXTRACTION AND MODELING
Assuming symmetrical device and applying very low source-todrain
voltage V SD , the total source-to-drain resistance across the
extrinsic pMOSFET can be derived from the liner region drain current
expression as in [16], expressed as
R tot = R TOText(V SG;V SB;T)
L 0 1L(V SG ;V SB ;T)
+
pe C ox W (V SG 0 V te 0 0:5V SD )
(1)
where
R TOText
1L
sum of resistances of the contact, wiring, p + diffusion
region, and p 0 lightly doped regions of the source and
drain side;
channel length reduction;
C ox gate oxide capacitance per unit area;
pe temperature-dependent hole mobility adapted from [17].
Expressions similar to (1) have been reported in [1]–[8], [18]. However,
they have generally made use of a device threshold voltage obtained
at room temperature and V SB = 0 V. As widely known, the
threshold voltage of short-channel devices is related to the drain/body
bias, channel length and temperature. Hence, using a bias/temperature-independent
threshold voltage in the extraction routine would be
inadequate for V SB 0 V and/or when the temperature differs from
the room temperature. To overcome this problem, an effective threshold
voltage suitable for Bi-MOS hybrid-mode operating condition is used
here. The effective threshold voltage, considering drain-induced barrier
lowering (DIBL), body-induced-barrier-lowering (BIBL), and temperature
effects, is expressed as
Fig. 1. Effects of V on the effective threshold voltage V . The data
markers , , , , , }, 4, and represent the extracted threshold voltage
at 223 K, 248 K, 273 K, 300 K, 323 K, 348 K, 373 K, and 398 K, respectively.
The solid lines represent the modeled results using TC = 0:25 V and
TC =0:23 V.
V te = V TO 0 V SD 0 V SB 0 (TC 1 + TC 2V SB)
T
1
300 K 0 1 (2)
where V TO is the zero-bias threshold voltage extracted at T = 300
K using the “Transconductance Peak” method [19]. For V SD =0:05
V considered here, the DIBL effect contributed by the term V SD
can be ignored. The BIBL factor accounts for the reduction
in the threshold voltage when V SB increases [13]. The parameter
TC 1 is defined as the temperature compensation factor extracted at
V SB = V SD =0V, whereas TC 2 is the temperature compensation
factor for V SB > 0 V. The composite effect of V SB and temperature
on V te is illustrated in Fig. 1. At V SB =0V, V te reduces about
23% when the temperature increases from 223 K to 398 K. However,
for V SB > 0 V, the reduction rate of V te with temperature
increases. The use of (2) in the extraction procedure implies that for a
specific source-to-gate bias V SG , the gate drive V GT =(V SG 0V te 0
0:5V SD) varies with L, T and V SB through V te . Therefore, any
extraction errors contributed by using a bias/temperature-independent
threshold voltage are avoided.
As widely known, the carrier density modulation effect in the
overlapping regions between the lightly doped regions and the gate
in the LDD structure, and the fringing field conductivity modulation
effect cause R TOText to be gate-bias-dependent. On the other hand,
the increase in gate control over the mobile charge at the two ends of
the channel leads to the expansion of the effective channel toward the
source and drain regions. Fig. 2 shows R TOText and 1L at various
Fig. 2. Gate modulation effects of R and 1L observed using “Paired
V ” method [3]. Data markers and represent the R and 1L
at 300 K, respectively; and represent the R and 1L at 398 K and
4 and represent the R and 1L at 223 K.
temperatures exhibiting similar declining trends with increasing V GT .
For V SB = 0 V and T = 300 K, R TOText and 1L decrease by
28.75% and 18.02%, respectively, as the gate drive V GT increases
from 0.55 V to 1.95 V. Reductions in R TOText and 1L result in higher
V SDe appearing across a “longer” intrinsic pMOSFET channel. This
phenomenon is critical in deep submicron devices because of the
associated scaling of supply voltage (i.e., V SD) applied to the extrinsic
pMOSFET. If gate-bias-independent R TOText and 1L values, extrapolated
at a low gate bias, are used in modeling the I-V characteristics
of the device, underestimation of source-to-drain current I SD would be
resulted at high V SG biases. Therefore, the determination of R TOText
(V SG ) and 1L (V SG ) is important to ensure accurate prediction of the
device characteristics for a wide range of gate biases.
To investigate the effect of V SB and temperature independently, the
extracted R TOText and 1L are averaged over the entire V GT range
considered earlier. This is accomplished by extending the method
proposed in [18] to various V SB biasing and temperature conditions.
This technique allows the isolation of the gate modulation effect and
yet does not require a fixed gate bias to be defined. In retrospect

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 1003
TABLE I
EXTRACTED COEFFICIENTS FOR THE R
OUR DEVICES
AND 1L MODELS FOR
Combining the gate bias modulation, temperature and body bias effects,
the R TOText () and L e (m) are modeled as
R TOText (V SG ;V SB ;T)=aT + b 0 c(V SG 0 V te ) 0 dV SB (3)
L e (V SG;V SB;T)=L(m) 0 1L(V SG;V SB;T) (4)
1L(V SG ;V SB ;T)=eT + f 0 g(V SG 0 V te ) 0 hV SB (5)
Fig. 3. Dependence of R and 1L on source-body voltage V and
temperature (inset).
where a; b; c; d; e; f; g; and h are coefficients extracted experimentally,
given in Table I. The validity of the proposed R TOText , L e and V te
models are verified by applying the modeled values into conventional
drain current model expression as in [16]. Fig. 4 demonstrates good
agreements between the experimental and modeled drain current characteristics
for a wide range of biases and temperatures.
IV. CONCLUSIONS
The R TOText and L e of scaled hybrid-mode devices have been
investigated. Together with a novel V te expression, analytical L e
and R TOText models useful for devices operating in a Bi-MOS hybrid-mode
environment have been presented. By including the effect of
body bias and temperature in the R TOText , L e , and V te models, the
drain current characteristics of scaled devices operating in a Bi-MOS
hybrid-mode environment can be predicted accurately using conventional
drain current expression.
ACKNOWLEDGMENT
Fig. 4. Prediction of the drive current (solid lines) for different temperatures,
gate lengths and body/gate terminal biases. The markers , }, and 4 represent
the measurement data for V = 0 V, 0.4 V, and 0.6 V, respectively.
[4], a very slight increment in R TOText and 1L with temperature
has been observed, as depicted in Fig. 3 (inset). Although applying
V SB > 0 V reduces the charge sharing effect [5], [7], narrowing
of the depletion width at the source-body and drain-body junctions
lengthens the effective channel region, justified by the reduction in
1L with increasing V SB as indicated in Fig. 3. It is interesting to note
that this channel lengthening effect appears to increase the numerator
of the second term in (1), and hence the channel resistance. However,
applying V SB also causes the physical broadening of the channel
formation under the gate. In contrast, this phenomenon reduces the
intrinsic channel resistance. As mentioned earlier, increasing V SB
reduces V te . This effect reduces the channel resistance per unit
length and is well represented by utilizing V te in the second term in
(1). As compared to V SB =0V condition, I SD increases when the
device is biased with V SB > 0 V. For a fixed V SD, R tot = V SD=I SD
reduces as a result. From the experimental results, the drop in R tot
resulted from the increase in channel carriers collected at the drain
region is also reflected in the trend of R TOText, as shown in Fig. 3.
Therefore, the results have proven that one important contributing
factor to I SD increment for V SB > 0 V is the composite effect
between the resultant R TOText , 1L, and V te .
The authors would like to acknowledge Chartered Semiconductor
Manufacturing Ltd for supplying the test wafers. They are also grateful
to the reviewers for their valuable comments.
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[1] S. S. S. Chung and J. S. Lee, “A new approach to determine the
drain-and-source resistance of LDD MOSFETs,” IEEE Trans. Electron
Devices, vol. 40, pp. 1709–1711, Sept. 1993.
[2] J. Y. C. Sun, M. R. Wordeman, and S. E. Laux, “On the accuracy of
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[4] Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I.
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ratio method for MOSFET channel-length extraction,” IEEE Electron
Device Lett., vol. 13, pp. 267–269, May 1992.
[5] S. Hong and K. Lee, “Extraction of metallurgical effective channel
length in LDD MOSFETs,” IEEE Trans. Electron Devices, vol. 42, pp.
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[6] Y. S. Jean and C. Y. Wu, “A new extraction algorithm for the metallurgical
channel length of conventional and LDD MOSFETs,” IEEE Trans.
Electron Devices, vol. 43, pp. 946–953, June 1996.
[7] C. M. Wu and C. Y. Wu, “A new method for extracting the
channel-length reduction and the gate-voltage-dependent series resistance
of counter-implanted p-MOSFETs,” IEEE Trans. Electron
Devices, vol. 44, pp. 2193–2199, Dec. 1997.
[8] T. H. Chang, J. G. Lo, T. C. Kuo, C. C. H. Hsu, S. Y. Yu, K. F. Tseng, and
L. S. Lu, “Effective channel length and source-drain series-resistance determination
after electrical gate length verification of metal-oxide-semiconductor
field-effect-transistor,” Jpn. J. Appl. Phys., vol. 37, part 1, no.
3A, pp. 796–800, Mar. 1998.

1004 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001
[9] K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent
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[12] S. S. Liu and S. L. Jang, “Deep-submicron lightly-doped-drain and
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[13] S. S. Rofail and K. S. Yeo, “Experimentally-based analytical model of
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IEEE Trans. Electron Devices, vol. 44, pp. 1473–1482, Sept.
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[14] S. A. Parke, C. H. Hu, and P. K. Ko, “Bipolar-FET hybrid-mode operation
of quarter-micrometer SOI MOSFETs,” IEEE Electron Device
Lett., vol. 14, pp. 234–236, May 1993.
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[16] K. Y. Toh, P. K. Ko, and R. G. Meyer, “An engineering model for
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[17] B. H. Cheng and J. Woo, “A temperature-dependent MOSFET inversion
layer carrier mobility model for device and circuit simulation,” IEEE
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Patterning Sub-30-nm MOSFET Gate with
Lithography
-Line
Kazuya Asano, Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu
Abstract—We have investigated two process techniques: resist ashing
and oxide hard mask trimming. A combination of ashing and trimming
produces sub-30-nm MOSFET gate. These techniques require neither
specific equipment nor materials. These can be used to fabricate experimental
devices with line width beyond the limit of optical lithography or
high-throughput -beam lithography. They provide 25-nm gate pattern
with -line lithography and sub-20-nm pattern with -beam lithography.
A 40-nm gate channel length nMOSFET is demonstrated.
I. INTRODUCTION
Currently, MOSFET gate length for advanced research is below
50 nm. Making such a small feature is not an easy task, in general.
Although e-beam lithography employing some positive resists such as
PMMA has high resolution, its throughput is too low even for research.
Manuscript received May 30, 2000; revised October 12, 2000. This work was
supported by DARPA AME Program under Contract N66001-97-1-8910. The
review of this brief was arranged by Editor R. Singh.
K. Asano is with the NKK Corporation, Kanagawa 212-0013, Japan.
Y.-K. Choi, T.-J. King, and C. Hu are with the Department of Electrical Engineering
and Computer Sciences, University of California, Berkeley, CA 94720
USA (e-mail: ykchoi@eecs.berkeley.edu).
Publisher Item Identifier S 0018-9383(01)03256-7.
We will discuss two techniques that provide sub-30-nm line width
without using any special equipment or materials. The first technique
is resist ashing. This technique was developed for making submicron
devices from g-line lithography about ten years ago [1]. Since then, it
has been rather widely used to produce smaller features than the resolution
limit of optical lithography [2]–[4]. The second technique is
an oxide hard mask trimming. Oxide hard mask trimming is relatively
straightforward, but we have found no reports that describe it, let alone
report on its use in the sub-30-nm regime. A combination of these two
techniques makes it possible to fabricate 25 nm line width using i-line
lithography.
II. EXPERIMENTS AND RESULTS
A. Ashing of i-Line Resist
Sample wafers were exposed with an i-line stepper. The thickness
of the positive i-line resist was 1.1 m and baked at 90 C for 1 min
before exposure and 120 C for 1 min after exposure, respectively. The
resist patterns after a development were ashed in an oxygen-plasma
asher, Technics PE II. Oxygen pressure was 260 mTorr with a flow rate
of 51.1 sccm.
The ashing rate of the i-line resist without hard baking (120 C) is
shown in Fig. 1. The vertical ashing rate is the rate of reduction of the
resist thickness, while the horizontal ashing rate is the rate of reduction
of the line width. Both ashing rates change linearly with the ashing
power and are independent of the initial line width.
The ratio of the horizontal ashing rate to the vertical ashing rate is
about 1.2:1, which produces isotropic profile. Ashing does not change
the edge roughness of the resist as shown in Fig. 2(a). The smoothness
of the initial lines is very important for good ashing results. In the case
of i-line lithography, line smoothness depends strongly on the mask
quality.
The taper angle of the narrow resist profile at the top corner increases
slightly after ashing. The top of the resist may be rounded in the end.
This can happen earlier in narrow lines than in wide patterns. Even if
the top of the resist is rounded off, etching does not present a problem
as long as the resist is thick enough.
B. Ashing e-Beam Resist
Two chemically amplified resists, SNR-2000 and SAL601, were
evaluated. Ashing of the e-beam resists was done in the same asher,
Technics PE II.
In the case of e-beam resist patterns, only a small amount of ashing
compared to i-line patterns is needed because the initial line width is
100 nm or less. We fixed the ashing power at 5 W, which was the lowest
power to sustain stable plasma. The ashing rates of the e-beam resists
are 22–30 nm/min at 5 W power. For SAL and SNR, the ashing rates
were almost the same.
One interesting phenomenon is resist hardening caused by SEM.
Since SAL and SNR are negative resists, they are hardened by the exposure
to e-beam (energy is less than 1 KeV) during SEM. After SEM,
ashing rate of the resist patterns exposed to the e-beam decreased to
two-thirds of those not exposed.
In Fig. 3(a), the SEM picture of a 17-nm ashed SNR-2000 resist line
is shown. This line was originally 80-nm wide after e-beam lithography.
C. Oxide Hard Mask Trimming
The concept of oxide hard mask trimming is similar to the resist
ashing. After the ashing-down of the gate resist patterns, an oxide
hard mask pattern is anisotropically etched. A Lam research model
0018–9383/01$10.00 © 2001 IEEE