Curriculum vitae (pdf, en, 50 KB, 10/23/13)
Curriculum vitae (pdf, en, 50 KB, 10/23/13)
Curriculum vitae (pdf, en, 50 KB, 10/23/13)
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Sara Vinco<br />
Name Sara Vinco<br />
Date of birth July 27, 1985<br />
Citiz<strong>en</strong>ship Italian<br />
Address Via Sanzio B<strong>en</strong>azzi 15, 37<strong>13</strong>5, Verona (VR)<br />
Email sara.vinco@univr.it<br />
Web page www.di.univr.it/~vinco<br />
Position and Education<br />
RECORD OF EMPLOYMENT<br />
January 20<strong>13</strong> – pres<strong>en</strong>t<br />
Research associate at the Departm<strong>en</strong>t of Computer Sci<strong>en</strong>ce of the University of Verona. Project title:<br />
Automatic device driver g<strong>en</strong>eration for HW accelerators in multi-core systems.<br />
December 20<strong>10</strong> January 2011<br />
Research assistant at the Computer Sci<strong>en</strong>ce Departm<strong>en</strong>t of the University of Verona – COCONUT project<br />
grant. Project title: Definition of the architecture of an EFSM g<strong>en</strong>erator.<br />
June July 20<strong>10</strong><br />
Research assistant at the Computer Sci<strong>en</strong>ce Departm<strong>en</strong>t of the University of Verona. Project title: Application<br />
of the COCONUT flow to the refer<strong>en</strong>ce platform for the final experim<strong>en</strong>tation of the project<br />
technologies.<br />
January 20<strong>10</strong> December 2012<br />
Ph.D. stud<strong>en</strong>t of the Sci<strong>en</strong>ce Engineering Medicine Graduate School of the University of Verona. Advisor:<br />
Prof. Franco Fummi.<br />
October December 2009<br />
Research assistant at the Computer Sci<strong>en</strong>ce Departm<strong>en</strong>t of the University of Verona. Project title: Automatic<br />
g<strong>en</strong>eration of device drivers for MPSoCs.<br />
September 2007<br />
Research assistant at the Computer Sci<strong>en</strong>ce Departm<strong>en</strong>t of the University of Verona. Project title: Integration<br />
of an abstract middleware in a co-simulation <strong>en</strong>vironm<strong>en</strong>t.<br />
EDUCATION<br />
• Ph.D. in Computer Sci<strong>en</strong>ce, University of Verona, 20<strong>13</strong>.<br />
Thesis Title: Reuse and Integration of Heterog<strong>en</strong>eous Compon<strong>en</strong>ts for Effici<strong>en</strong>t Embedded Software G<strong>en</strong>eration<br />
Advisor: Prof. F. Fummi<br />
Reviewer: Prof. P. Mishra, Prof. D. Sciuto<br />
Thesis pres<strong>en</strong>ted at the annual ACM/SigDa PhD Forum at ACM/IEEE Design Automation & Test in<br />
Europe Confer<strong>en</strong>ce (DATE), 2012, and at the annual ACM/SigDa PhD Forum at ACM/IEEE Design<br />
Automation Confer<strong>en</strong>ce (DAC), 2012.
• M. Sc. in Computer Sci<strong>en</strong>ce, University of Verona. July 2009. Grade: 1<strong>10</strong>/1<strong>10</strong> cum laude.<br />
Thesis title: A methodology for automatic device driver g<strong>en</strong>eration<br />
Advisor Prof. F. Fummi<br />
• B.Sc. in Computer Sci<strong>en</strong>ce, University of Verona. July 2007. Grade: 1<strong>10</strong>/1<strong>10</strong> cum laude.<br />
Thesis title: An abstract-middleware based methodology for the design of networked embedded systems<br />
Advisor Prof. F. Fummi<br />
• Sci<strong>en</strong>tific high school diploma at Liceo A. Messedaglia, Verona. 2004. Grade: <strong>10</strong>0/<strong>10</strong>0 cum laude.<br />
VISITING EXPERIENCES<br />
September - November 20<strong>13</strong><br />
Visiting scholar at the University of Southampton.<br />
Hosting professor: Prof. M. Zwolinski.<br />
Project title: Formal modeling of analog circuit descriptions with VHDL-AMS and Verilog-AMS to gain<br />
C++ code g<strong>en</strong>eration.<br />
Sponsored by a CooperInt grant from the University of Verona.<br />
June - December 2011<br />
Visiting scholar at the University of Michigan.<br />
Hosting professor: Prof. V. Bertacco.<br />
Project title: Effici<strong>en</strong>t simulation of SystemC systems on GPGPUs.<br />
SUMMER SCHOOLS<br />
• SWING, School on Security of Wireless Networking, 20<strong>10</strong>.<br />
• Mobile Computing and Communications: Towards the Next G<strong>en</strong>eration of Networks, J.T. Schwartz International<br />
School for Sci<strong>en</strong>tific Research. 20<strong>10</strong>.<br />
• ARTIST Summer School in Europe, Artist European Network of Excell<strong>en</strong>ce on Embedded Systems.<br />
20<strong>10</strong>.<br />
SCHOLARSHIPS AND RESEARCH AWARDS<br />
• CooperInt (COOPERazione INTernazionale) cooperation grant from the University of Verona to support<br />
the stay at University of Southampton. 2012.<br />
• Travel awards from ACM and SigDa to att<strong>en</strong>d both the the annual ACM/SigDa PhD Forum at ACM/IEEE<br />
Design Automation & Test in Europe Confer<strong>en</strong>ce (DATE), 2012, and at the annual ACM/SigDa PhD<br />
Forum at ACM/IEEE Design Automation Confer<strong>en</strong>ce (DAC), 2012.<br />
• Best paper award at the IEEE Forum on Design Languages in 2011 for the paper Effici<strong>en</strong>t implem<strong>en</strong>tation<br />
and abstraction of SystemC data types for fast simulation.<br />
• Premio di Laurea AICA - Confindustria Servizi Innovativi e Tecnologici grant for the value of the master<br />
thesis in terms of applicability in the Italian industrial context. 20<strong>10</strong>.<br />
• E.S.U. grant from the University of Verona to att<strong>en</strong>d a course of English grammar and culture at the<br />
Nottingham Tr<strong>en</strong>t University (Nottingham, England, UK). 2005.<br />
2
PRESENTATIONS AND POSTER SESSIONS<br />
• On the Use of GP-GPUs for Accelerating Compute-int<strong>en</strong>sive EDA Applications, IEEE/ACM Design And<br />
Test in Europe Confer<strong>en</strong>ce (DATE), March 18, 21, 20<strong>13</strong>, Gr<strong>en</strong>oble, Embedded tutorial.<br />
• Energy Aware TLM Platform Simulation via RTL Abstraction, IEEE High Level Design Validation and<br />
Test Workshop (HLDVT), November 7-12, 2012, Huntington Beach.<br />
• Accurate Profiling of Oracles for Self-Checking Time-Constrained Embedded Software, IEEE High Level<br />
Design Validation and Test Workshop (HLDVT), November 7-12, 2012, Huntington Beach.<br />
• The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterog<strong>en</strong>eous Embedded Systems, IEEE High<br />
Level Design Validation and Test Workshop (HLDVT), November 7-12, 2012, Huntington Beach.<br />
• Reconciliation of Heterog<strong>en</strong>eous Embedded System Domains to Gain a Homog<strong>en</strong>eous SW Repres<strong>en</strong>tation,<br />
ACM/SigDa PhD Forum at ACM/IEEE Design Automation Confer<strong>en</strong>ce (DAC), June 01-<strong>10</strong>, 2012,<br />
San Francisco, Poster session.<br />
• SAGA: SystemC Acceleration on GPU Architectures, IEEE Design Automation Confer<strong>en</strong>ce (DAC), June<br />
01-<strong>10</strong>,2012, San Francisco.<br />
• UNIVERCM: a Formal Computational Model for Heterog<strong>en</strong>eous Embedded Systems, ACM/SigDa PhD<br />
Forum at ACM/IEEE Design Automation & Test in Europe Confer<strong>en</strong>ce (DATE), March 12-15, 2012,<br />
Dresd<strong>en</strong>, Poster session.<br />
• MOUSSE: scaling MOdelling and verification to complex heterog<strong>en</strong>eoUS embedded Systems Evolution,<br />
ACM/IEEE Design Automation & Test in Europe Confer<strong>en</strong>ce (DATE), March 12-15, 2012, Dresd<strong>en</strong>.<br />
• Reusing of Properties after Discretization of Hybrid Automata, IEEE Microprocessor Test and Verification<br />
(MTV), December 5-7, 2011, Austin.<br />
• Reusing of Properties after Discretization of Hybrid Automata, IEEE High-Level Design Validation and<br />
Test Workshop (HLDVT), November <strong>10</strong>-11, 2011, Napa Valley, Poster session.<br />
• UNIVERCM the UNIversal VERsatile Computational Model for heterog<strong>en</strong>eous embedded system design,<br />
IEEE High-Level Design Validation and Test Workshop (HLDVT), November <strong>10</strong>-11, 2011, Napa Valley.<br />
• On the Mutation Analysis of SystemC TLM-2.0 Standard, IEEE Microprocessor Test and Verification<br />
(MTV), December 5-11, 2009, Austin.<br />
• Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded<br />
Platform, IEEE Microprocessor Test and Verification (MTV), December 5-11, 2009, Austin.<br />
• RTL IP Abstraction into Optimized Embedded Software, IEEE East-West Design and Test Symposium<br />
(EWDTS), September 16-21, 20<strong>10</strong>, St. Petersburg.<br />
• Automatic Customization of Device Drivers for IP-cores Used with Assorted CPU Organizations, ACM/IEEE<br />
International Confer<strong>en</strong>ce on Hardware/Software Codesign and System Synthesis (CODES - ISSS), October<br />
11-16, 2009, Gr<strong>en</strong>oble.<br />
3
Teaching activity<br />
2012-20<strong>13</strong><br />
”Basic Information Technology”, adjunct professor, bachelor degree in Communication Studies, University<br />
of Verona.<br />
”Design of Embedded Systems”, teaching assistant managing the laboratory activities and projects, master<br />
degree in Engineering and Computer Sci<strong>en</strong>ce, University of Verona.<br />
”Computer Architecture”, teaching assistant tutoring stud<strong>en</strong>ts, bachelor degree in Computer Sci<strong>en</strong>ce,<br />
University of Verona.<br />
2011-2012<br />
”Design of Embedded Systems”, teaching assistant managing the laboratory activities and projects, master<br />
degree in Engineering and Computer Sci<strong>en</strong>ce, University of Verona.<br />
”Computer Architecture”, teaching assistant tutoring stud<strong>en</strong>ts, bachelor degree in Computer Sci<strong>en</strong>ce,<br />
University of Verona.<br />
20<strong>10</strong>-2011<br />
”Design of Embedded Systems”, teaching assistant managing the laboratory activities and projects, master<br />
degree in Engineering and Computer Sci<strong>en</strong>ce, University of Verona.<br />
”Computer Architecture”, teaching assistant tutoring stud<strong>en</strong>ts, bachelor degree in Computer Sci<strong>en</strong>ce,<br />
University of Verona.<br />
2008-2009<br />
”Computer Architecture”, teaching assistant tutoring stud<strong>en</strong>ts, bachelor degree in Computer Sci<strong>en</strong>ce,<br />
University of Verona.<br />
”Introduction to Computer Architecture”, teaching assistant tutoring stud<strong>en</strong>ts, bachelor degree in Bioinformatics,<br />
University of Verona.<br />
STUDENTS’ SUPERVISION<br />
Master/Bachelor Stud<strong>en</strong>ts Supervision<br />
• Davide Costanzi, G<strong>en</strong>erazione automatica di modelli IP-XACT, Bachelor Degree in Computer Sci<strong>en</strong>ce,<br />
Advisor Prof. G. Pravadelli. AA. 2012/20<strong>13</strong>.<br />
• Michele Pizzini, Automatic G<strong>en</strong>eration of APU Ori<strong>en</strong>ted Software Applications from RTL IPs, Master<br />
Degree in Engineering and Computer Sci<strong>en</strong>ce. Advisor Prof. F. Fummi. AA. 2012/20<strong>13</strong> (thesis writing<br />
in process).<br />
• Diego Braga, The IP-XACT formalism for modeling heterog<strong>en</strong>eous embedded systems, Master Degree<br />
in Engineering and Computer Sci<strong>en</strong>ce, AA. 20<strong>10</strong>/2011.<br />
• Massimo B<strong>en</strong>edetti, G<strong>en</strong>erazione automatica di SW embedded a partire da descrizioni TLM, Master<br />
Degree in Computer Sci<strong>en</strong>ce. Advisor Prof. F. Fummi. AA. 2009/20<strong>10</strong>.<br />
• Diego Forrini, Astrazione di IP RTL in software dedicato e ottimizzazione mediante astrazione dei tipi<br />
di dato HDL , Master Degree in Computer Sci<strong>en</strong>ce. Advisor Prof. Franco Fummi. AA. 2009/20<strong>10</strong>.<br />
• Matteo Laur<strong>en</strong>zi, Astrazione di IP RTL in software dedicato e ottimizzazione mediante astrazione del<br />
protocollo di comunicazione, Master Degree in Computer Sci<strong>en</strong>ce. Advisor Dr. N. Bombieri. AA.<br />
2009/20<strong>10</strong>.<br />
4
Professional Activities<br />
• Co-chair for the track <strong>en</strong>titled ”Hardware/Software Co-design and Design Automation” of the IEEE/IFIP<br />
International Confer<strong>en</strong>ce on Embedded and Ubiquitous Computing (EUC), 2014.<br />
• Program committee member of the IEEE/IFIP International Confer<strong>en</strong>ce on Embedded and Ubiquitous<br />
Computing (EUC), 20<strong>13</strong>.<br />
• Delegate of the Computer Sci<strong>en</strong>ce Ph.D. stud<strong>en</strong>ts in the Computer Sci<strong>en</strong>ce Departm<strong>en</strong>t Council, University<br />
of Verona (20<strong>10</strong>-20<strong>13</strong>).<br />
• Reviewer (or secondary reviewer) for IEEE/ACM confer<strong>en</strong>ces, including IEEE/ACM CODES+ISSS,<br />
IEEE/ACM DATE, IEEE/ACM DAC, IEEE DSD, ECSI/IEEE FDL, ACM/IEEE MEMOCODE, IEEE<br />
SIES, IEEE VLSI, IFIP/IEEE VLSI-SOC, IEEE HLDVT, IEEE/IFIP EUC.<br />
Research interests<br />
The main interest of Sara Vinco’s research is the integration and simulation of heterog<strong>en</strong>eous embedded systems.<br />
In particular, the activity carried out in the latest years spans over the following research lines: integration<br />
of heterog<strong>en</strong>eous compon<strong>en</strong>ts via interface g<strong>en</strong>eration, homog<strong>en</strong>eous formal modeling of heterog<strong>en</strong>eous compon<strong>en</strong>ts<br />
to achieve homog<strong>en</strong>eous simulation, and software g<strong>en</strong>eration.<br />
INTEGRATION OF HETEROGENEOUS COMPONENTS VIA INTERFACE GENERATION<br />
Modern embedded systems are highly heterog<strong>en</strong>eous, as they are composed of a mix of analog and digital<br />
HW, as well as embedded SW. Furthermore, the tight bound with the physical <strong>en</strong>vironm<strong>en</strong>t implies to take into<br />
account physical evolution during the design and verification phases. In this context, reuse is a very difficult<br />
task, as the compon<strong>en</strong>ts to integrate are highly heterog<strong>en</strong>eous. On the other hand, reuse is a winning approach<br />
to save design cost and time. Indeed, top-down approaches allow to optimize and configure each step of design,<br />
but any time that a compon<strong>en</strong>t must be added or changed, the whole design flow must be undergone again.<br />
Giv<strong>en</strong> these motivations, the main goal of this research is to develop a methodology that allows to automate<br />
the integration process. Sara Vinco proposed an innovative methodology for determining the necessary interfaces.<br />
The IP-XACT description of the heterog<strong>en</strong>eous compon<strong>en</strong>ts is analyzed to gather information about<br />
their domain and interface. The IP-XACT design description is th<strong>en</strong> exploited to determine the desired connections<br />
betwe<strong>en</strong> compon<strong>en</strong>ts. A taxonomy allows th<strong>en</strong> to determine the necessary connecting compon<strong>en</strong>ts to<br />
be g<strong>en</strong>erated [IC.15],[IC.<strong>10</strong>].<br />
This step must th<strong>en</strong> be followed by g<strong>en</strong>eration of the interfaces. This is a very error prone and time consuming<br />
process, as interface designers rarely have a deep expertise of the involved compon<strong>en</strong>ts. As a result,<br />
automatic interface g<strong>en</strong>eration is preferable. Sara Vinco ext<strong>en</strong>ded the state of the art by focusing on the g<strong>en</strong>eration<br />
of two types of interfaces: soft drivers and device drivers.<br />
Soft drivers are interfaces allowing communication betwe<strong>en</strong> software compon<strong>en</strong>ts. Wh<strong>en</strong> existing software<br />
has to be reused, it may indeed be necessary to map the services invoked to the correct signature exported by<br />
an existing compon<strong>en</strong>t, or to protect shared data. These tasks are the goal of soft drivers. Their implem<strong>en</strong>tation<br />
is usually associated with software <strong>en</strong>gineering, rather than with embedded design. However, their g<strong>en</strong>eration<br />
is critical wh<strong>en</strong> integrating a heterog<strong>en</strong>eous system. Sara Vinco proposed a flow for automatic g<strong>en</strong>eration of<br />
soft drivers, taking into account the desired type of communication [IC.8].<br />
Device drivers constitute the interface betwe<strong>en</strong> the hardware and the software domain. Their implem<strong>en</strong>tation<br />
is very complex, as the device driver must comply both with the device communication protocol and with<br />
5
the requirem<strong>en</strong>ts and constraints of the underlying CPU architecture. Curr<strong>en</strong>t state of the art exploits formal<br />
specification of the device protocol, that are very difficult to extract wh<strong>en</strong> the hardware compon<strong>en</strong>t is third<br />
party. Sara Vinco contributed by proposing a methodology that extracts the device communication protocol<br />
from the testb<strong>en</strong>ch of the device itself. Furthermore, the g<strong>en</strong>erated device driver can be customized with respect<br />
to the target architecture characteristics, by providing user specifications [JR.3], [IC.2], [IC.3], [IC.8],<br />
[IC.16].<br />
The device driver g<strong>en</strong>eration methodology is also provided with a co-simulation platform, that connects the<br />
QEmu software emulator and SystemC to validate the g<strong>en</strong>erated code and hardware-software communication<br />
[IC.5].<br />
HOMOGENEOUS FORMAL REPRESENTATION OF HETEROGENEOUS COMPONENTS<br />
G<strong>en</strong>erating the necessary interfaces allows communication but preserves the degree of heterog<strong>en</strong>eity of the<br />
system. Co-simulation would allow to validate the system behavior, but it is unreliable as it implies to connect<br />
not only differ<strong>en</strong>t simulators but also differ<strong>en</strong>t models of computation and levels of abstraction. Furthermore,<br />
building a co-simulation framework for managing all the typical domains of embedded systems would be a<br />
very critical and time consuming operation.<br />
Exploiting top-down flows for designing the <strong>en</strong>tire system is the complem<strong>en</strong>tary approach. Approaches<br />
such as Ptolemy and Metropolis allow to provide a system specification and to refine it through a number of<br />
steps, by choosing the appropriate model of computation and communication style of all compon<strong>en</strong>ts. On the<br />
other hand, top-down flows do not allow reuse of existing compon<strong>en</strong>ts.<br />
In this sc<strong>en</strong>ario, Sara Vinco proposed UNIVERCM, an automata based model of computation that covers all<br />
the typical domains of embedded systems. The starting heterog<strong>en</strong>eous compon<strong>en</strong>ts are automatically converted<br />
to the computational model, with transformations that preserve the starting behavior and that are implem<strong>en</strong>ted<br />
in automatic conversion tools, thus supporting a fully bottom-up flow [JR.1], [IC.9], [IC.<strong>13</strong>].<br />
The homog<strong>en</strong>eous description is th<strong>en</strong> used as a starting point for automatic g<strong>en</strong>eration of code for simulation<br />
and validation of the integrated system, or for effici<strong>en</strong>t execution [IC.18],[IC.<strong>13</strong>].<br />
HARDWARE TO SOFTWARE MIGRATION<br />
For long time, hardware implem<strong>en</strong>tation of a functionality has be<strong>en</strong> considered more advisable than the corresponding<br />
software implem<strong>en</strong>tation for gaining better performance and effici<strong>en</strong>cy. Indeed, hardware designs<br />
are customized to the needs and constraints of the surrounding system. A major drawback of this choice is the<br />
cost in terms of money and time: indeed, any change requires to go through a redesign process and to realize<br />
a new custom circuit, thus making integration and reuse extremely chall<strong>en</strong>ging. Furthermore, costs of silicon<br />
realization t<strong>en</strong>d to be high for highly optimized and customized circuits.<br />
The developm<strong>en</strong>t of highly and massively parallel processors, such as multiprocessors and GP-GPUs (G<strong>en</strong>eral<br />
Purpose Graphics Processing Units), has improved by far the effectiv<strong>en</strong>ess and the performance of SW.<br />
The availability of multiple processing units and of light synchronization mechanisms on one side, and the<br />
easiness of reuse and adaptation of software compared to hardware, make software a viable alternative.<br />
In this context, Sara Vinco proposes a range of methodologies that, from a common starting point, gain C++<br />
code g<strong>en</strong>eration with differ<strong>en</strong>t approaches. The starting point is a set of heterog<strong>en</strong>eous existing compon<strong>en</strong>ts,<br />
reconciliated to a single formalism through the UNIVERCM-based approach.<br />
The first approach proposed is the g<strong>en</strong>eration of C++ code implem<strong>en</strong>ting the starting functionality. The<br />
g<strong>en</strong>erated code can be used both as an effici<strong>en</strong>t implem<strong>en</strong>tation of the starting system, or rather as a software<br />
version of its functionality. The g<strong>en</strong>erated compon<strong>en</strong>ts are converted to one or more C++ functions, managed<br />
by a single scheduling routine. The implem<strong>en</strong>tation of the scheduling routine differs whether the support of<br />
continuous time behaviors is preserved [IC.18] or not [IC.6]. The g<strong>en</strong>erated code can also be parallelized by<br />
6
creating local schedulers, associated with differ<strong>en</strong>t execution cores and managing a subset of the C++ functions.<br />
A c<strong>en</strong>tralized scheduler is in charge of synchronizing local schedulers [IC.11].<br />
GP-GPUs offer a massive level of parallelism that can be exploited to speed up computation. In detail,<br />
discrete GP-GPUs can be used to run code that simulates the starting system, while integrated GP-GPUs<br />
(or APUs) can be exploited as hardware accelerators for running software code. Sara Vinco proposed two<br />
flows, targeting each of such sc<strong>en</strong>arios. SAGA proposed a flow to simulate RTL HDL code on GP-GPUs.<br />
RTL processes are partitioned in dataflows according to inter-process dep<strong>en</strong>d<strong>en</strong>cies, and such dataflows are<br />
th<strong>en</strong> associated with differ<strong>en</strong>t cores. Multiple copies of the same dataflow can be run in parallel to increase<br />
throughput and to run more instancies at one time [IC.12], [IC.17], [IC.14]. G<strong>en</strong>erating code for APUs allows<br />
to modify the internal structure of the code, in order to get more performing code. To this ext<strong>en</strong>t, [IC.19]<br />
proposed an approach to exploit both inter-process dep<strong>en</strong>d<strong>en</strong>cies and pipeline structure of the starting designs<br />
to achieve massively parallel execution in software on APUs.<br />
The code g<strong>en</strong>eration flows have be<strong>en</strong> accompanied by the implem<strong>en</strong>tation of an effici<strong>en</strong>t data type library,<br />
reproducing hardware data types (e.g., multi-value logic) in a very effici<strong>en</strong>t and performing way. This allows<br />
to preserve compatibility with respect to the starting code, without slowing down the execution or adding the<br />
overhead of hardware libraries (e.g., SystemC) [JR.2], [IC.7].<br />
7
Complete publication list<br />
H-index: 4<br />
Citations: <strong>50</strong><br />
Source: Google Scholar (http://scholar.google.com) – Last accessed: October <strong>23</strong>, 20<strong>13</strong>.<br />
In all the publications, except [IC.12], authors are listed in alphabetical order.<br />
Refereed international journals JR (3)<br />
Refereed international confer<strong>en</strong>ces IC (19)<br />
REFEREED INTERNATIONAL JOURNALS<br />
JR.3.<br />
JR.2.<br />
JR.1.<br />
A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco, Semi-Automatic G<strong>en</strong>eration of Device Drivers for Rapid Embedded<br />
Platform Developm<strong>en</strong>t, in IEEE Transactions on Computer Aided Design, vol. 32, n. 9, pp. 1293-<strong>13</strong>06, 20<strong>13</strong>.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/TCAD.20<strong>13</strong>.2257924]<br />
N. Bombieri, F. Fummi, V. Guarnieri, F. Stefanni, S. Vinco, HDTLib: an effici<strong>en</strong>t implem<strong>en</strong>tation of SystemC data types<br />
for fast simulation at differ<strong>en</strong>t abstraction levels, in International Journal on Design Automation for Embedded Systems,<br />
vol. 16, n. 2, pp. 115-<strong>13</strong>5, 2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.<strong>10</strong>07/s<strong>10</strong>617-012-9092-z]<br />
L. Di Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco, UNIVERCM: the UNIversal VERsatile Computational<br />
Model for Heterog<strong>en</strong>eous System Integration, in IEEE Transactions on Computers, 2012, vol. 62, n. 2, pp. 225 - 241,<br />
2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/TC.2012.156]<br />
REFEREED INTERNATIONAL CONFERENCES<br />
IC.19.<br />
IC.18.<br />
IC.17.<br />
IC.16.<br />
IC.15.<br />
IC.14.<br />
IC.<strong>13</strong>.<br />
N. Bombieri, F. Fummi, S. Vinco, On the Automatic G<strong>en</strong>eration of GPUori<strong>en</strong>ted Software Applications from RTL<br />
IPs, in Proceedings of ACM/IEEE International Confer<strong>en</strong>ce on Hardware/Software Codesign and System Synthesis<br />
(CODES+ISSS), pp. 1-<strong>10</strong>, 20<strong>13</strong>.<br />
[doi: (not available yet)]<br />
F. Fummi, M. Lora, F. Stefanni, S. Vinco, Code G<strong>en</strong>eration Alternatives to Reduce Heterog<strong>en</strong>eous Embedded Systems<br />
to Homog<strong>en</strong>eity, Proceedings of ECSI/IEEE/CEDA Forum on specification & Design Languages, pages 1-4, 20<strong>13</strong>.<br />
[doi: (not available yet)]<br />
F. Fummi, D. Chatterjee, V. Bertacco, N. Bombieri, S. Vinco, H.D. Patel, On the use of GP-GPUs for accelerating<br />
computing int<strong>en</strong>sive EDA applications, Embedded tutorial in Proceedings of IEEE/ACM Design And Test in Europe<br />
Confer<strong>en</strong>ce (DATE), pp. <strong>13</strong>57-<strong>13</strong>66, 20<strong>13</strong>.<br />
[doi: http://dx.doi.org/<strong>10</strong>.7873/DATE.20<strong>13</strong>.279]<br />
N. Bombieri, F. Fummi, V. Guarnieri, G. Pravadelli, S. Vinco, Redesign and Verification of RTL IPs through RTL-to-<br />
TLM Abstraction and TLM Synthesis, in Proceedigns of IEEE International Workshop on Microprocessor Test and<br />
Verification (MTV), pp. 76-81, 2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/MTV.2012.21]<br />
D. Braga, F. Fummi, G. Pravadelli, S. Vinco, The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterog<strong>en</strong>eous<br />
Embedded Systems, in Proceedings of IEEE High Level Design Validation and Test Workshop (HLDVT), pp. 76-83,<br />
2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/HLDVT.2012.6418246]<br />
N. Bombieri, S. Vinco, V. Bertacco, D. Chatterjee, SystemC Simulation on GP-GPUs: CUDA vs. Op<strong>en</strong>CL, in Proceedings<br />
of IEEE International Confer<strong>en</strong>ce on Hardware/Software Codesign and System Synthesis (CODES-ISSS, ESWEEK<br />
confer<strong>en</strong>ce), pp. 343-352, 2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1145/<strong>23</strong>80445.<strong>23</strong>80<strong>50</strong>0]<br />
L. Di Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco, A Formal Support for Homog<strong>en</strong>eous Simulation of<br />
Heterog<strong>en</strong>eous Embedded Systems, in Proceedings of IEEE International Symposium on Industrial Embedded Systems<br />
(SIES’12), pp. 1-8, 2012.<br />
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8
IC.12.<br />
IC.11.<br />
IC.<strong>10</strong>.<br />
IC.9.<br />
IC.8.<br />
IC.7.<br />
IC.6.<br />
IC.5.<br />
IC.4.<br />
IC.3.<br />
IC.2.<br />
IC.1.<br />
S. Vinco, D. Chatterjiee, V. Bertacco, F. Fummi, SAGA: SystemC Acceleration on GPU Architectures, in Proceedings<br />
of IEEE Design Automation Confer<strong>en</strong>ce (DAC), pp. 115-120, 2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1145/2228360.2228382]<br />
A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco, On the automatic synthesis of parallel SW from RTL models of<br />
hardware IPs, in Proceedings of IEEE ACM Great lakes symposium on VLSI (GLSVLSI), pp. 71-74, 2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1145/2206781.2206800]<br />
M. Becker, G. Bertrand, F. Fummi, W. Mueller, G. Pravadelli, S. Vinco, MOUSSE: scaling MOdelling and verification<br />
to complex heterog<strong>en</strong>eoUS embedded Systems Evolution, in Proceedings of ACM/IEEE Design Automation & Test in<br />
Europe Confer<strong>en</strong>ce (DATE), pp. 296-299, 2012.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/DATE.2012.6176482]<br />
L. Di Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco, UNIVERCM: the UNIversal VERsatile Computational<br />
Model for heterog<strong>en</strong>eous embedded system design, in Proceedings of IEEE High-Level Design Validation and Test<br />
Workshop (HLDVT), pp. 33-40, 2011.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/HLDVT.2011.6114163]<br />
N. Bombieri, F. Fummi, D. Quaglia, S. Vinco, Automatic Interface G<strong>en</strong>eration for Compon<strong>en</strong>t Reuse in HW-SW partitioning,<br />
in Proceedings of EUROMICRO Confer<strong>en</strong>ce on Digital System Design (DSD), pp. 793-796, 2011.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/DSD.2011.<strong>10</strong>5]<br />
N. Bombieri, F. Fummi, V. Guarnieri, F. Stefanni, S. Vinco, Effici<strong>en</strong>t implem<strong>en</strong>tation and abstraction of SystemC data<br />
types for fast simulation, in Proceedings of IEEE Forum on Design Languages – best paper award, pp. 1-7, 2011.<br />
[ISSN: 1636-9874]<br />
N. Bombieri, D. Forrini, F. Fummi, M. Laur<strong>en</strong>zi, S. Vinco, RTL IP Abstraction into Optimized Embedded Software, in<br />
Proceedigns of IEEE East-West Design and Test Symposium (EWDTS), 20<strong>10</strong>.<br />
[doi: (not available yet)]<br />
F. Fummi, G. Perbellini, D. Quaglia, S. Saggin, S. Vinco, Mixing Simulated and Actual Hardware Devices to Validate<br />
device Drivers in a Complex Embedded Platform, in Proceedings of IEEE Microprocessor Test and Verification (MTV),<br />
pp.63-68, 2009.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/MTV.2009.<strong>13</strong>]<br />
F. Fummi, G. Perbellini, D. Quaglia, S. Vinco, A SystemC-c<strong>en</strong>tric Approach for Simulation and G<strong>en</strong>eration of WSN<br />
Applications Targeted to ZigBee, in Proceedings of IEEE International Confer<strong>en</strong>ce on Mobile and Ubiquitous Systems:<br />
Computing, Networking and Services (MobiQuitous), pp. 320-321, 2009.<br />
[doi: http://dx.doi.org/<strong>10</strong>.4<strong>10</strong>8/ICST.MOBIQUITOUS2009.6934]<br />
A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco, Automatic Customization of Device Drivers for IP-cores Used with<br />
Assorted CPU Organizations, in Proceedings of ACM/IEEE International Confer<strong>en</strong>ce on Hardware/Software Codesign<br />
and System Synthesis (CODES - ISSS), pp. 245-254, 2009.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1145/1629435.1629460]<br />
N. Bombieri, F. Fummi, G. Pravadelli, S. Vinco, Correct-by-Construction G<strong>en</strong>eration of Device Drivers Based on RTL<br />
Testb<strong>en</strong>ches, in Proceedings of IEEE Design and Test in Europe Confer<strong>en</strong>ce (DATE), pp. 1<strong>50</strong>0-1<strong>50</strong>5, 2009.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/DATE.2009.<strong>50</strong>90900]<br />
F. Fummi, G. Perbellini, D. Quaglia, S. Vinco, AME: an Abstract Middleware Environm<strong>en</strong>t for validating Networked<br />
Embedded Systems Applications, in Proceedings of IEEE High-Level Design Validation and Test Workshop (HLDVT),<br />
pp.187-194, 2007.<br />
[doi: http://dx.doi.org/<strong>10</strong>.1<strong>10</strong>9/HLDVT.2007.4392812]<br />
Verona, October <strong>23</strong>, 20<strong>13</strong><br />
Signature<br />
Sara Vinco<br />
9