The HERON_IO5V example4 - Hunt Engineering Ltd.

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The HERON_IO5V example4
Rev 1.2 T. Hollis 29-04-05
The HERON-IO5V module is a module that has an FPGA and 2 channels of fast A/D along with 2
channels of fast D/A.
Most users will use the FPGA to provide either a custom I/O capability or a processing resource that
uses the FPGA for that processing. In that case the Example4 project can form a starting point for the
development of that.
Example4 is provided for users who want to use the FPGA to handle and process data between the
A/Ds and D/As, but will not interface with the HERON FIFOs. A user who is embedding a HERON-
IO5V into a system is an example of this.
History
Example revision 1.0 08-04-04 Document first written for HERON-IO5V
Example revision 1.1 08-03-05 Example updated to run at 160MSPS continuous
Example revision 1.2 29-04-05 Removed reference to specific ISE versions
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What the bitstream does
The (Embedded Analogue I/O) example4 project for the HERON-IO5V is supplied on the HUNT
ENGINEERING CD, along with the bitstream that can be loaded directly onto the HERON-IO5V.
If you make changes to the project and re-build it you can change the functionality to be whatever you
want, but if you use the supplied bit stream you need to know what it is doing.
Clock Generation
The standard clock soldered to “User Osc1” of the HERON-IO5V is 100MHz. Example 4 uses one of
the Digital Clock Managers (DCM) as a Digital Frequency Synthesiser (DFS) to generate a 160MHz
clock from the 100MHz “User Osc1”.
In Example 4 the A/D’s and D/A’s have the same sample clock frequency of 160MHz, which has been
chosen as it is the maximum frequency that digital sample values can be transferred to the D/A
converters.
A/D Converters
The Example 4 bitstream uses both channels of A/D and both channels of D/A. The samples from A/D
component A are replayed on D/A channel A, and the inputs from A/D B are simply replayed on D/A
channel B. Both the A/D’s and D/A’s are clocked at the same rate of 160MHz.
The output of each of the A/D converters is two 12bit data busses and a ‘data clock’ output that runs at
half the sample frequency. The two digital values on the two 12 bit busses are the values for two
consecutive samples, these values are clocked into the FPGA using the ‘data clock’ which in the
example runs at (160MHz / 2) = 80MHz .
On the ‘User_Ap4’ interface to the Hardware Interface Layer (HIL) the two 12bit busses for A/D
converter A are ‘ADC_A_A’ and ‘ADC_A_B’ with the data clock is ‘ADC_DCO_A’ and for A/D
converter B they are ‘ADC_B_A’ and ‘ADC_B_B’ with the data clock is ‘ADC_DCO_B’.
Both of the A/D converter data clocks are doubled in frequency back to 160MHz using DCM’s as
frequency doublers. This retains the timing between of the data from the converters and the two
160MHz clocks. The frequency doubling DCM’s need to be held in reset until the input clock is stable,
and in this example this means the DFS that is generating the 160MHz must have acquired lock .
The two new 160MHz clocks can now be used to multiplex the data from A/D converter A onto a
single 12bit buss running at 160MHz, and data from A/D converter B can be multiplexed onto another
12bit buss running at 160MHz.
At this point the both data busses are shifted by 4bits to make 16bit words. These 16bit sample values
are then clocked into two FIFO’s at 160MHz.
D/A Converters
The two D/A converters on the HERON-IO5V are clocked with a single D/A sample clock, which in this
example is 160MHz from the output of the DFS. The read and write clocks on the two FIFO’s will all be
exactly the same frequency but the timing is undefined, which is why the FIFO’s have to be included.
The HUNT ENGINEERING Hardware Interface Layer for the D/A converters also includes a DCM, which
ensures the correct timing of the D/A data relative to the ‘da_data_clock’. This DCM must be held in reset
until the 160MHz from the DFS is stable.
2

HSB
No use is made of the HSB interface, but please note the HE_USER component is still placed and tied
inactive to prevent unconnected signals being interpreted as a request to send an HSB message.
Example 4 is a good confidence check for using with embedded modules. It can be configured into the
FPGA using the HSB, or from the (optional) PROM. When the part is configured signals on the
module analogue inputs should be seen re-constructed on the module analogue outputs.
FUNCTIONAL BLOCK DIAGRAM
2
channels
A/D
FIFO’s and
Formatting
2
channels
D/A
HERON
I/F
HSB
I/F
Inactive
Where are the bitstream and examples?
The bit streams for this example can be found on the HUNT ENGINEERING CD under
\fpga\io5v\embedded_IO(ex4). The name of the .hcb file reflects the FPGA part number i.e.
2v1500fg676.hcb.
There are no DSP or host example as this is an example for stand alone use.
An easier way to navigate to the correct directory is to select the “Files” link next to the “Embedded
Analog I/O” link under the IP sections of the CD browser.
The source files for the FPGA example can be found in the \src subdirectory. The sources in the
\io5v\common directory are also required. There is a project for ISE in the ‘ISE’ subdirectory.
3

FPGA example code
You should understand the HUNT ENGINEERING VHDL support for HERON modules before
looking at this section. If you do not then please review example1 again (the getting started example
for FPGA modules).
Example4 also has some options that need to be set in the user_ap4.vhdl file, these are:-
SCLK_G_DOMAIN INTERNAL_SCLK_G DIFF_RANGE_A DIFF_RANGE_B
True True False False
For the D/A the correct options are:-
INTERNAL_SCLK_DAC DAC_PLL DAC_FREQ
True False 160
The timing constraints for Example 4 are defined in the user constraints file (.ucf) of the design. The
timing specification for the D/A clock "da_data_clk" is set at the D/A maximum clock frequency of 160
MHz. The timing specification for the A/D converters data output clocks "dco_a_n" and "dco_b_n" are
set at 105MHz, which corresponds to the maximum A/D sample frequency of 210MSPS. The Example 4
project builds successfully with this timing constraint, even though the sample A/D sample frequency
used is only 160MHz, and so shows that the A/D section of the project could be clocked up to the full
rate of 210MHz
If you add new clock nets into your design then you need to add new timing constraints.