Integration of epitaxial SiGe(C) layers in advanced CMOS devices ...

Integration of epitaxial SiGe(C) layers
in advanced CMOS devices
Doctoral thesis presentation in
solid state electronics
by:
Julius Hållstedt
1 1

Outline
• Introduction to MOSFET devices
• SiGe(C) as mobility booster
• Epitaxial growth of SiGe(C)
• Temperature stabilty and silicide issues with
SiGe(C)
• Integration of SiGeC layers in pMOSFETs
• Integration of sSi and relaxed SiGe in
nMOSFETs
2 2

Introduction to MOSFET devices
Cleanroom
• Transistors key element in
most electronic circuits
e.g. microprocessors, memories,
communication components,
mobile phones, cars, medical
equipments
Waferlevel
Die (Playstation 3)
Processor (Pentium)
3 3

Downscaling of MOSFETs
IC invented
8086 486
Pentium D
No. of transisors on chip
1.E+09
10 9 10 -1
10 6
1.E+06
10 3
1.E+03
1.E-01
10 -4
1.E-04
Cost per transitor (US $)
1
1.E+00
1950 1960 1970 1980 1990 2000 2010
Year
10 -7
1.E-07
4 4

MOSFET operation
Digital applications: MOSFET used as a switch
G
OFF
V S
S
p+
G
V G
Metal/heavily
doped Si
Gate Oxide
D
t ox
L G
(gate length)
-0.5 0 0.5 1 1.5 2
Si n-type p+
V D
Drain current (A)
10 -4
10 -6
10 -7
10 -8
10 -9
10 -10
10 -11
S
G
S
Subthreshold
SS -1
Linear region
I D
D
ON
D
10 -5 0
20
15
10
5
Drain current (µA)
10 -12
-0.5 0 0.5 1 1.5 2
V T
Gate Voltage(V)
5 5

Introduction to MOSFET devices
Concepts for improved MOSFET performance
• Enhanced mobility
• High-k gate-dielectric
• Metal gate
• Ultra thin body SOI
• Multiple gate e.g. Finfets
Induce strain by
using SiGe and
SiGeC
6 6

Mobility boosters
Substrate-based
Process-based
Biaxial
Strain
Crystal
orientation
Liners
S/D
STI
SACVD
Embedded
SiGe
Bulk SOI
In plane
device
rotation
Crystallographic
rotation
CESL
Tensile/
compressive
SMT
Tensile
SiGe
compressive
SiC
Tensile
Tensile
biaxial
Tensile
Relaxed
SiGe
Tensile/
compressive
Strained
SiGe
SGOI
compressive
sSOI
Tensile/
compressive
Tensile
Natural mobility boost
HOT
nMOS
and
pMOS
Normally uniaxial strain
7 7

SiGe or SiGeC in MOSFETs
Ni silicide
pMOSFETs
n +
Si
Si cap
Strained SiGeC
Si
Ni silicide
nMOSFETs
Buried Oxide
Ni silicide
SiGe
Si substrate
p +
Si
Strained
Si
SiGe
n +
Si
sSi
Relaxed SiGe
Si substrate
Si substrate
8 8

Outline
• Introduction to MOSFET devices
• SiGe(C) as a material system
• Epitaxial growth of SiGe(C)
• Temperature stabilty and silicide issues with
SiGe(C)
• Integration of SiGeC layers in pMOSFETs
• Integration of sSi and relaxed SiGe in
nMOSFETs
9 9

SiGe(C) as mobility booster
Strain induces splitting of the degenerated bandstructure in Si
Compressively strained Si:
Energy
∆2
Valence band splitting and inversion
of the hh and lh band
Conduction band splitting with ∆4
valleys defining the band edge
E g
Si
∆6
lh+hh
∆4
hh
lh
lh
hh
E g
SiGe
Type II
Tensile strained Si (or SiC):
Energy
Conduction band splitting with ∆2
valleys defining the band edge
Valence band splitting with lh and hh
band
E g
Si
∆6
lh+hh
∆4
∆2
lh
hh
E g
SiC
Type I
1010

SiGe(C) as mobility booster
• The difference in atomic radius
induce strain in the epitaxial layers
Si/Si 1-x Ge x
a sub. a layer
Si/SiGe
Compressive strain
Si/Si:C
Tenslie strain
Si/SiGeC Strain compensation
Biaxial compressive strain
Biaxial tensile strain
Unstrained
epitaxial layer
Si
Ge
C
1 11

Outline
• Introduction to MOSFET devices
• SiGe(C) as a material system
• Epitaxial growth of SiGe(C)
• Temperature stabilty and silicide issues with
SiGe(C)
• Integration of SiGeC layers in pMOSFETs
• Integration of sSi and relaxed SiGe in
nMOSFETs
1212

CVD reactor
ASM Epsilon 2000
Industrially used cold wall single wafer system
1313

CVD reactor
1
Growth temperature: 550-1050°C
Pressure: 15-760 torr
Vapors move to wafer and
chemical reaction begins.
By-products,to gas
exhaust treatment
2 Adsorption 5
Desorption of
by-products
Deposition, surface processes
4
SiH 4
, SiH 2
Cl 2
Silicon sources
GeH 4
Germanium source
SiH 3
CH 3
Carbon source
B 2
H 6
, AsH 3
, PH 3
Dopant sources
HCl Etchant
H 2
Carrier gas
N 2
Purge gas
Film
Substrate
3
1414

Chemical reactions
• Silane-based
• SiH4(g) + _ ⇔ H2 + SiH2 ⇔ Si(film)+ _ + 2H2
• (GeH4 has analogue reactions)
• Dichlorsilane-based epitaxy
• SiH2Cl2(g) + _ ⇔ Si(film) + 2HCl(g) + _
•
• SiH2Cl2(g) ⇔ SiCl2 +H2(g)
• SiCl2 + 3_ ⇔ Si(film) +2Cl + _
• Carbon incorporation:
• Silane-based:
• SiH2 + SiH3CH3(g) ⇔ SiH4(g) + SiCH4
• Dichlorsilane-based:
• SiCl2 + SiH3CH3(g) ⇔ SiH2Cl2(g) + SiCH4
_ denotes a lattice incorporation site
1515

Growth optimisation
HRRLMs have been used to optimize the growth
parameters of SiGeC layers.
Si 0.78 Ge 0.21 C 0.01
Si 0.73 Ge 0.26 C 0.01
[100]
a) b) c)
Si sub.
k ⊥
SiGeC layer
∆k ⊥=0.02 Å -1
Si 0.82 Ge 0.17 C 0.01
ω
Enable strain, defect and quality optimization
∆k // =0.02 Å -1
ω/2θ
k //
[110]
1616

As a result of all optimization of
the growth parameters a 3-D
process window is obtained.
The volume above the grey
surface represents high quality
layers
The limitations of the MFCs
are defining the box.
T=625°C up to 0.8% C
T=575°C up to 1.1% C
T=625° C P=20 torr
Used for in-house HF
HBTs (~80GHz)
Used for SiGe MOSFET
Paper 6-7
Using chlorinated chemistry results in much higher C
concentrations (up to 2%) due to the etching of Si.
1717

By applying the optimum growth
parameters:
P-doped Si and Si:C layers (10 18
cm -3 ) were investigated by
temperature dependent Hall
measurements
Si ref. mobility values are in good
agreement with previous results at
this doping level
Mobility [cm 2 /Vs]
300
250
200
150
100
Si ref.
0.2% C
0.5% C
50
Mobility values decreases with
increasing carbon concentration.
Scattering due to the generated
defects (mainly interstitial carbon).
0
50 150 250 350
Temperature [K]
1818

Selective growth of boron doped
SiGe
• SiGe Source/Drain
• SiGe channel
• HBT applications
• Future devices, opto etc...
• Selective growth on patterned wafers
– All influenced by pattern dependency or
loading effect
1919

Pattern dependency
(A)
[µm]
(B)
Test Pattern
160
80
1
40
2
Si
20
4
10
8
Isolated Chips
Si
Si
Si
Opening sizes from 1
1-160 160 µm 2
Si coverages from
0.01-37 %
Si
2020

Pattern dependency
21
80
Large growth rate
and Ge amount
variation when
changing amount of
open Si (Si coverage)
Ge [%]
20
19
18
17
16
15
70
60
50
40
30
Growth rate [Å/min]
14
0.10 1.00 10.00 100.00
Si Coverage [%]
20
2121

Origin of pattern dependency
Laminar
gas flow
δ (x)=A(µx/U) 1/2
Stationary (low velocity)
boundary layer
Wafer
2 22

Origin of pattern dependency
Diffusion of growth species
throug stationary layer
towards opening
boundary layer
Creates gas
depletion
around opening
Oxide Mask
Wafer
2323

Range of gas depletion
Gas flow
Growth rate [µm/min]
[Å/min]
200
150
100
50
0
Angle in degrees from
gas flow direction
0
0
90
90
270
-90
360
180
SES
SEE
SE
W
SEN
0 5000 10000 15000 20000
Distance from big opening [µm]
Distance from big opening [µm]
90
180
-90
0
Growth without rotation
Similar growth behavior in all
directions
Big opening depletes gas in a
radius of 1-1.5 cm
The small openings close to
the big opening display
simialr growth behavior
2424

Effect of surface migration
species
Make poly Si stripes around
the openings
By putting these closer to
the opening less adsorbed
specis can diffuse to the
opening
Growth or pile up around
the edge should decrease?!
2525

Effect of surface migration
species
Growth rate [Å/min]
150
100
50
a)
P Ge [mtorr]
1.0
0.7
0.5
Result – opposite:
Again the reason
for the decrease is
the increased area
of exposed Si when
the poly stripes are
longer.
0
0 10 20 30
Distance [µm]
2626

Effect of surface migration
species
90
0.5 µm
45
0
90
1 2 3 [µm]
No difference in pile up
for the different poly
stripe distances
Stepheight [nm]
45
0
90
10 µm
1 2 3
[µm]
45
30 µm
0
1 2 3 [µm]
Scan direction
2727

Methods to reduce gas depletion
effects
• Growth parameters:
– Decreased pressure: faster diffusion
– Increased gas flow: thinner boundary layer
– Increased HCl partial pressure
• Wafer pattern:
– Uniform repetitive pattern with similar
structures
– Inser dummy features to compensate for
in-uniform gas consumption
2828

Outline
• Introduction to MOSFET devices
• SiGe(C) as a material system
• Epitaxial growth of SiGe(C)
• Temperature stabilty and silicide issues
with SiGe(C)
• Integration of SiGeC layers in pMOSFETs
• Integration of sSi and relaxed SiGe in
nMOSFETs
2929

3030

Outline
• Introduction to MOSFET devices
• SiGe(C) as a material system
• Epitaxial growth of SiGe(C)
• Temperature stabilty and silicide issues with
SiGe(C)
• Integration of SiGeC layers in pMOSFETs
• Integration of sSi and relaxed SiGe in
nMOSFETs
3131

SiGe(C) channel pMOSFETs on
UTB SOI
NiSi
Lg=100 nm – 200µm
Poly-Si
SiGe
Si
SiO 2
80 nm

Long channel electrical
characteristics
0.06
1.00E-01
10 -1
Drain current (µA/µm)
0.05
0.04
0.03
0.02
0.01
SIMOX Substrates
0
10 1.00E-08
-2.5 -1.5 -0.5 0.5 1.5 2.5
Gate voltage (V)
Si
SiGeC
SiGe
1.00E-02
10 -2
Drain current (µA/µm)
1.00E-03
10 -3
10 -4
1.00E-04
1.00E-05
10 -5
1.00E-06
10 -6
1.00E-07
10 -7
3 33

Mobility Si, SiGe and SiGeC
channels
Effective electric field (MV/cm)
200
175
0 0.1 0.2 0.3 0.4 0.5
Si universal
Mobility (cm 2 /Vs)
150
125
100
75
50
SiGe
SiGeC
Si
25
0
SIMOX Substrates
0 2 4 6 8 10
x10 12
Inversion charge density (cm -2 )
3434

Bulk vs UTB SOI
160
SiGe
140
FD SOI
Mobility [cm 2 /Vs]
120
100
80
60
40
Bulk
Si
SiGe
Si
20
0
0 2 4 6 8 10 12
Inversion charge density [cm -2 ]
10 12
3535

Outline
• Introduction to MOSFET devices
• SiGe(C) as a material system
• Epitaxial growth of SiGe(C)
• Temperature stabilty and silicide issues with
SiGe(C)
• Integration of SiGeC layers in pMOSFETs
• Integration of sSi and relaxed SiGe in
nMOSFETs
3636

Introduction
• Bandgap narrowing
• Implantation damage difficult to aneal
Misfit dislocations:
-Source to drain leakage
• Threading dislocations:
-Substrate leakage
• VS-Increased self heating -not considered in
this study
3737

Experimental - Devices
• Thin and supercritical
sSi
S
D
NiSi
sSi
• Supercritical sSi ~1 Gpa
SiGe VS
• Thin sSi up to 3.2 GPa
Si substrate
• Wells and retrograde
n+ poly Si
channel doping:
G
-in situ
-implantation
S
D
sSi
• Channel peak doping
conc:
Si 0.7 Ge sSi
0.3
80 nm
-310 18 cm -3
SiGe VS
-710 18 cm -3
G
Si substrate
3838

Experimental - Stress Measurement
[100]
a) b)
sSi Stress sSi and mismatch measurement
of substrates after device processing
Si
sub.
Si
sub.
HRXRD
•Highly relaxed SiGe VS (90-100%)
∆k - =0.02Å-1
Relaxed SiGe
(thick graded) ω
∆k // =0.02Å -1
•Highly strained Si (

Mobility Enhancement (Long Channels)
Electron mobility (cm 2 /Vs)
400
300
200
100
Si ref.
1.8 Gpa
0
0.5 1 1.5 2 2.5
Effective field (MV/cm)
1.3 Gpa
1.0 Gpa
Mobility enhancement
2.2
2
1.8
1.6
1.4
1.2
1
This study
Rim Literature et al. [1] values
0 0.5 1 1.5 2
Stress [GPa]
4040

Device Performance (L G =80 nm)
Drain Current (A/µm)
450
2
10 -2 V DS 0.1 V
10 -4
1.0V
400
1.8 GPa
10 -6
350 1.3 GPa
10 -8
Si ref.
1.0 GPa
10 -10
300
10 -12
SS~80mV/Dec.
250
10 -14
Gate Voltage Stress [GPa]
(V)
Transconductance [µS/µm]
V D =1 V
0 0.5 1 1.5 2
1.8
1.6
1.4
1.2
1
-0.5 0 0.5 1 1.5 2 2.5
Transconductance enhancment
4141

Substrate Junction Leakage
Comparison between in-situ and implanted devices:
1x10 -3
Current (A)
I off
in-situ
1x10 -5
1x10 -7
1x10 -9
I off implanted
I D
I Sub
10 -11
-0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage (V)
4242

Substrate Junction Leakage
Comparison between in-situ and implanted devices:
10 -9 Wafer
Drain-substrate current (A/ µm)
10 -10
10 -11
10 -12
10 -13
Implanted
1.3 GPa
Si Ref.
Implanted
and in-situ
In-situ
1.3 Gpa
4343

Substrate Junction Leakage
Effect of increasing the Ge amount in the substrate:
Drain-substrate Current (A/µm
Drain-substrate current (A/µm)
10 -5 Drain-Substrate diodes
Increasing
10 -10
Ge %
1.8
1.3 GPa 2.2
3.2
GPa
1.0
GPa
GPa
Si ref. GPa
10-1.5 -15
-1 -0.5
Wafer
0 0.5 1 1.5
10 -5
10 -10
10 -15
Drain-substrate Voltage (V)
4 44

Substrate Junction Leakage
Effect of increasing the Ge amount in the substrate:
1000000
6
100000
5
Thin VS TDD ~ 1*10 9 cm -2 [5]
Thin VS TDD ~ 1*10 7 cm -2 [5]
[5] Eneman et al.
APL 2005
10 6 Leakage from
Leakage Factor
10000
4
1000
3
100
2
10
1
Comercial graded
TDD ~3*10 5 cm -2 [5]
Implanted
0 0.5 1 1.5 2 2.5 3 3.5
Si Stress [Gpa]
In-situ
bandgap narrowing
4545

Source to Drain Leakage L G =80 nm
Current (A/µm)
10 -4 10 -6
I S, I D
10 -8
10 -10
I D
10 -12
I S
10 -14
Gate Voltage (V)
Attributed to enhanced As
diffusion through misfit
dislocations between source and
drain
-0.5 0 0.5 1 1.5 2 2.5
Only visible at short gate lengths
4646

Source to Drain Leakage L G =80 nm
Counts
14
12
10
8
6
4
2
Doping 3 x 10 18 cm -3
Doping 7 x 10 18 cm -3
0
-16 -14 -12 -10 -8 -6 -4 -2
Log Source Current @ V GS
= -0.5 V
• Leakage effectively
reduced for
increased channel
doping
• Manifest theory of
enhanced As
diffusion along
misfit dislocations
4747

Source to Drain Leakage L G =80 nm
Channel Direction
S
D
Misfit dislocations
causing enhanced
As diffusion
G
Rotation of Devices!
4848

Source to Drain Leakage L G =80 nm
Direction
Diffusion distance
along dislocation
~1.4 times longer.
S
Can we see this in the
80 nm devices?
D
Misfit dislocations
G
4949

Source to Drain Leakage L G =80 nm
Counts
8
6
4
0 degrees
50 degrees
• Channel rotation
can be used to
reduce S/D leakage.
2
0
-12 -10 -8 -6 -4
Log Source Current @ V GS
= -0.5 V
5050

Conclusions
• 1.8X sSi mobility enhancement.
• sSi nMOSFETs 1.5X performance enhancement
at 80 nm gate length.
• Substrate leakage current was reduced by
in-situ doped substrates.
• Increased channel doping masked the enhanced
As diffusion along the misfit dislocation
lines which reduced S/D leakage.
• Rotation of the channel orientation was also
shown to reduce the source to drain leakage at
L G =80 nm.
5151

Aknowlegdements
Jun Luo, Valur Guðmundsson Yong-Bin Wang and Christian Ridder
are gratefully acknowledged for assistance in device processing.
Jun Lu at Ångström Laboratory is accredited for providing the TEM
image.
The Ion Technology Center (ITC) at Uppsala University is
acknowledged for ion implantation.
This work was in part financially supported by Swedish Foundation
for Strategic Research (SSF) through the NEMO program and EU
through the “SiNANO Network of Excellence”.
5252