IEEE Paper Template in A4 (V1) - ijmer

International Journal of Modern Engineering Research (IJMER)
www.ijmer.com Vol.2, Issue.1, pp-01-03 ISSN: 2249-6645
TABLE I
TRANSISTOR SIZE
Device W/L(μm)
M1,M2,M3 40/0.6
M4,M5 20/0.6
M6,M7,M8,M9 42/0.6
M8,M9 50/0.6
M10,M11 60/0.6
M12,M13 0.8/0.6
3. SIMULATION RESULTS
The design of this Operational Transconductance Amplifier
(OTA) is done using Cadence Tool. The Simulation results are
done using Cadence Spectre environment using UMC 0.18 μm
CMOS technology. The simulation result of the OTA shows
that the open loop gain of approximately 71 dB. The OTA has
GBW of about 37 KHz.
The Table II shows that the simulated results of the OTA. The
AC response which shows gain and phase change with
frequency is shown in figure 2. Figure 3 shows the DC sweep
response of This OTA. The Transient response with input in
pulse is shown in figure 4. Figure 5 illustrates PSRR variations
with frequency. The variation in CMRR is shown in figure 6.
The simulated results of this OTA shows that PSRR of 85
dB and CMRR of 90 dB.
Figure 2: Shows AC response which shows gain and phase
change with frequency.
TABLE II
SIMULATED CHARACTERSTICS OF OTA
Specifications Simulated
CMOS
technology
Open loop gain
0.18μm
71 dB
Figure 3: DC sweep response.
Supply voltage
Bias
Voltage
PSRR
CMRR
1.8 V
1.8V
85 dB
90 dB
Figure 4: Transient response with input is pulse.
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