Towards a Power and Energy Efficient Use of Partial Dynamic ...

Towards a Power and Energy Efficient Use of
Partial Dynamic Reconfiguration
Robin Bonamy
CAIRN-IRISA
Université de Rennes1
Lannion
robin.bonamy@irisa.fr
Daniel Chillet
CAIRN-IRISA
Université de Rennes1
Lannion
daniel.chillet@irisa.fr
Olivier Sentieys
CAIRN-IRISA
Université de Rennes1
Lannion
olivier.sentieys@irisa.fr
Sébastien Bilavarn
LEAT
Université de
Nice Sophia Antipolis
sebastien.bilavarn@unice.fr
Abstract—Nowadays, System-on-Chip architectures are composed
of several execution resources which support complex
applications. These applications increasingly need flexibility to
adapt to their environment. Embed a reconfigurable resource
in these SoC enables to flexibilize the hardware by sharing
silicon area and limiting the cost of the global circuit. Partial
reconfiguration is more and more used since it enables to fully
exploit the resource but there is few work in the characterization
of the energy consumption during reconfiguration. This paper
presents the work on modelling energy during dynamic, partial
reconfiguration and the future use of models.
I. INTRODUCTION
Run-time reconfiguration, the ability to change a configuration
while the rest of the circuit is running, is a research
subject since the 90s [1] and is now commonly used in FPGAs,
configurable circuits, since Xilinx and Altera [2] now provide
such circuits. The main advantages of the partial, run-time
reconfiguration are to add flexibility and to reuse hardware
area, allowing power and production costs reductions. During
last decade, much work has been done on tools to exploit
the reconfigurable aspects of these configurable circuits [3][4]
and [5]. However, there is few work in the characterization
and estimation of the power and energy consumption during
reconfiguration. Configurable areas become a usual extension
of Systems-On-Chip which are increasingly used in integrated
and embedded systems where the energy consideration is
substantial. In the scope of the Open-PEOPLE project [6],
which aim is to provide a complete heterogeneous hardware
and software platform for power and energy estimation, optimization
and measurement, we build models of the energy
consumption of reconfigurable devices. Our work focuses on
the energy required during partial reconfiguration. This paper
first introduces the partial reconfiguration procedure. Then, in
Section III, an energy cost model of dynamic application implemented
with partial run-time reconfiguration is presented.
Section IV presents the method to extract energy models.
Finally, we conclude this article and present future work.
II. PARTIAL RECONFIGURATION CONCEPT
Nowadays, most of configurable devices store their configuration
in RAM. This architecture allows the modification of the
configuration as many times as the designer needs. Moreover,
it is now possible to dynamically change the configuration of
a part of the device. Configuration memory can be accessible
from a port inside the configurable device allowing the
designer to perform self reconfiguration. For Xilinx FPGAs,
this port is the Internal Reconfiguration Access Port (ICAP)
[7][8].
Reconfigurable devices are divided into blocks, called
frames, the smallest configuration area addressable. FPGAs
can be divided in coarse and fine grain Partial Reconfiguration
Regions (PRR) to suit application.
The configurable area of the FPGA is supposed composed
of N P Partial Reconfigurable Regions (PRR), and this composition
is static. Then, the FPGA is modeled as a set of PRRs
and defined by
FPGA = {P RR j } ∀ j = 1, . . . , N P . (1)
Reconfiguration is done using a file containing configuration
data needed for each P RR j , called the bitstream. Loading
this configuration has a time and energy cost. From our
experiments, we observe that the energy for the reconfiguration
phase mainly depends of the size of the bitstream file which
has an impact on the configuration time depending of the
bitstream file size.
Dynamic Reconfiguration enables to change on-the-fly tasks
configured in a given PRR. Moreover, Section IV shows that
it is possible to reconfigure a low power task when the region
is not used to minimize the global power consumption. This
specific task for the P RR j is called T lp j for low power task.
III. PARTIAL RECONFIGURATION POWER MODELLING
A definition of an application is based on its task graph G
which indicates the execution order of the tasks. This graph
contains a set of N T tasks and is defined by
G = {T i } ∀ i = 1, . . . , N T , (2)
with T i the i th task of the application.
Dynamic reconfiguration of an application requires a managing
system. This management of the application on the
hardware execution resource is supposed to be supported by an
operating system (OS). The goal of the OS is to evaluate the
task scheduling at each OS logical time, called T ick occurring
every T T ick , and to propose a set of ready tasks for each T ick.
The scheduling algorithm is out of the scope of this paper but

we consider that the scheduler produces a valid list of ready
tasks for each T ick.
The execution time of each task T i depends on its instantiation,
and is defined by the variable C i,j (t) for task
T i instantiated in P RR j . This variable is decreased by the
scheduler at each cycle if the task T i is included in the set
of read tasks at the current T ick. The power consumption of
each task T i is also dependent from its instantiation, and is
defined by the variable P i,j for task T i instantiated in P RR j .
The time and the power to configure a specific task T i
depend on the bitstream size of this task which depends on
the PRR size selected for the task. These time and power for
uploading the bitstream in the configuration memory are given
by the variables T u prrj and P u prrj for the P RR j .
From these definitions, we propose to model the optimization
problem through the minimization of an energy expression
of the global system. The goal of the optimization is to
compute the task configurations which limit the power consumption
of the system at each T ick. These task instantiations
are defined though the variable X i,j (t) which is equal to 1 if
the task T i is instantiated on P RR j at time T ick = t, or equal
to 0 otherwise. Due to the OS behavior, i.e. new schedule
computed at each T ick, the optimization problem must be
solved at each T ick. At each T ick, the OS knows which tasks
are configured on which P RR. So the OS knows the values
of variable X i,j (t − 1), and then the power consumption is
known before the new scheduling. This power consumption
related to this T ick are the power consumed by task already
implemented, P T A (t, j), by low power tasks, P T lp (t, j), by
reconfiguration of new tasks, P P R (t, j) and the power consumed
by newly implemented tasks, once reconfiguration is
finished, P NT (t, j) for each P RR j . These power profiles are
defined in the following equations:
∑N T
P T A (t, j) = (1 − (X i,j (t) − (X i,j (t − 1))) × P i,j
i=1
N T
∑
P T lp (t, j) = (1 − X i,j (t)) × P T lp,j
i=1
N T
∑
P P R (t, j) = | (1 − (X i,j (t) − X i,j (t − 1))) | × P u prrj
i=1
N T
∑
P NT (t, j) = (1 − (X i,j (t) − (X i,j (t − 1))) × P i,j (3)
i=1
With these expressions of the power consumption, the
energy consumption during one T ick is given by:
E T ick (t) =
∑N P
j=1
P T A (t, j) × T T ick
+ P T lp (t, j) × T T ick
+ P P R (t, j) × T uprrj
+ P NT (t, j) × (T T ick − T uprrj ). (4)
From this expression, the optimization problem must compute
the X i,j values for the new T ick according to G and
C i,j (t). These new values lead to reduce the energy which
will be consumed between the current T ick (t) and the next
T ick (t + 1).
IV. POWER MEASURES
In order to build power consumption models and to validate
the previously presented approach, real measures of the energy
of dynamic reconfiguration are needed. We implemented an
application similar to the one proposed in [9] in a Virtex-
5. Figure 1 presents the power consumption obtained while
reconfiguring a P RR j for a T i to T lp j . This figure shows
that there is an important reduction of the power consumption,
in this case, power is reduced by 25 mW . This confirms the
advantage to use Partial Reconfiguration (PR) and low power
tasks to reduce global energy consumption.
Fig. 1. Power consumption of a Virtex-5 during the reconfiguration of a
PRR from a Task to a low power task versus time.
V. CONCLUSION
This paper has presented our work on power and energy
characterization of partial reconfiguration. The measures realized
confirm the potential of reconfiguration to reduce energy
consumption and the lack of tools to estimate and optimize the
use of this feature. Our future work will focus on continuing
building energy consumption models on other platforms with
different reconfiguration flows and energy optimization with
these models and a validation on a real application.
ACKNOWLEDGMENT
The authors would like to thank the French National Agency
for the support of this work in the scope of the OpenPEOPLE
project.
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