Getting Started with QNX Neutrino - QNX Software Systems

© 2009, QNX Software Systems GmbH & Co. KG. Neutrino and interrupts
Time
Hardware interrupt
request line
1
4
1
2
2
ISR x
3
3
Process
Edge-sensitive interrupt assertion.
Even if the ISR fails to clear the source of the interrupt, when the kernel sends the EOI
to the PIC (step 2 in the diagram), the PIC wouldn’t re-interrupt the kernel, because
there isn’t another active-going edge transition after the EOI. In order to recognize
another interrupt on that line, the line must first go inactive (step 4), and then active
(step 1).
Well, it seems all our problems have been solved! Simply use edge-sensitive for all
interrupts.
Unfortunately, edge-sensitive mode has a problem of its own.
Suppose your ISR fails to clear the cause of the interrupt. The hardware would still
have the interrupt line asserted when the kernel issues the EOI to the PIC. However,
because the PIC is operating in edge-sensitive mode, it never sees another interrupt
from that device.
Now what kind of bozo would write an ISR that forgot to clear the source of the
interrupt? Unfortunately it isn’t that cut-and-dried. Consider a case where two devices
(let’s say a SCSI bus adapter and an Ethernet card) are sharing the same interrupt line,
on a hardware bus architecture that allows that. (Now you’re asking, “Who’d set up a
machine like that?!?” Well, it happens, especially if the number of interrupt sources on
the PIC is in short supply!) In this case, the two ISR routines would be attached to the
same interrupt vector (this is legal, by the way), and the kernel would call them in turn
whenever it got an interrupt from the PIC for that hardware interrupt level.
April 30, 2009 Chapter 4 • Interrupts 173