Getting Started with QNX Neutrino - QNX Software Systems

© 2009, QNX Software Systems GmbH & Co. KG. Writing interrupt handlers
}
sizeof (event),
0);
if (interruptID == -1) {
fprintf (stderr, "%s: can’t attach to IRQ %d\n",
progname, HW_SERIAL_IRQ);
perror (NULL);
exit (EXIT_FAILURE);
}
...
return (EXIT_SUCCESS);
Detaching an interrupt handler
This creates the association between the ISR (the routine called intHandler(); see
below for details) and the hardware interrupt vector HW_SERIAL_IRQ.
At this point, if an interrupt occurs on that interrupt vector, our ISR will be dispatched.
When we call InterruptAttach(), the kernel unmasks the interrupt source at the PIC
level (unless it’s already unmasked, which would be the case if multiple ISRs were
sharing the same interrupt).
When done with the ISR, we may wish to break the association between the ISR and
the interrupt vector:
int
InterruptDetach (int id);
I said “may” because threads that handle interrupts are generally found in servers, and
servers generally hang around forever. It’s therefore conceivable that a
well-constructed server wouldn’t ever issue the InterruptDetach() function call. Also,
the OS will remove any interrupt handlers that a thread or process may have associated
with it when the thread or process dies. So, simply falling off the end of main(),
calling exit(), or exiting due to a SIGSEGV, will dissociate your ISR from the interrupt
vector, automagically. (Of course, you’ll probably want to handle this a little better,
and stop your device from generating interrupts. If another device is sharing the
interrupt, then there are no two ways about it — you must clean up, otherwise you
won’t get any more interrupts if running edge-sensitive mode, or you’ll get a constant
flood of ISR dispatches if running in level-sensitive mode.)
Continuing the above example, if we want to detach, we’d use the following code:
void
terminateInterrupts (void)
{
InterruptDetach (interruptID);
}
If this was the last ISR associated with that interrupt vector, the kernel would
automatically mask the interrupt source at the PIC level so that it doesn’t generate
interrupts.
April 30, 2009 Chapter 4 • Interrupts 177