Compact SiPM based Detector Module for Time-of-Flight PET/MR

Compact SiPM based Detector Module for
Time-of-Flight PET/MR
M. Ritzert 1 , V. Mlotok 1 , I. Perić 1 , P. Fischer 1 ,
C. Piemonte 2 , N. Zorzi 2 , T. Solf 3 , V. Schulz 3 , A. Thon 3
1 Institute for Computer Engineering
Heidelberg University, Mannheim, Germany
2 Fondazione Bruno Kessler
Trento, Italy
3 Philips Research Europe
Aachen, Germany
Realtime Conference, Beijing, 2009
RTC, 2009 1

Project Overview
I Project funded by the European Union in FP7.
I Develop a compact PET detector module for use in a
simultaneous ToF PET/MR detector, scalable to a
whole-body scanner.
I Develop novel reconstruction algorithms to make
good use of the available information (MR based
attenuation and motion correction).
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Requirements for the PET Detector
I MR compatible design, i.e. no magnetic components,
especially no PMTs, inside the magnet, no wire loops.
I Fit inside the little available space inside the MR
scanner.
1. Develop a compact detector module.
2. Require few wire and other connections through the
MR scanner.
I No relevant performance degredation by MR
gradients and HF signals from MR operation.
I Sub-nanosecond timing for ToF PET.
I Several thousand channels even in a “small” animal
scanner.
I Rugged design to withstand the vibrations inside an
MR scanner.
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State of the Art in Simultaneous PET/MR
I Use a light guide to guide the scintillation light to PMT
detectors outside the magnet.
Drawback: Lots of optical fibres, bad light yield.
I APD detectors with first
amplification stage inside
the field, all other
processing outside the B
field.
Drawback: Lots of
connections required,
potential of large noise
pickup on long wires.
→ Not scalable.
M. Judenhofer et al., “Simultaneous PET-MRI:
a new approach for functional and morphological
imaging,” Nature Medicine 14, 459 - 465
(2008)
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Our Approach
Put everything inside the tube:
I Light detection
I Amplification
I Digitization
I Timestamping
I Serialization
→ Only few data connections for a large number of
channels.
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Methods
I Highly integrated
electronics.
I Very compact module
design.
I Large area SiPM
detectors.
I Aggressive mechanics
and cooling.
I Differential architecture
for EMI robustness. Actual size: 33×33 mm².
I Modular concept with
defined interfaces on the
connectors.
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Block Diagram
Power
3 rd PCB 2 nd PCB 1 st PCB
LDO
to DAQ
FPGA
Readout
Readout
ASIC
ASIC
Impedance
Matching
DACs
digital
analog
to HV
suply
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Top PCB: Detectors
I 64 channels.
I 4×4 mm² SiPMs.
I 4×4 monolithic arrays of 2×2 silicon
photomultipliers.
→ Entire surface covered by SiPMs
→ High packing fraction.
I Passive components required to
interface to the ASICs located on
the bottom side of the PCB.
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Middle PCB: Hit Digitizing
I Two readout ASICs, each handling
32 SiPM channels.
I Self-triggering by leading-edge
discriminator.
I 100 ps FWHM coincidence timing
resolution.
I 20 bit timestamps.
I 9 bit ADC for energy readout.
I Digitization of absolute arrival time
and signal energy.
I All-digitial, differential output to the
FPGA.
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Bottom PCB: Control, Processing
I Xilinx Spartan FPGA for
I Control of the ASICs.
I Hit data preprocessing.
I Interfacing between the ASICs and
the system.
I DACs to generate bias voltages for
the ASICs and SiPM devices.
I Interface to DAQ: Several LVDS
connections.
I Local analog power regulation.
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Test Setup
I Testboard
containing a single
PCB stack and
interface to USB.
I Light-tight box for
measurements
with SiPMs.
I Detector board replaced with dummy board
connecting pulse inputs to SMA connectors for ASIC
characterization.
I Linux-based data acquisition and data analysis.
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Results – Setup Verification
Counts
25 k
20 k
15 k
10 k
5 k
Measurement
19.7% FWHM
0
0 400 800 1200
Energy [keV]
22 Na spectrum measured with a single LYSO crystal
standing on one SiPM. Bad optical coupling! → Bad
resolution.
But: Proves that the entire stack works as expected!
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Results – Discriminator Threshold
100
Triggers Seen [%]
80
60
40
20
0
Measurement
3.0 m ± 626 µV
2 2.5 3 3.5 4 4.5
Trigger Voltage [mV]
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Results – Threshold Dispersion I
Discriminator Schematics
Threshold
Setting
differential
pair input
Pulse Input
Expected Behavior
Disabled
several σ noise
Trigger
Out
Trigger Rate
0
bar range
in next plot
Threshold Setting
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Results – Threshold Dispersion II
60 m
Threshold Setting [V]
40 m
20 m
0
-20 m
-40 m
0 10 20 30 40 50 60 70
Channel
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Results – Threshold Dispersion III
I Bar offset: Switching offset of a differential pair of
NMOS transistors in close proximity.
I Effects: Large threshold dispersion between
channels, limit on lowest possible threshold.
I Compensation circuit implemented in next generation
ASIC.
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Future System Integration
I Motherboard PCB with
six (3×2) stacks with
minimal spacing.
I Large FPGA to process
the data and send it off
via Gigabit Ethernet.
I Box to firmly hold the
components and provide
the infrastructure for
cooling.
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Outlook
I Improved ASIC
I Decreased discriminator threshold dispersion.
I Lower power consumption.
I Should be back from fabrication just today.
I Operation with full crystal array.
I Measure performance in MR.
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Acknowledgements
This project is supported by the European Union under the
7 th framework program (Grant Agreement #201651).
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