COMNET III CACI

Shared memory switches are characterized by a central memory in which the cells are
buffered. Typically, the design includes a multiplexor on the input side and a
demultiplexor on the output side. Incoming cells are multiplexed and sent through a
single connection to the shared memory. They are typically buffered by VPI/VCI value.
On the output side of the switch, the demultiplexor takes the cells from the memory and
distributes them to the respective output ports. The basic architecture of a shared memory
switch is shown in Figure 32.
Switch
Mux
Mux
Control
Figure 32: Shared memory switch
Shared bus switches use an internal bus to connect the ports. They are further categorized
into single bus or multiple bus architectures. As the name implies, a single bus
architecture contains only one bus through which the ports are connected. A multiple bus
architecture provides some level of parallelism by connecting the ports through multiple
busses. The speed of the busses is typically in the gigabyte range. In case of a single bus
architecture, a medium access algorithm arbitrates the access of the ports to the bus. For
multiple bus architectures, a separate bus is provided for each port, hence eliminating the
need for an arbitration algorithm. Figure 33 illustrates a single bus architecture.
Bus
Ports
Figure 33: Single bus architecture
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