Base Course - train-z
Base Course - train-z
Base Course - train-z
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Owner: Dipl. Ing. Mario Blunk<br />
Buchfinkenweg 5<br />
99097 Erfurt / Germany<br />
Phone +49 176 2904 5855 / +49 361 5189 618<br />
Email marioblunk@arcor.de<br />
Internet http://www.<strong>train</strong>z.de<br />
Doc. Vers. 6.5
CadSoft EAGLE Training<br />
The slides you will see in the following give an overview of topics<br />
addressed for EAGLE Version 5.x and 6.x. You will get details and<br />
practicing in my course.<br />
Please find more on booking and pricing here:<br />
http://www.<strong>train</strong>z.de/pdf/contents_EAGLE_classes_Mario_Blunk.pdf
Overview<br />
set up your project<br />
draw your schematic<br />
define net classes<br />
ERC<br />
place your devices on the board<br />
DRC settings<br />
routing manually / vias / layer setup<br />
autorouter<br />
device library<br />
CAMProcessor
click right/<br />
New Project<br />
Project Set Up
click right on<br />
project name /<br />
new<br />
schematic<br />
Create Schematic
command ADD<br />
Drawing Frame #1
Symbol placing #1<br />
commands ADD, USE, MOVE, DELETE, GROUP,<br />
NAME, VALUE, CHANGE, SMASH
command INVOKE<br />
Symbol placing #2
Nets #1<br />
commands NET, NAME, LABEL, SPLIT,<br />
JUNCTION, SHOW
Nets #2<br />
commands CHANGE XREF ON, LABEL
command GATESWAP<br />
Gate Swap<br />
before after
Busses<br />
commands BUS, NAME, LABEL, SPLIT
Structure
commands<br />
DISPLAY,<br />
LAYER,<br />
CHANGE LAYER<br />
Schematic Layers
Documentation #1
Documentation #2
Electrical<br />
Engineering<br />
large scale systems<br />
motor control<br />
contactors<br />
contact references<br />
“dummy packages”
Drawing Grid<br />
command<br />
GRID<br />
Alternative<br />
Grid:<br />
CTRL+Alt
Schematic Pages<br />
command<br />
EDIT .s2<br />
rearranging by<br />
EDIT .s2 .s1<br />
Script : scr new_page
Net Classes #1<br />
rules for minimal measures :<br />
track width via drills clearance to other signals<br />
command<br />
CLASS<br />
ULP : exportclass
Net Classes #2<br />
commands<br />
INFO,<br />
CHANGE CLASS<br />
ULP : cmdchangeclass
command TEXT<br />
Text #1
command INFO<br />
Text #2
Text #3<br />
Command TEXT >PROJEKT
Device Naming<br />
command RUN renumbersheet.ulp
Assembly Variants #1<br />
command VARIANT
Assembly Variants #2
ERC<br />
command<br />
ERC<br />
ULP : statisticsch
Printing<br />
command<br />
Scripts #1
1. 2.<br />
Scripts #2
Scripts #3<br />
Execution on EAGLE start up automatically !<br />
run script manually: scr eagle.scr
Scripts #4<br />
More on EAGLEScripting here:<br />
Scripting Tutorial
PCB<br />
Thanks to: Key Design Electronics Ltd. http://www.kdel.co.uk/<br />
26 Lancaster Way, Scalby, Scarborough, YO13 0QH, England<br />
+44 (0) 1723 341809
command<br />
Board<br />
Board
Outlines<br />
commands MOVE, WIRE, SPLIT, DEL, ARC, CIR<br />
$ / €<br />
grid metric / inch ?
Metric vs Imperial<br />
0.1inch<br />
2.54 mm<br />
=<br />
x inch wanted<br />
y mm given<br />
0.1inch=100 mil
Holes #1<br />
commands<br />
ADD,<br />
DELETE,<br />
MOVE
Holes #2<br />
commands<br />
COPY,<br />
DELETE,<br />
MOVE,<br />
LOCK<br />
grid<br />
metric / inch ?<br />
Script scr euro_2
command<br />
ADD<br />
Marks #1
Marks #2<br />
commands MOVE, DELETE, COPY, LOCK<br />
Contact<br />
PCB<br />
house !
Contact<br />
PCB<br />
house !<br />
Marks #3
command MARK<br />
Measurements
Befehl DIM<br />
Dimensions
Placing Devices #1<br />
commands LOCK, MOVE, GROUP, CHANGE,<br />
ROTATE R45, MIRROR, RATSNET
Placing Devices #2<br />
mirrored !<br />
keep out
commands<br />
TEXT,<br />
CHANGE<br />
TEXT<br />
SIZE<br />
RATIO<br />
LAYER<br />
Text #1
Text #2
Text #3
Board Layers<br />
commands<br />
DISPLAY,<br />
LAYER<br />
CHANGE LAYER
commands<br />
WIRE,<br />
POLY,<br />
DELETE,<br />
MOVE,<br />
SPLIT,<br />
GROUP<br />
Restricted Areas #1
Restricted Areas #2<br />
commands<br />
WIRE,<br />
DELETE,<br />
MOVE,<br />
SPLIT,<br />
GROUP
Restricted Areas #3<br />
commands<br />
POLY,<br />
DELETE,<br />
MOVE,<br />
GROUP
Routing #1<br />
commands<br />
ROUTE,<br />
WIRE,<br />
SPLIT,<br />
RIPUP,<br />
RATSNET,<br />
MOVE<br />
VIA,<br />
CHANGE WIDTH / LAYER<br />
Use net name prefixes !
Routing #2<br />
commands<br />
WIRE,<br />
VIA<br />
NAME,<br />
RATSNET,<br />
...
Via Properties<br />
commands INFO, CHANGE SHAPE / DIA / DRILL<br />
ULP : teardrops
Polygons #1
command POLY<br />
Polygons #2
Polygons #3<br />
commands RATSNET, NAME
Polygons #4<br />
commands CHANGE ISO / THERMAL / ORPHAN /<br />
POUR / WIDTH, RIP @ xyz
Polygons #5
name GND<br />
Polygons #6
Track Length<br />
Command MAEANDER 50<br />
Settings for max. difference & gap in : DRC/MISC<br />
ULP: length
Autorouter #1<br />
route all nets:<br />
AUTO (not very reasonable)<br />
route all but:<br />
AUTO ! GND +5V<br />
route only:<br />
AUTO RD_CPU<br />
Restricted by net class settings !<br />
Use net name prefixes !
Autorouter #2
Autorouter #3
Autorouter #4<br />
autoroute_classes.ulp
Rip Up<br />
Rip up all nets:<br />
RIPUP (not very reasonable)<br />
Rip up all nets except:<br />
RIPUP ! GND +5V<br />
Rip up only:<br />
RIPUP CLK_RAM CLK_JTAG<br />
Use net name prefixes !
command<br />
DRC<br />
DRC #1
command<br />
DRC<br />
DRC #2
command<br />
DRC<br />
DRC #3
DRC #4<br />
command<br />
DRC<br />
Via drills greater<br />
than 0,6mm<br />
without<br />
solder stop<br />
lacquer !
DRC #5<br />
Solder Stop<br />
Mask<br />
IMPORTANT<br />
for FinePitch<br />
Packages e.g.<br />
TQFP144 !
DRC #6
DRC #7<br />
change Max & Min to 2 mil<br />
ULP : lengthfreqri
DRC #8<br />
Via in an SMD pad not covered with solder stop lacquer<br />
NOTE: Contact PCB house ! Solder cream may drain into drill !<br />
DRC setting Clearance/Same Signals SMDVia=0 required !
DRC #9<br />
0 > no DRC check !
Solder Stop #1<br />
Via covered<br />
Via not covered<br />
Do not use as test pad for ICT or<br />
FPT !<br />
Contact board assembly house !
Solder Stop #2<br />
Exceptional case:<br />
not covered via
Importing SCH / BRD<br />
new schematic sheets<br />
mind the GRID !<br />
net class number<br />
net name prefixes
Multilayer PCBs<br />
1. Do you really need a multilayer PCB ?<br />
2. Supply and Signal Layers<br />
3. Layer Setup<br />
4. Vias<br />
5. Contact PCB house !
Layer Stack #1<br />
signals<br />
VCC<br />
GND<br />
signals<br />
+ supply buffering<br />
+ signal access<br />
+ cross talk<br />
radiation & shielding<br />
impedance PWR/GND
Layer Stack #2<br />
VCC<br />
signals<br />
signals<br />
GND<br />
+ radiation & shielding<br />
+ impedance PWR/GND<br />
supply buffering<br />
signal access<br />
cross talk
Layer Stack #3<br />
VCC<br />
GND<br />
signals<br />
signals<br />
GND<br />
GND<br />
+ supply blocking<br />
+ cross talk<br />
+ radiation & shielding<br />
+ impedance PWR/GND<br />
signal access
command DRC<br />
Layer Setup #1<br />
prepreg<br />
core
Layer Setup #2<br />
prepreg<br />
prepreg<br />
prepreg<br />
core<br />
core<br />
4 layers<br />
1 x core<br />
2 x prepreg<br />
1+2*15+16<br />
4 layers<br />
2 x core<br />
1 x prepreg<br />
1*2+15*16<br />
6 layers<br />
2 x core<br />
3 x prepreg<br />
1+2*3+14*15+16
command DRC<br />
Layer Setup #3<br />
copper thickness<br />
core/prepreg thickness
Vias #1<br />
through<br />
buried<br />
blind<br />
micro<br />
(very small drill<br />
diameter)<br />
(1+2*15+16)<br />
1+(2*15)+16<br />
[15:1+2*15+16]<br />
[1+2*15+16:15]
command VIA<br />
Vias #2
Routing #1<br />
BlindVia from top<br />
to layer 2<br />
BuriedVia from layer 2<br />
to layer 15<br />
BlindVia from layer 15<br />
to layer 16<br />
ThroughVia from<br />
top to bottom layer<br />
test pads for ICT, FPT, … ?
Routing #2
Checklist :<br />
http://www.<strong>train</strong>z.de/pdf/Design_Checklist_en.pdf
Documentation #1<br />
Layer 21/22 und 51/52<br />
Commands:<br />
SMASH,<br />
MOVE,<br />
GROUP,<br />
CHANGE<br />
SIZE<br />
RATIO<br />
before:<br />
after:<br />
ULP : normalizetext
Documentation #2<br />
Layers 51 and 52 (tDocu / bDocu)<br />
commands TEXT, WIRE, MOVE, GROUP,<br />
CHANGE TEXT / SIZE / RATIO
Layer 21/22 (tPlace / bPlace)<br />
Documentation #3
drawing frame<br />
Layer 48 (Document)<br />
Documentation #4<br />
commands<br />
ADD,<br />
MOVE,<br />
GROUP
Bill Of Material<br />
& Net List ...<br />
Commands: EXPORT PART, EXPORT NET<br />
RUN bom<br />
RUN exportictnetlistpadcoordinates<br />
RUN ipcd356<br />
RUN statisticbrd<br />
- Assembly Variants<br />
- Export from BRD/SCH
DXFImport/Export<br />
Export ULP: dxf.ulp<br />
For active layers only !<br />
Import :<br />
http://www.cadsoft.de/downloads/toolsandconverters
Library Structure #1
Library Structure #2
Library Structure #3
Library Structure #4
Library Structure #5
Library Structure #6
Set Up Your Library #1
Set Up Your Library #2<br />
ULP : check-used-lbrs
Copying Symbols #1<br />
in source library commands: GROUP, CUT
Copying Symbols #2<br />
In destination library create new symbol, then<br />
command: PASTE
commands:<br />
WIRE,<br />
PIN,<br />
TEXT,<br />
CHANGE<br />
DIR<br />
FONT<br />
SIZE<br />
Editing Symbols
Rename / Delete Symbols<br />
in current library commands:<br />
RENAME NAND.sym NAND_OC.sym<br />
REMOVE NAND.sym
Copying Package #1<br />
Drag & Drop
Copying Package #2<br />
in source library commands: GROUP, CUT
Copying Package #3<br />
in destination library create new package, then<br />
command: PASTE
commands:<br />
Editing Package #1<br />
LAYER,<br />
PAD,<br />
SMD,<br />
WIRE,<br />
MOVE,<br />
GROUP,<br />
DEL,<br />
NAME,<br />
CHANGE<br />
ULPs: cmdsnappads , printinductor , spiralcoil
commands:<br />
PAD,<br />
WIRE,<br />
NAME<br />
Editing Package #2<br />
Layer Millings<br />
Notify PCB house !
Notify PCB house !!<br />
Editing Package #3
Editing Package #4
Options / Set / Misc<br />
Editing Package #2
Rename / Delete Package<br />
in current library commands:<br />
RENAME DIL14.pac DIL14.pac<br />
REMOVE DIL14.pac
Copying Device
Create Device #1
Create Device #2<br />
commands ADD, PACK, CONNECT, TECH, ATTR<br />
ULPs : expprojectlbr , makesymboldevicepackagebsdl
Library Tutorial<br />
http://www.<strong>train</strong>z.de/pdf/library_tutorial.pdf
CAMProcessor #1
CAMProcessor #2
CAMProcessor #3
PentaLogix ViewMate #1<br />
Pentalogix Inc.<br />
4749 Hastings Place<br />
Lake Oswego, OR 97035<br />
USA<br />
Tel.: (800) 2381920 or (503) 8289409<br />
Fax: (503) 8289408<br />
Email: support@pentalogix.com<br />
Web: www.pentalogix.com
PentaLogix ViewMate #2
PentaLogix ViewMate #3
PentaLogix ViewMate #4
Milling Outlines #1
Milling Outlines #2<br />
1. RUN outlines.ulp<br />
2. SCRIPT *.scr<br />
3. CAMProcessor ...
Drills & Holes #1
Drills & Holes #2
Drills & Holes #3
RUN drillegend.ulp<br />
Drills & Holes #4
Logos #1<br />
command: RUN importbmp.ulp
Logos #2<br />
1.<br />
3.<br />
2.
Logos #3<br />
3.
Logos #4
6 Layer Demo<br />
Thanks to: Key Design Electronics Ltd. http://www.kdel.co.uk/<br />
26 Lancaster Way, Scalby, Scarborough, YO13 0QH, England<br />
+44 (0) 1723 341809
Boundary Scan System M1<br />
Testing Boards<br />
without Adaptor ?<br />
System M1<br />
click here !<br />
What is Boundary Scan ?
German PCB Houses:<br />
Links #1<br />
www.qprint.de<br />
www.jlp.de<br />
(prototypes)<br />
(mass production)<br />
PCB Assembly in Germany:<br />
www.epsa.de<br />
www.hasec.de<br />
www.ertron.de
Links #2<br />
Run Windows Software on your Linux PC !<br />
700 Raymond Ave.<br />
Suite 120<br />
Saint Paul, MN 55114<br />
USA<br />
Tel. +1 651.523.9300<br />
Fax +1 651.523.9399<br />
http://www.codeweavers.com
Thanks for your Attention !