Design and Implementation of NOC Based 16 PE

Design and Implementation of NOC Based 16 PE
O.Hammami, , K.Hamwi, M.H.Jabbar,M.Khaddour,A.Mzah
ENSTA Paristech,
75739, Paris, France
hammami@ensta.fr
Abstract— Multiprocessor system on chip is now emerging in
many embedded system applications. With the transistor
technology continue to be smaller in geometry, integration of
large number of processors and other components is possible.
However, communication has become crucial as the number of
processors and IP blocks is increased in the MPSoC architecture.
Network on Chip (NoC) is an alternative to bus based
communication approach which provides superior advantages.
In this paper, we designed and implemented NoC-based MPSoC
design on Xilinx Virtex 4 LX200 FPGA. Two NoC architecture;
2-ary 4-tree and 2-ary 4-fly, is developed to be used for the
MPSoC communication.
Keywords— MPSoC, NoC, FPGA.
The netlist is converted to EDF files to be used by ZeBu
Compiler. In ZeBu compiler, several threads are performed in
parallel for synthesis, place and route process on the target
board. Software application is developed at this point in the
Xilinx EDK tool using C programming.
Xilinx IP
Library
Processors,
BRAMs
MHS File
Xilinx EDK
NoC Architecture
PDD File
Arteris
NoCcompiler
Arteris
Danube IP
Library
I. INTRODUCTION
The aim of this work is to demonstrated MPSoC design
with 16 MicroBlazes as master and 16 SSRAMs as slave. The
masters and slaves are connected through 2-ary 4-tree and 2-
ary 4-fly NoC architecture. It is chosen due to the similar
properties in terms of the number of master and slave such
that fair comparison can be made. Several interfaces have
been designed to accommodate different communication
standard between MicroBlaze and SSRAM with the NoC.
Additional Application Programming Interface (APIs) is also
developed used for synchronization of the masters.
II. DESIGN FLOW
Xilinx Platgen
RTL File (vhdl)
RTL File (vhdl)
Xilinx XST and
ngc2edf
EDF Files
Zebu Compiler
(zCui)
SW Applications
EDK
The design flow of the work is shown in Fig. . The first step
is designing NoC architecture using based on various
components to be used to construct a NoC architecture such as
switches, Network Interface Unit (NIU), route table, adapter
and etc. Once the NoC is successful designed, VHDL files can
be generated with the testbench.The VHDL file of the NoC is
then integrated in the Xilinx EDK tool for designing MPSoC
as an IP core. In the EDK, MicroBlaze processors and
SSRAM is connected using NoC architecture through
modifying Microprocessor Hardware Specification (MHS) file.
The design is then translated to netlist using Platform
Generation within the Xilinx EDK tool
.
Fig. 1 ZeBu UF-4 board
Xilinx PAR
(thread 1)
. . .
Bit File
Xilinx PAR
(thread N)
Execution
ELF Files
VHEX Files
Fig. 2 Design flow for MPSoC with NoC architecture
Report Files
The ELF files generated from Xilinx EDK tool is then
converted to VHEX files to be used to execute to the target
board with the bit file generated from ZeBu Compiler. OCP
has been used to interface between MicroBlaze (masters) and
SSRAM (slaves) to the NoC. It is defined by an international
committee, OCP-IP [8]. The protocol is independence from
bus protocols and allows us to develop reusable IP cores
without having loss of high performance access to the NoC.
1

The OCP protocol uses 32 bit data width for masters as well
as slave connection.
ZeBu UF-4 board as shown in Fig. has 4 FPGA devices based
on Xilinx Virtex-4 LX200 that is equivalent of 6 million of
ASIC gates on a single PCI card [9].
The structure of MPSoC is shown in Fig.3 for the design with
2-ary 4-tree and 2-ary 4-fly NoC architecture respectively. All
the MPSoC have been realized using Embedded Design Kit
(EDK) tools from Xilinx [10]. MicroBlaze softcore processor,
as shown in Figure 5, is used as masters and SSRAM is used
as slaves for all MPSoC designs. The MicroBlaze is an
embedded soft core processors from Xilinx based on 32 bits
Reduced Instruction Set Computer (RISC). It is highly
reconfigurable and offer design flexibility in which users can
select several configuration options such as floating point
Microblaze 0
Microblaze 1
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.0
1.0
2.0
Network-on-chip
3.0
4.0
5.0
6.0
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 0
SRAM 1
units, integer multiplier and integer divider. The MicroBlaze
processor is configured to its full configuration and is given
additional local 32 kB Block Random Access Memory
(BRAM) memory connected via two LMB BRAM Memory
Controllers using 2 LMBs (Local Memory Bus) to provide
Instruction Memory (via ILMB port) and Data Memory (via
DLMB port). The MicroBlaze uses Fast Simplex Link (FSL)
for its interconnection. FSL bus is a uni-directional connection,
provides simple and fast point-to-point communication
between two components in the EDK environment. Off chip
memory is used for the slave due to the large size is needed to
stored the data block. Using SRAM from the ZeBu UF4 board,
each slave has the value of 2 MB.
FSL-to-OCP OCP-to-NTTP
NTTP-to-OCP OCP-to-BRAM
Microblaze 0 Network -on-chip
SRAM 0
interface
interface
interface
interface
0.0
1.0
2.0
3.0
FSL-to-OCP OCP-to-NTTP
NTTP-to-OCP OCP-to-BRAM
Microblaze 1
interface
interface
interface
interface
SRAM 1
Microblaze 2
FSL-to-OCP
interface
OCP-to-NTTP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
SRAM 2
Microblaze 2
Microblaze 3
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.1
1.1
2.1
3.1
4.1
5.1
6.1
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 2
SRAM 3
Microblaze 3
Microblaze 4
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.1
1.1
2.1
3.1
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 3
SRAM 4
Microblaze 4
Microblaze 5
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.2
1.2
2.2
3.2
4.2
5.2
6.2
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 4
SRAM 5
Microblaze 5
Microblaze 6
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.2
1.2
2.2
3.2
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 5
SRAM 6
Microblaze 6
Microblaze 7
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.3
1.3
2.3
3.3
4.3
5.3
6.3
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 6
SRAM7
Microblaze 7
FSL-to-OCP
interface
OCP-to-NTTP
interface
0.3
1.3
2.3
3.3
NTTP-to-OCP
interface
OCP-to-BRAM
interface
SRAM 7
Microblaze 8
Microblaze 9
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.4
1.4
2.4
3.4
4.4
5.4
6.4
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 8
SRAM 9
Microblaze 8
Microblaze 9
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.4
1.4
2.4
3.4
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 8
SRAM 9
Microblaze 10
Microblaze 11
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.5
1.5
2.5
3.5
4.5
5.5
6.5
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 10
SRAM 11
Microblaze 10
Microblaze 11
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.5
1.5
2.5
3.5
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 10
SRAM 11
Microblaze 12
Microblaze 13
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.6
1.6
2.6
3.6
4.6
5.6
6.6
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 12
SRAM 13
Microblaze 12
Microblaze 13
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.6
1.6
2.6
3.6
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 12
SRAM 13
Microblaze 14
Microblaze 15
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.7
1.7
2.7
3.7
4.7
5.7
6.7
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 14
SRAM 15
Microblaze 14
Microblaze 15
FSL-to-OCP
interface
FSL-to-OCP
interface
OCP-to-NTTP
interface
OCP-to-NTTP
interface
0.7
1.7
2.7
3.7
NTTP-to-OCP
interface
NTTP-to-OCP
interface
OCP-to-BRAM
interface
OCP-to-BRAM
interface
SRAM 14
SRAM 15
III. EXPERIMENTAL RESULTS
TABLE I compares the FPGA resources of the two NoC
architectures in the MPSoC design. 2-ary 4-tree architecture
has more slices than 2-ary 4-fly NoC for about 2% because it
contains more switches. For BRAM and DSP48, both NoC
IV. CONCLUSION
In this paper, we discussed the design and implementation
on FPGA of MPSoC with NoC architecture. Two MPSoC
designs with different NoC architecture have been executed
on Virtex 4 LX200 FPGA from Xilinx. The design is
evaluated using parallel programming DCT algorithm. Result
shown that for DCT application on 2-ary 4-fly NoC
architecture has slightly better speedup 2-ary 4-fly NoC
architecture. In terms of logic utilization, MPSoC design with
2-ary 4-fly used more 2% of slices than 2-ary 4-fly NoC
architecture.
Fig. 1 Block diagram of MPSoC with 2-ary 4-fly NoC architecture
TABLE I
LOGIC UTILIZATION OF MPSOC WITH DIFFERENT NOC ARCHITECTURE
NoC Topology Slices % BRAM % DSP %
2-ary 4-tree 40.73 76.49 50
2-ary 4-fly 38.00 76.49 50
architectures have the same value which is 76% and 50%
respectively. These values are come from the MPSoC design
such as MicroBlaze processors and other IPs such as OCP
interfaces.
[1] W. Wolf, A. A. Jerraya, and G. Martin, "Multiprocessor System-on-
Chip (MPSoC) Technology," Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on, vol. 27, pp. 1701-1713,
2008.
[2] OCP-IP, www.ocpip.org.
[3] EVE, "ZeBu UF-4," http://www.eve-team.com.
[4] Xilinx, www.xilinx.com.
REFERENCES
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