TUESDAY KEYNOTE MIKE MULLER - DAC

TUESDAY KEYNOTE 

June 5, 8:30 - 9:30am 

SUMMARY: 

Comparing the original ARM design of 1985 to those of 

today’s latest microprocessors, Mike will look at how far 

has design come and what EDA has contributed to enabling 

these advances in systems, hardware, operating systems, 

and applications and how business models have evolved 

over 25 years. He will then speculate on the needs for scaling 

designs into solutions for 2020 from tiny embedded sensors 

through to cloud based servers which together enable the 

internet of things. He will look at what are the major challenges 

that need to be addressed to design and manufacture these 

systems and proposes some solutions. 

6 

Room: 102/103 General Interest 

SCALING FOR 2020 SOLUTIONS 

MIKE MULLER 

ARM, Inc., Cambridge, United Kingdom 

www.DAC.com 

BIO: 

Mike Muller was one of the founders of ARM. Before joining 

the Company, he was responsible for hardware strategy and 

the development of portable products at Acorn Computers 

and was part of the original ARM design team. He was 

previously at Orbis Computers who developed network 

computers. At ARM he was VP, Marketing from 1992 to 1996 

and EVP, Business Development until October 2000 when 

he was appointed Chief Technology Officer. In October 2001, 

he was appointed to the board of ARM Holdings plc.

GENERAL SESSION 

Tuesday, June 5, 8:30 - 9:45am Room: 102/103 

OPENING REMARKS - Patrick Groeneveld - 49th DAC General Chair 

AWARDS PRESENTATIONS 

MARIE R. PISTILLI WOMEN IN EDA 

ACHIEVEMENT AWARD 

For her significant contributions in helping women advance in 

the field of EDA technology. 

Dr. Belle W. Y. Wei - Don Beall Dean of the Charles W. 

Davidson College of Engineering, San Jose State Univ. 

P.O. PISTILLI UNDERGRADUATE 

SCHOLARSHIPS FOR ADVANCEMENT 

IN COMPUTER SCIENCE AND 

ELECTRICAL ENGINEERING 

The objective of the P.O. Pistilli Scholarship program is to 

increase the pool of professionals in Electrical Engineering, 

Computer Engineering, and Computer Science from 

under-represented groups (women, African-American, 

Hispanic, Native American, and physically challenged). In 

1989, the ACM Special Interest Group on Design Automation 

(SIGDA) began providing the program. Beginning in 1993, 

the Design Automation Conference provided the funds for the 

scholarship and a volunteer committee continues to administer 

the program for DAC. DAC funds a $4000 scholarship, 

renewable up to five years, to graduating high school seniors. 

The 2012 recipient is: 

Catherine Agor Mullings 

A. RICHARD NEWTON 

GRADUATE SCHOLARSHIPS 

Each year the Design Automation Conference sponsors the 

A. Richard Newton Graduate Scholarship to support 

graduate research and study in Design Automation (EDA). 

Each scholarship is awarded directly to a University for the 

Faculty Investigator to expend in direct support of the project 

and students named in the application. The criteria are: the 

quality and applicability of the proposed research; the impact 

of the award on the EDA program at the institution; the 

academic credentials of the student(s); and financial need. 

This year’s scholarship goes to: 

Advisor: 

Prof. Yiran Chen – Univ. of Pittsburgh 

Student: 

Wujie Wen – Univ. of Pittsburgh 

Project: 

NVSim-VX: Variation Aware Emerging 

Nonvolatile Memory Simulator 

2011 PHIL KAUFMAN AWARD 

FOR DISTINGUISHED 

CONTRIBUTIONS TO EDA 

Sponsored by the EDA Consortium and IEEE Council on EDA 

Dr. C. L. David Liu – William Mong honorary chair professor 

of Computer Science and former president of the National 

Tsing Hua University in Hsinchu, Taiwan 

Dr. C. L. David Liu received this award for his distinguished 

technical contributions, leadership skills, and business 

acumen in electronic design automation. 

Dave Liu is honored for his work in leading the transformation 

from ad hoc EDA to algorithmic EDA. 

IEEE CEDA OUTSTANDING 

SERVICE CONTRIBUTION 

For significant services as DAC General Chair 2011. 

Leon Stok – IBM Corp. 

IEEE FELLOW 

For contributions to analysis and modeling of VLSI interconnects. 

Luis Miguel Silveira – Technical Univ. of Lisbon 

IEEE FELLOW 

For contributions to circuits, architectures, and software technology 

for field-programmable gate arrays. 

Steve Trimberger – Xilinx Inc. 

IEEE FELLOW 

For contributions to system-level power characterization, including 

thermal management. 

Naehyuck Chang – Seoul National Univ. 

DONALD O. PEDERSON BEST PAPER 

AWARD FOR THE IEEE TRANSACTION 

ON CAD 

For the paper titled: “An Analytical Approach for Network-on- 

Chip Performance Analysis,” IEEE Transaction on Computer- 

Aided Design of Integrated Circuits and Systems, December 

2010, Vol. 29, No. 12, pp. 2001-2013. 

Umit Ogras – Intel Corp. 

Paul Bogdan – Carnegie Mellon Univ. 

Radu Marculescu – Carnegie Mellon Univ. 

ACM/IEEE A. RICHARD NEWTON 

TECHNICAL IMPACT AWARD IN 

ELECTRONIC DESIGN AUTOMATION 

For advancing the theory and implementation of model 

order reduction for efficient circuit analysis via dominant 

pole/zero methods. 

“PRIMA: Passive Reduced-Order Interconnect Macromodeling 

Algorithm,” IEEE Transactions on Computer-Aided Design of 

Integrated Circuits and Systems, August 1998, Vol. 17, Issue 

8, Pages 645-654. 

Altan Odabasioglu – Gear Design Solutions 

Mustafa Celik – Synopsys, Inc. 

Larry Pileggi – Carnegie Mellon Univ. 

SIGDA OUTSTANDING 

NEW FACULTY 

Outstanding New Faculty for 2012. 

David Atienza – Ecole Polytechnique Fédérale de Lausanne 

ACM/SIGDA OUTSTANDING PH.D. 

DISSERTATION AWARD 

In recognition of the outstanding dissertation 

“Algorithmic Studies on PCB Routing.” 

Dr. Tan Yan – University of Illinois at Urbana-Champaign 

Prof. Martin D. Wong (Dissertation Advisor) – 

University of Illinois at Urbana-Champaign 

7

WEDNESDAY KEYNOTE 

June 6, 10:45 - 11:45am 

BIO: 

Joshua Friedrich is a Senior Technical Staff Member and 

Senior Manager of POWER TM Technology Development in 

IBM’s Server and Technology Group. In his role, Josh leads 

the physical design, technology direction, and methodology of 

IBM’s future POWER TM processors. Josh has been part of the 

POWER development team since POWER4 TM , and on past 

POWER TM designs, Josh has led multiple design disciplines 

including power estimation and reduction, hardware 

characterization, memory subsystem circuit development, 

and core execution units. Before joining IBM, Josh received 

his Bachelor of Science in Electrical Engineering from the 

University of Texas at Austin. 

8 

Room: 102/103 User Track 

DESIGNING HIGH PERFORMANCE SYSTEMS-ON-CHIP 

Experience state-of-the art design through the eyes of two 

experts that help shape these advanced chips! In this unique 

dual-keynote, the design process at two leading companies 

will be discussed. The speakers will cover key challenges, 

engineering decisions and design methodologies to achieve 

POWER TM Processor Design 

and Methodology Directions 

JOSHUA 

FRIEDRICH 

IBM Server and Technology 

Group, Austin, TX 

SUMMARY: 

Processor designs and the EDA tools that support them 

stand at a key inflection point. The era of Dennard scaling 

and exponential single thread performance growth is a 

distant memory. Multi-thread performance continues to 

grow. However, the gain from simply adding more cores to 

a die by stepping to the next process node is diminishing 

due to technology challenges, application bottlenecks, and 

power/packaging constraints. To continue to deliver the costperformance 

gains that drive our industry, designers will 

need to bring significant innovation to bear by integrating 

heterogeneous system components and accelerating key 

portions of the software stack in hardware. This transformation 

from technology-driven design to innovation-driven design 

defines new priorities for EDA development compared to 

prior eras. While timing optimization, power reduction, and 

support for modular designs remain necessary, differentiation 

will be achieved by enabling designer productivity through 

technology simplification, design abstraction, and robust 

support for heterogeneous IP. 


top performance and turn-around time. The presentations 

describe where EDA meets practice under the most advanced 

nodes, so will be of key interest to both designers and EDA 

professionals alike. 

Designing a 22nm Intel ® 

Architecture Multi-CPU 

and GPU 

BRAD 

HEANEY 

Intel Corp., Folsom, CA 

SUMMARY: 

With each new process technology node and integration of 

more system components on to a monolithic die, the design 

methodology challenges must advance to enable validation 

and implementation of these complex products. With Intel’s 

new 22nm technology, we are designing products with over 

1.4 billion transistors and integrating hardware blocks that 

naturally want different process and design optimizations. 

The recently launched 3rd Generation Intel Core Process 

(codename Ivy Bridge) has an integrated Graphics Processing 

Unit that has different process and design demands than the 

CPU Core Processor. With the size and diversity of the product 

hardware, combined with new advanced process technology 

features, such as Intel’s new tri-gate transistor, more 

capabilities for silicon debug, coverage, and manufacturing 

need to be planned and incorporated into the architecture 

and design implementation. By close collaboration between 

the process development and design teams at Intel, we are 

able to develop design methods to ramp these large, complex 

products into high volume manufacturing at, or ahead of, the 

schedule on prior products. 

BIO: 

Brad Heaney is an Intel Architecture Group Project Manager 

and operates out of Intel’s Folsom Design Center. Brad is a 

25 year veteran at Intel and started his career working on 

the design of the 80386 family of CPUs and is the holder 

of four patents for his design work. In the last few years, 

Brad has been managing the teams that deliver Intel’s lead 

vehicles for ramping new process technologies. Brad’s team 

developed the Penryn CPU, which was a lead vehicle for 

45nm process technology. In April of this year, they launched 

the Ivy Bridge CPU (3rd Generation Intel Core Processor), 

which is the lead vehicle for Intel’s 22nm process technology. 

Brad received his Bachelor of Science degree from Drexel 

University in Philadelphia and his Master of Science in 

Electrical Engineering degree from Stanford University prior 

to joining Intel.

THURSDAY KEYNOTE 

June 7, 11:00am - 12:00pm 

SUMMARY: 

It was June 1982 that I had my first technical paper in the EDA 

area presented at the 19th Design Automation Conference. It 

was exactly 20 years after I completed my doctoral study and 

exactly 30 years ago from today. I would like to share with the 

audience how my prior educational experience prepared me 

to enter the EDA field and how my EDA experience prepared 

me for the other aspects of my professional life. 

Room: 102/103 General Interest 

MY FIRST DESIGN AUTOMATION 

CONFERENCE - 1982 

C. L. LIU 

National Tsing Hua Univ., Hinschu, Taiwan 

BIO: 

C. L. Liu received his B. Sc. degree (1956) from the National 

Cheng Kung University in Taiwan, and his S. M. (1960) and 

Sc. D. (1962) degrees from the Massachusetts Institute of 

Technology. He taught at the Massachusetts Institute of 

Technology, the University of Illinois at Urbana-Champaign, 

and the National Tsing Hua University in Taiwan. He also 

served as the President of the National Tsing Hua University 

from 1998 to 2002. 

He is currently the William Mong Honorary Chair Professor 

of Computer Science at the National Tsing Hua University, 

an industrial consultant, and the host of a weekly radio show 

(since 2005). He has published over 180 technical papers, 

eight technical textbooks and research monographs in the 

area of EDA, computer –aided instruction, real-time systems, 

combinatorial optimization, and discrete mathematics, and 

seven essay collections in the area of science and humanities. 

www.DAC.com 9

DAC 2012 MANAGMENT DAY 

TUESDAY, JUNE 5 10:00am - 4:00pm 

Room: 309 Additional Registration Fees Apply 

Organizer: 

Yervant Zorian - Synopsys, Inc., Mountain View, CA 

The DAC 2012 Management Day provides managers with timely information to help them make decisions where business and technology intersect. This is a unique 

opportunity for managers to gain insights from their peers in the industry. 

Today’s complex SoCs require different types of optimizations and the adoption of emerging solutions to meet such requirements. Optimizing for volume production, 

low power, and shrinking sizes necessitates accurate trade-off analysis and technical/business decision-making by management. Also, moving to new semiconductor 

technology nodes, such as 20nm or 28nm, can significantly affect the choices of suppliers. The Management Day sessions will discuss these changing needs 

and present corresponding management decision criteria that allow managers to make the right choices from a pool of alternate options for flows, methodologies, 

and suppliers. 

The Management Day is comprised of two sessions, which will feature presentations by managers representing fab-less companies, systems houses and suppliers to 

the design ecosystem. Senior managers will discuss the latest and emerging solutions, along with their economic impact. 

SESSION 1: 

10:00am - 11:30am 

Speakers: 

Vincent Ratford – Senior Vice President, Xilinx, San Jose, CA 

Chi-Feng Wu – Vice President Engineering, Realtek, Hsinchu, Taiwan 

Norbert Diesing – Director Engineering, PMC Sierra, Vancouver, BC, Canada 

SESSION 2: 

1:30 - 4:00pm 

Speakers: 

Ajoy Bose – President CEO, Atrenta, San Jose, CA 

Indavong Vongsavady – Director Engineering, ST Microelectronics, 

Crolles, France 

Pankaj Mayor – Vice President, Cadence Design Systems, San Jose, CA 

Jitendra Khare – Director Engineering, Applied Micro, Sunnyvale, CA 

William Eklow – Distinguished Engineer, Cisco Systems, San Jose, CA 

10 


General Interest 

Decision Making for Complex ICs 

Moving to new semiconductor technology nodes for complex ICs can significantly 

affect the choices of design flow, methodologies and suppliers. This session 

will cover the challenges of complex chip design and present corresponding 

management decision criteria that allow managers to make the right choices from 

a pool of alternate options. This session feature presentations by senior managers 

representing a range of fab-less chip companies. 


Trade-Offs and Choices for Emerging SoCs 

Today’s emerging SoCs require multiple types of optimizations and the adoption 

of advanced solutions to meet stringent design requirements. Optimizing for 

volume production, low-power, and shrinking sizes necessitates accurate trade-off 

analysis and technical/business decision making by management. This session 

will feature senior managers of today’s most complex nanometer chip design 

suppliers, fab-less companies, and system houses.

TECHNICAL SESSIONS 

TUESDAY, JUNE 5 

1 

10:00 - 11:30am 

2 

10:00 - 11:30am 

SPECIAL SESSION: E-HEALTH: 

A KILLER APPLICATION FOR ELECTRONIC DEVICES? 

Chair: 

Rajesh Gupta - Univ. of California at San Diego, La Jolla, CA 

New electronic systems for diagnostics and care are changing the practice of 

health management, opening the door to personalized medicine as well as to 

support for remote care of chronic patients. This session starts with a survey of 

the field, and then presents the latest inroads in bio-sensing and data acquisition 

chains, and finally terminates with a presentation of security aspects as a key 

design problem. Design challenges and design flows for the emerging biomedical 

electronic systems will be presented. 

3 

10:00 - 11:30am 

PANEL: WILL RELIABILITY BE THE 

DEATH OF MOORE’S LAW? 

Chair: 

Ana Hunter - Samsung, San Jose, CA 

Speakers: 

Naresh R. Shanbhag - Univ. of Illinois at Urbana-Champaign, Urbana, IL 

Jose Maiz - Intel Corp., Portland, OR 

Sani Nassif - IBM Research, Austin, TX 

Subhasish Mitra - Stanford Univ., Stanford, CA 

Goeran Jerke - Robert Bosch GmbH, Reutlingen, Germany 

Room: 304 

Bio Design Automation 

2.1 Biomedical Electronics Serving as Physical, 

Environmental, and Emotional Guardians? 

Rudy Lauwereins - IMEC, Leuven, Belgium 

2.2 Integrated Biosensors for Personalized Medicine 

Giovanni De Micheli, Cristina Boero, Camilla Baj-Rossi, Irene Taurino, 

Sandro Carrara - Ecole Polytechnique Fédérale de Lausanne, Switzerland 

2.3 Design Challenges for Secure Implantable Medical Devices 

Wayne Burleson, Shane Clark, Ben Ransford, Kevin Fu 

- Univ. of Massachusetts, Amherst, MA 

DESIGN AUTOMATION FOR THINGS WET, 

SMALL, SPOOKY, AND TAMABLE 

Chair: 

Tsung-Yi Ho - National Cheng Kung Univ., Tainan, Taiwan 

The future of design automation may well be in novel technologies and in new 

opportunities. This session begins with design techniques that in the past may 

have applied exclusively to electronic design automation, but now are applied to 

the wet (microfluidics), the small (nanoelectronics), and the spooky (quantum). The 

papers cover routing and placement, pin assignment, cell design, and technology 

mapping applied to microfluidics biochips, quantum gates, and silicon nanowire 

transistors. The last paper, a perspective, details (tamable) challenges to solve 

energy arbitration, alternative energy sourcing and capacity provisioning for 

computational resources through dynamic deferral of energy loads. 

3.1 Design of Pin-Constrained General-Purpose 

Digital Microfluidic Biochips (10:00am) 

Yan Luo, Krishnendu Chakrabarty - Duke Univ., Durham, NC 

Room: 305 

Room: 300 

Design for Manufacturability 

The latest technology roadmap cites “reliability and resilience” as key long-term 

challenges to continue the Moore’s Law scaling. How much will electromigration, 

aging, and thermal effects limit the benefits of smaller process geometries? Is 

the cost of reliability (margins, area, power) a showstopper? To what extent will 

new architectures and design tools mask unreliability? This panel discusses these 

issues and looks at how reliability challenges could limit product design over the 

coming decade. 

Emerging Technologies 

3.2 Path Scheduling on Digital Microfluidic Biochips (10:15am) 

Daniel Grissom, Philip Brisk - Univ. of California, Riverside, CA 

3.3 Realizing Reversible Circuits Using a New 

Class of Quantum Gates (10:30am) 

Zahra Sasanian, Michael Miller - Univ. of Victoria, Victoria, BC, Canada 

Robert Wille - Univ. of Bremen, Germany 

3.4 Physical Synthesis onto a Sea-of-Tiles with 

Double-Gate Silicon Nanowire Transistors (10:45am) 

Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De 

Micheli - Ecole Polytechnique Fédérale de Lausanne, Switzerland 

3.5 A Microgrid View of Energy Efficient Systems (11:00am) 


www.DAC.com Best Paper Nominees are Denoted in Orange. Perspective Papers are Denoted in Dark Gray. 11



4 BE 

10:00 - 11:30am 

5 

12 

DESIGN AND DATA SECURITY: IS IT EVEN POSSIBLE? 

10:00 - 11:30am Room: 308 

Chair 

Mohammad Tehranipoor - Univ. of Connecticut, Mansfield, CT 

Threats against IC design information and data integrity are on the rise. 

The potential costs of IP counterfeiting and secure data exposure motivate 

research activity in this area. As design processes are distributed physically, the 

vulnerable attack surface increases dramatically, necessitating robust security 

approaches. This session explores hardware design approaches to protecting 

design information from theft or modification, and securing sensitive data onchip. 

The techniques investigated in the papers of this session include the design 

of physically unclonable functions, hardware trojan detection, dynamic power 

analysis defenses, and design obfuscation. 

5.1 A Code Morphing Methodology to Automate Power 

Analysis Countermeasures (10:00am) 

Gerardo Pelosi, Giovanni Agosta, Alessandro Barenghi 

- Politecnico di Milano, Milan, Italy 

6 SYSTEM 

10:00 - 11:30am 

EFFICIENT: LOW-POWER DESIGN TECHNIQUES 

Chair 

Hamid Mahmoodi - San Francisco State Univ., San Francisco, CA 

Power consumption is one of the critical challenges in advanced technologies. 

Exploiting power and sleep modes reduces power when the circuit is idle as in the 

first paper in the session, or to dynamically adjust voltage and frequency (DVFS) 

as in the second. Memories make up a large portion of current and future systems 

and it is important to accurately estimate their power consumption as in the third 

paper, or to reduce the energy of emerging memory technologies, as in the fourth 

paper. 

4.1 A Semiempirical Model for Wakeup Time Estimation 

in Power-Gated Logic Clusters (10:00am) 

Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien 

- Univ. de Rennes 1, Lannion, France 

5.2 Security Analysis of Logic Obfuscation (10:15am) 

Jeyavijayan Rajendran, Ramesh Karri - Polytechnic 

Institute of New York Univ., Brooklyn, NY 

Youngok Pino - Air Force Research Lab, Rome, NY 

Ozgur Sinanoglu - New York Univ., Abu Dhabi, United Arab Emirates 

5.3 Hardware Trojan Horse Benchmark via Optimal Creation 

and Placement of Malicious Circuitry (10:30am) 

Miodrag Potkonjak, Sheng Wei - Univ. of California, Los Angeles, CA 

Kai Li, Farinaz Koushanfar - Rice Univ., Houston, TX 

5.4* On Improving the Uniqueness of Silicon-Based Physically 

Unclonable Functions via Optical Proximity Correction (10:45am) 

Domenic Forte, Ankur Srivastava - Univ. of Maryland, College Park, MD 

SIMULATION: THE NEED FOR SPEED! 

Chair 

Gunar Schirner - Northeastern Univ., Boston, MA 

Simulation is an integral part of system design and exploration. There is a continued 

quest for speeding and improving the performance of full system simulation 

by either finding the right level of abstraction or accelerating the underlying 

simulation infrastructure. This session presents state of the art approaches from 

both domains ranging from hybrid MPSoC model to GPU platforms, focusing on 

optimizing synchronization, parallelizing, and accelerating full system simulation. 

6.1 Transformer: A Functional-Driven CycleAccurate 

Multicore Simulator (10:00am) 

Zhenman Fang, Qinghao Min, Keyong Zhou, Yi Lu, Yibin Hu, 

Weihua Zhang, Binyu Zang - Fudan Univ., Shanghai, China 

Haibo Chen - Shanghai Jiao Tong Univ., Shanghai, China 

Jian Li - IBM Corp., Austin, TX 

Room: 306 

Room: 310 

4.2 Cost-Effective Power Delivery to Support Per-Core Voltage 

Domains for Power-Constrained Processors (10:15am) 

Nam Sung Kim, Hamid Reza Ghasemi, 

Abhishek Sinkar - Univ. of Wisconsin, Madison, WI 

Mike Schulte - Advanced Micro Devices, Inc., Austin, TX 

4.3 A Hybrid and Adaptive Model for Predicting Register File 

and SRAM Power Using a Reference Design (10:30am) 

Eric Donkoh, Alicia P. Lowery, Emily Shriver - Intel Corp., Hillsboro, OR 

4.4 Coding-Based Energy Minimization for 

Phase Change Memory (10:45am) 

Azalia Mirhoseini, Farinaz Koushanfar - Rice Univ., Houston, TX 

Miodrag Potkonjak - Univ. of California, Los Angeles, CA 

6.2 SAGA: SystemC Acceleration on GPU Architectures (10:15am) 

Sara Vinco, Franco Fummi - Univ. of Verona, Italy 

Debapriya Chatterjee, Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI 

6.3 Synchronization for Hybrid MPSoC Full-System Simulation (10:30am) 

Luis Gabriel Murillo, Juan Eusse, Jovana Jovic, Sergey Yakoushkin, 

Rainer Leupers, Gerd Ascheid - RWTH Aachen Univ., Aachen, Germany 

6.4 A Non-Intrusive Timing Synchronization Interface for 

Hardware-Assisted HW/SW Co-Simulation (10:45am) 

Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay 

- National Tsing Hua Univ., HsinChu, Taiwan 

www.DAC.com Best Paper Nominees are Denoted in Orange 

Low-Power Design and Power Analysis 

Embedded System Validation and Verification 

System Level Design and Communication



7 

1:30 - 3:00pm 

8 

PANEL: SYSTEM MODELS - DOES ONE SIZE FIT ALL? 

Chair 

Brian Bailey - EETimes EDA Designline, Oregon City, OR 

Speakers: 

Stuart Swan - Cadence Design Systems, Inc., San Jose, CA 

Rick Higgins - Qualcomm, Inc., San Diego, CA 

John Goodenough - ARM, Inc., San Jose, CA 

Frederic Risacher - Research in Motion, Ltd., Waterloo, ON, Canada 

Andrea Kroll - Tensilica, Inc., San Jose, CA 

SPECIAL SESSION: CAN EDA COMBAT THE RISE OF 

ELECTRONIC COUNTERFEITING? 

1:30 - 3:00pm Room: 304 

Chair 


The Semiconductor Industry Association (SIA) estimates that counterfeiting 

costs the US semiconductor companies $7.5B in lost revenue, and this is indeed 

a growing global problem. Repackaging the old ICs, selling the failed test parts, 

as well as gray marketing, are the most dominant counterfeiting practices. Can 

technology do a better job than lawyers? What are the technical challenges 

to be addressed? What EDA technologies will work: embedding IP protection 

measures in the design phase, developing rapid post-silicon certification, or 

counterfeit detection tools and methods? 

9 

RELIABILITY: FROM ATOMS TO 3-D 

1:30 - 3:00pm 

Chair 

Angan Das - Intel Corp., Santa Clara, CA 

With shrinking device sizes and increasing design complexity, reliability has 

become a critical issue. Besides traditional reliability issues for power delivery 

networks and clock signals, new challenges are emerging. This session presents 

papers that cover a wide spectrum of reliability issues including long-term 

device aging, verification of power and 3-D ICs, and high-integrity, low-power 

clock networks. 

9.1* Physics Matters: Statistical Aging Prediction 

under Trapping/Detrapping (1:30pm) 

Jyothi Bhaskarr Velamala, Ketul B. Sutaria, 

Yu Cao - Arizona State Univ., Tempe, AZ 

Takashi Sato - Kyoto Univ., Kyoto, Japan 

Room: 305 System Level Design and Communication 

System-level modeling is a critical part of product design flows. Developing 

a single model that simultaneously satisfies the needs of software developers, 

system architects, hardware developers, and verification engineers is hard. Time of 

availability, usage models, accuracy requirements, development effort, and speed 

vary greatly. Is it possible for one size to fit all? Who will provide the models? Who 

will pay for them? The panelists will review different aspects of system modeling 

and discuss which abstraction levels best address specific user requirements. 


8.1 Can EDA Combat the Rise of Electronic Counterfeiting? 

Carl McCants - Defense Advanced Research Projects Agency, Arlington, VA 

William Bryson - Analytical Solutions, Inc., Albuquerque, NM 

Matthew Sale - U.S. Naval Surface Warfare Center, Crane, IN 

Peilin Song - IBM Research, Yorktown Heights, NY 

Farinaz Koushanfar - Rice Univ., Houston, TX 

Saverio Fazzari - Booz Allen Hamilton, Inc., Arlington, VA 


Room: 300 

Verification and Test 

9.2 Library-Aware Resonant Clock Synthesis (LARCS) (1:45pm) 

Xuchu Hu - Cadence Design Systems, Inc., Univ. of California, Santa Cruz, CA 

Walter Condley, Matthew Guthaus - Univ. of California, Santa Cruz, CA 

9.3 Incremental Power Grid Verification (2:00pm) 

Abhishek, Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada 

9.4 Analysis of DC Current Crowding in Through-Silicon-Vias 

and its Impact on Power Integrity in 3-D ICs (2:15pm) 

Sung Kyu Lim, Xin Zhao - Georgia Institute of Technology, Atlanta, GA 

Michael Scheuermann - IBM T.J. Watson Research Ctr., Yorktown Heights, NY 

Best Paper Nominees are Denoted in Orange www.DAC.com 13



10 

1:30 - 3:00pm 

11 

12 

14 

EDA FOR EMERGING APPLICATIONS AT THE KILOMETER, 

METER, MICRON, AND NANOMETER SCALES 

Chair 

Sai-Wang (Rocco) Tam - Marvell Semiconductor, Inc., Santa Clara, CA 

The design automation community has traditionally been both active and 

successful in accelerating the realization of hardware for emerging application 

spaces. Of growing interest are energy-efficient living spaces and healthcare. The 

first two presentations in this session address cyber physical systems that could 

make home appliances more energy-efficient and improve human mobility. Also of 

significant interest are wireless communication and new display technologies. The 

last two presentations provide a discussion of MEMS-based filters that could 

enable software-defined radio, and techniques for managing Vth and mobility 

variations for improved LED displays. 

1:30 - 3:00pm 

FACING DEPENDABILITY: SYSTEM-LEVEL SOLUTIONS 

AND CYBERCAR CHALLENGES 

Chair 

Hans-Joachim Wunderlich - Univ. of Stuttgart, Stuttgart, Germany 

Dependability has became a major design constraint for embedded systems. 

Whereas early work on dependability has concentrated at lower abstraction 

levels, recent research increasingly explores system-level approaches. Run-time 

adaptivity is a promising approach to cope with the dependability challenges at 

the system level. This session addresses system-level dependability from several 

facets such as analysis, cure, and diagnosis. The last paper, a perspective, outlines 

how the arrival of Cybercars calls for novel abstractions, models, protocols, design 

methodologies, testing and evaluation tools to automate the integration, and 

analysis of the sophisticated critical dependeability and security requirements. 

11.1 Towards Fault-Tolerant Embedded Systems 

with Imperfect Fault Detection (1:30pm) 

Jia Huang, Kai Huang, Andreas Raabe, Christian 

Buckl - fortiss GmbH, Munich, Germany 

Alois Knoll - Technische Univ. München, Germany 

1:30 - 3:00pm 

VOLATILE OR NON-VOLATILE? THAT’S THE QUESTION 

Chair 

Tei-Wei Kuo - National Taiwan Univ., Taipei City, Taiwan 

Non-volatile memories are attractive because they retain information even when 

they are powered off. However, several challenges need to be addressed before 

they can be successfully deployed. One major problem is the limited number of 

writes that non-volatile memory cells can endure before they start failing. Papers 

in this session propose architectural schemes to improve the lifetime and reliability 

of non-volatile memories with minimal power and performance overheads. 

12.1 Software Controlled Cell Bit-Density to 

Improve NAND Flash Lifetime (1:30pm) 

Xavier Jimenez, David Novo, Paolo Ienne - 

Ecole Polytechnique Fédérale de Lausanne, Switzerland 

Room: 306 

Room: 308 

Room: 310 

10.1 Tracking Appliance Usage Information in Residential Settings 

Using Off-the-Shelf Low-Frequency Meters (1:30pm) 

Deokwoo Jung - Advanced Digital Sciences Center, Singapore 

Athanasios Bamis - Univ. of Connecticut, Storrs, CT 

Andreas Savvides - Yale Univ., New Haven, CT 

10.2 Implementing an FPGA System for Real-Time Intent 

Recognition for Prosthetic Legs (1:45pm) 

Xiaorong Zhang, He Huang, Qing Yang - Univ. of Rhode Island, Kingston, RI 

10.3 Statistical Design and Optimization for Adaptive 

Post-silicon Tuning of MEMS Filters (2:00pm) 

Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. 

Fedder, Tamal Mukherjee, Larry Pileggi - Carnegie Mellon Univ., Pittsburgh, PA 

10.4 Generic Low-Cost Characterization of VTH and 

Mobility Variations in LTPS TFTs for Non-Uniformity 

Calibration of Active-Matrix OLED Displays (2:15pm) 

Reza Chaji, Javid Jaffari - IGNIS Innovations, Inc., Waterloo, ON, Canada 

11.2 Steady-State Dynamic Temperature Analysis and Reliability 

Optimization for Embedded Multiprocessor Systems (1:45pm) 

Ivan Ukhov, Min Bao, Petru Eles, Zebo Peng - 

Linköping Univ., Linköping, Sweden 

11.3 Considering Diagnosis Functionality during Automatic 

System-Level Design of Automotive Networks (2:00pm) 

Michael Glass, Michael Eberl, Jürgen Teich - 

Univ. of Erlangen-Nuremberg, Germany 

Ulrich Abelein - Audi AG, Ingolstadt, Germany 

11.4 Meta-Cure: A Reliability Enhancement Strategy for Metadata 

in NAND Flash Memory Storage Systems (2:15pm) 

Yi Wang, Zili Shao - The Hong Kong Polytechnic Univ., Hong Kong 

Luis Angel D. Bathen, Nikil Dutt - Univ. of California, Irvine, CA 

11.5 EDA for Secure and Dependable Cybercars: 

Challenges and Opportunities (2:30pm) 


Ing. Ahmad-Reza Sadeghi, Hervé Seudié - 

Technische Univ. Darmstadt, Germany 

12.2 Observational Wear Leveling: An Efficient Algorithm 

for Flash Memory Management (1:45pm) 

Chundong Wang, Weng-Fai Wong - National Univ. of Singapore, Singapore 

12.3 Cache Revive: Architecting Volatile STT-RAM Caches 

for Enhanced Performance in CMPs (2:00pm) 

Adwait Jog, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, 

Chita R. Das - Pennsylvania State Univ., University Park, PA 

Asit K. Mishra, Ravishankar Iyer - Intel Corp., Hillsboro, OR 

12.4 Point and Discard: A Hard-Error-Tolerant Architecture 

for Non-Volatile Last Level Caches (2:15pm) 

Jue Wang, Xiangyu Dong, Yuan Xie - 

Pennsylvania State Univ., University Park, PA 



Embedded Design Methodology and Case Studies 

Embedded Architecture & Platforms



13 PANEL: WILL YOUR NEXT ASIC EVER BE AN FPGA? 

4:00 - 6:00pm Room: 305 

Chair: 

Kevin Morris - EE Journal, Portland, OR 

Speakers: 

Brent Przybus - Xilinx, Inc., San Jose, CA 

Misha Burich - Altera Corp., San Jose, CA 

Bill Lynch - Huawei Technologies Co., Ltd., Santa Clara, CA 

Dave Ofelt - Juniper Networks, Inc., Sunnyvale, CA 

Jeanne Trinko Mechler - IBM Corp., Burlington, VT 

John Frediani - Advantest America, Inc., Cupertino, CA 

14 

As each technology node increases in cost, the economics for FPGAs become more 

compelling. FPGAs have gotten larger, faster, and cooler while still maintaining 

flexibility. Have these factors brought us to a tipping point? Alternatives in process 

node, shuttles, and 3-D IC offer choices in the cost, performance, and power 

tradeoffs. What products are on the precipice of a decision in favor of FPGAs? 

Witness our expert panelists define the tradeoff point between FPGAs and ASICs. 

SPECIAL SESSION: SELF-AWARE AND ADAPTIVE 

TECHNOLOGIES: THE FUTURE OF COMPUTING SYSTEMS? 

4:00 - 6:00pm 

Chair 

Xiaoyun Zhu - VMware, Inc., Palo Alto, CA 

This session will present contributions from industry and universities toward 

the realization of next-generation computing systems based on Self-Aware 

computing. Self-Aware computing is an emerging system design paradigm aimed 

at overcoming the exponentially increasing complexity of modern computing 

systems and improving performance, utilization, reliability, and programmability. 

In a departure from current systems which are based on design abstractions that 

have persisted since the 1960s which place significant burden on programmers 

and chip designers, Self-Aware systems mitigate complexity by observing their own 

runtime behavior, learning, and taking actions to optimize behaviors automatically. 

14.1 Self-Aware Computing in the Angstrom Processor 

Srini Devadas, Henry Hoffman, George Kurian, Eric Lau, Jason E. Miller, 

Sabrina M. Neuman, Mahmut Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha 

P. Chandrakasan - Massachusetts Institute of Technology, Cambridge, MA 

Jim Holt - Massachusetts Institute of Technology, 

Freescale Semiconductor, Inc., Cambridge, MA 

Martina Maggio - Lund Univ., Lund, Sweden 

15 

Room: 304 

WHY MODEL? BECAUSE REALITY IS 

COMPLICATED ENOUGH! 

4:00 - 6:00pm 

Chair 

Ibrahim Elfadel - Masdar Institute of Science and Technology, 

Abu Dhabi, United Arab Emirates 

Models are an essential part of design. Good models capture the required 

details of the underlying physical system while abstracting away the unimportant 

behavior. They allow us to bridge between levels of representation, to account for 

new effects, and handle complexity, both in size as well as functionality, enabling 

reliable predictions of behavior and performance. The papers in this session 

address different aspects of the extremely important and challenging problem 

of developing compact and efficient models for current and future technologies 

ranging from thermal-mechanical stress in 3-D ICs, FINFETs, interconnect 

effects, circuit non-linearity, and delay sensitivity. 

15.1 Exploring Sub-20nm FinFET Design with 

Predictive Technology Models (4:00pm) 

Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline - ARM, Inc., Austin, TX 




14.2 The Case for Elastic Operating System Services in fos 

Lamia Youseff - Google, Inc., Fremont, WA 

Nathan Beckmann, Harshad Kasture, Charles Gruenwald, 

Anant Agarwal - Massachusetts Institute of Technology, Cambridge, MA 

David Wentzlaff - Princeton Univ., Princeton, NJ 

14.3 A Compiler and Runtime for Heterogeneous Computing 

Rodric Rabbah, Joshua Auerbach, David F. Bacon, 

Ioana Burcea, Perry Cheng, Stephen J. Fink, Sunil Shukla - 

IBM T.J. Watson Research Ctr., Yorktown Heights, NY 

14.4 The Helix Project: Overview and Directions 

Simone Campanoni, Glenn Holloway, Gu-Yeon Wei, 

David Brooks - Harvard Univ., Cambridge, MA 

Timothy Jones - Univ. of Cambridge, United Kingdom 

Room: 300 

Circuit and Interconnect Analysis 

15.2 Fast Nonlinear Model Order Reduction via Associated 

Transforms of High-Order Volterra Transfer Functions (4:15pm) 

Ngai Wong, Yang Zhang, Haotian Liu, Qing Wang, 

Neric Fong - The Univ. of Hong Kong, Hong Kong 

15.3 AMOR: An Efficient Aggregating Based Model Order Reduction 

Method for Many-Terminal Interconnect Circuits (4:30pm) 

Xuan Zeng, Yangfeng Su, Fan Yang - Fudan Univ., Shanghai, China 

15.4 BLAST: Efficient Computation of Nonlinear Delay Sensitivities 

in Electronic and Biological Networks using Barycentric 

Lagrange Enabled Transient Adjoint Analysis (4:45pm) 

Arie Meir, Jaijeet Roychowdhury - Univ. of California, Berkeley, CA 

15.5 DAE2FSM: Automatic Generation of Accurate Discrete-Time 

Logical Abstractions for Continuous-Time Circuit Dynamics (5:00pm) 

Karthik V. Aadithya, Jaijeet Roychowdhury - Univ. of California, Berkeley, CA 

15.6* Chip/Package Co-Analysis of Thermo-Mechanical 

Stress and Reliability in TSV-based 3-D ICs (5:15pm) 

Moongon Jung, Sung Kyu Lim - Georgia Institute of Technology, Atlanta, GA 

David Z. Pan - Univ. of Texas, Austin, TX 




16 

4:00 - 6:00pm 

16.1 Symbolic Model Checking on SystemC Designs (4:00pm) 

Chun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, 

Chung-Yang (Ric) Huang - National Taiwan Univ., Taipei, Taiwan 

17 

18 

16 

IS FORMAL VERIFICATION READY FOR 

THE SYSTEM LEVEL? 

Chair 

Erik Seligman - Intel Corp., Hillsboro, OR 

Formal verification has largely displaced simulation for Combinational Equivalence 

Checking. Formal technology for Sequential Equivalence Checking has made 

inroads for applications such as retiming and power optimization. This session 

explores the application of formal techniques at the system level. The papers 

cover topics such as verification of SystemC designs, formally relating abstract 

models to synthesized RTL, equivalence checking for behaviorally synthesized 

pipelines, and a novel application in the domain of network security. The session 

also features a perspective paper on the interplay of induction and deduction in 

formal verification. 

4:00 - 6:00pm 

NOCS NEXT TOP MODEL: 

FROM SYSTEM-LEVEL TO PROTOTYPE 

Chair 

Fabien Clermidy - CEA-LETI, Grenoble, France 

What do “Attackboards,” “Aging,” and “Wide-I/O” have in common? They represent 

some of the key new contributions highlighted in recent Network-on-Chip (NoC) 

research. This session is an exciting mix of innovative and more accurate methods 

for modeling NoC designs, new architectures for NoCs, and fabricated prototype 

chips at relevant technology nodes. All of these provide tremendous insights into 

future NoCs. This session also has a significant component of 3-D NoC design 

and prototyping. 

17.1 Cost-Efficient Buffer Sizing in Shared-Memory 3-D 

MPSoCs using Wide I/O Interfaces (4:00pm) 

Sahar Foroutan, Frédéric Pétrot - TIMA Laboratory, 

Grenoble Institute of Technology, Grenoble, France 

Abbas Sheibanyrad - TIMA Laboratory/CNRS, Grenoble, France 

17.2 Attackboard: A Novel Dependency-Aware Traffic 

Generator for Exploring NoC Design Space (4:15pm) 

Yoshi Shih-Chieh Huang, Yu-Chi Chang, Tsung-Chan Tsai, Yuan-Ying 

Chang, Chung-Ta King - National Tsing Hua Univ., Hsinchu, Taiwan 

4:00 - 6:00pm 

TIMING ANALYSIS AND SOFTWARE-CONTROLLED 

MEMORY: ARE WE SAFE? 

Chair 

Frank Slomka - Univ. of Ulm, Germany 

The need to consider precise timing behavior is one of the key requirements 

of embedded systems integrated into a physical environment. However, the 

generation of tight and safe timing guarantees is very difficult. A second difficulty 

in the design of embedded systems results from the need to use multiple, 

heterogeneous memories. The corresponding memory architectures require 

explicit software control. The papers in this session provide novel contributions in 

worst-case execution-time estimation and software memory management. 

18.1* WCET-Centric Partial Instruction Cache Locking (4:00pm) 

Huping Ding, Tulika Mitra - National Univ. of Singapore, Singapore 

Yun Liang - Advanced Digital Sciences Center, Singapore 

18.2 Worst-Case Execution Time Analysis for 

Parallel Run-Time Monitoring (4:15pm) 

Daniel Lo, G. Edward Suh - Cornell Univ., Ithaca, NY 

Room: 306 

Room: 308 

Room: 310 


16.2 System Verification of Concurrent RTL Modules by 

Compositional Path Predicate Abstraction (4:15pm) 

Joakim Urdahl, Dominik A. Stoffel, Markus Wedler, 

Wolfgang Kunz - Univ. of Kaiserslautern, Germany 

16.3 Equivalence Checking for Behaviorally Synthesized Pipelines (4:30pm) 

Kecheng Hao, Fei Xie - Portland State Univ., Portland, OR 

Sandip Ray - Univ. of Texas, Austin, TX 

16.4 Proving Correctness of Regular Expression Accelerators (4:45pm) 

Mitra Purandare, Kubilay Atasu, Christoph Hagleitner 

- IBM Research - Zurich, Switzerland 

16.5 Sciduction: Combining Induction, Deduction, and 

Structure for Verification and Synthesis (5:00pm) 

Sanjit A. Seshia - Univ. of California, Berkeley, CA 

System Level Design and Communication 

17.3 Towards Graceful Aging Degradation in NoCs 

Through an Adaptive Routing Algorithum (4:30pm) 

Koushik Chakraborty, Kshitij Bhardwaj, 

Sanghamitra Roy - Utah State Univ., Logan, UT 

17.4* Explicit Modeling of Control and Data for 

Improved NoC Router Estimation (4:45pm) 

Siddhartha Nath, Andrew B. Kahng, Bill Lin - 

Univ. of California at San Diego, La Jolla, CA 

17.5 Approaching the Theoretical Limits of a Mesh NoC 

with a 16-Node Chip Prototype in 45nm SOI (5:00pm) 

Sunghyun Park, Tushar Krishna, Chia-Hsin O. Chen, 

Bhavya Daya, Li-Shiuan Peh, Anantha P. Chandrakasan - 

Massachusetts Institute of Technology, Cambridge, MA 

17.6 High Radix Self-Arbitrating Switch Fabric with Multiple 

Arbitration Schemes and Quality of Service (5:15pm) 

Sudhir K. Satpathy, Reetuparna Das, Ronald Dreslinski, Trevor Mudge, 

Dennis Sylvester, David Blaauw - Univ. of Michigan, Ann Arbor, MI 

Embedded Software 

18.3 Conforming the Runtime Inputs for Hard Real- 

Time Embedded Systems (4:30pm) 

Kai Huang, Gang Chen, Christian Buckl - fortiss GmbH, Munich, Germany 

Alois Knoll - Technische Univ. München, Germany 

18.4 STM Concurrency Control for Embedded Real- 

Time Software with Tighter Time Bounds (4:45pm) 

Mohammed T. El-Shambakey, Binoy Ravindran - 

Virginia Polytechnic Institute and State Univ., Blacksburg, VA 

18.5 HaVOC: A Hybrid-Memory-Aware Virtualization Layer for On- 

Chip Distributed ScratchPad and Non-Volatile Memories (5:00pm) 

Luis Angel D. Bathen, Nikil Dutt - Univ. of California, Irvine, CA 

18.6 Age-Based PCM Wear Leveling with Nearly Zero Search Cost (5:15pm) 

Pi-Cheng Hsiu - Academia Sinica, Taipei, Taiwan 

Chi-Hao Chen, Chia-Lin Yang - National Taiwan Univ., Taipei, Taiwan 

Tei-Wei Kuo - National Taiwan Univ., Academia Sinica, Taipei, Taiwan 

Cheng-Yuan Michael Wang - Macronix International Co., Ltd., Hsinchu, Taiwan 

www.DAC.com Best Paper Nominees are Denoted in Orange. Perspective Papers are Denoted in Dark Gray.


WEDNESDAY, JUNE 6 

19 

9:00 - 10:30am 

20 

SPECIAL SESSION: ROUTING-DRIVEN DESIGN CLOSURE 

9:00 - 10:30am Room: 304 

Chair 

Shankar Krishnamoorthy - Mentor Graphics Corp., San Jose, CA 

With each subsequent technology node, routing complexity increases exponentially 

to handle the explosion of design rules and routing constraints. Metal layer stacks 

are becoming increasingly complex, with varying degrees of wire widths and 

interconnect parasitics becoming the norm. This session discusses design closure 

from a routing-centric perspective from three angles: core routing technology, 

guiding physical design to create a friendlier hand-off to routing, and reducing 

routing complexity by changing the underlying methodology. 

21 

PANEL: HIGH-LEVEL SYNTHESIS PRODUCTION 

DEPLOYMENT: ARE WE READY? 

Chair 

Clem Meas - quickSTART Consulting, Boulder, CO 

Speakers: 

Eli Singerman - Intel Corp., Haifa, Israel 

Kazutoshi Wakabayashi - NEC Corp., Tokyo, Japan 

Mark Johnstone - Freescale Semiconductor, Inc., Austin, TX 

Mark Warren - Cadence Design Systems, Inc., San Jose, CA 

Vinod Kathail - Xilinx, Inc., San Jose, CA 

Andres Takach - Calypto Design Systems, Inc., Wilsonville, OR 

9:00 - 10:30am 

20.1 Algorithms and Data Structures for Fast and Good VLSI Routing 

Dirk Mueller, Michael Gester, Tim Nieberg, Christian Panten, 

Christian Schulte, Jens Vygen - Univ. of Bonn, Germany 

20.2 Guiding a Physical Design Closure System to Produce 

Easier-to-Route Designs with More Predictable Timing 

Zhuo Li, Gi-Joon Nam, Cliff Sze - IBM Research - Austin, TX 

Charles Alpert - IBM Corp., Cedar Park, TX 

Natarajan Viswanathan, Nancy Zhou - 

IBM Systems and Technology Group, Austin, TX 

20.3 Rule Agnostic Routing by Using Design Fabrics 

Gyuszi Suto - Intel Corp., Hillsboro, OR 

STORING, COMPUTING, AND STORING WHILE COMPUTING: 

THE NEW FACE OF NON-VOLATILITY IN SYSTEMS 

Chair 

Charles Augustine - Intel Corp., Hillsboro, OR 

As energy-efficient designs leverage non-volatility in logic and memory, serious 

challenges emerge in design and design automation. How can nanomagnets be 

efficiently used in logic? What new applications are driven using these disruptive 

technologies? This session is intended to provide insights into design philosophies 

using nanomagnetic and resistive technologies. The four papers encompass a 

wide spectrum of topics from energy optimization in spin-transfer-torque memories 

to efficient neural algorithms mapped onto RRAM arrays. 

21.1 Making Non-Volatile Nanomagnet Logic Non-Volatile (9:00am) 

Aaron Dingler, Steve J. Kurtz, Michael T. Niemier, Xiaobo Sharon Hu, 

Gyorgy Csaba, Joseph Nahas, Wolfgang Porod, Gary H. Bernstein, 

Peng Li, Vijay Karthik Sankar - Univ. of Notre Dame, Notre Dame, IN 

Room: 305 

Room: 300 

High-Level and Logic Synthesis 

High-level synthesis has historically over-promised and under-delivered, but that is 

all about to change. Or, is it? Are we ready to climb the ladder up to the next level 

of design abstraction? Watch our panelists debate whether today’s technology 

can handle system validation, IP integration and optimization, power/performance 

constraints, and design verification challenges. Find out if we are about to connect 

the world of embedded software development to hardware design. 

Physical Design 


21.2 mLogic: Ultra-Low Voltage Non-Volatile Logic 

Circuits Using STT-MTJ Devices (9:15am) 

Daniel Morris, David M. Bromberg, Jian-Gang (Jimmy) Zhu, 

Larry Pileggi - Carnegie Mellon Univ., Pittsburgh, PA 

21.3 Future Cache Design using STT MRAMs for Improved Energy 

Efficiency: Devices, Circuits, and Architecture (9:30am) 

Sang Phill Park, Sumeet K. Gupta, Niladri N. Mojumder, 

Anand Raghunathan, Kaushik Roy - Purdue Univ., West Lafayette, IN 

21.4 Hardware Realization of BSB Recall Function 

with Memristor Crossbar Arrays (9:45am) 

Miao Hu, Hai Li - Polytechnic Institute of New York Univ., Brooklyn, NY 

Qing Wu, Garrett S. Rose - Air Force Research Lab, Rome, NY 




22 

9:00 - 10:30am 

22.1 A Methodology for Energy-Quality Tradeoff 

Using Imprecise Hardware (9:00am) 

Jiawei Huang, John Lach, Gabriel Robins - Univ. of Virginia, Charlottesville, VA 

22.2 On the Exploitation of the Inherent Error Resilience of 

Wireless Systems under Unreliable Silicon (9:15am) 

Georgios Karakonstantis, Andreas Burg - 


Christoph Roth, Christian Benkeser - Eidgenössische 

Technische Hochschule Zürich, Zürich, Switzerland 

23 

24 

18 

YOU CAN COUNT ON ME: WHY IT’S OK TO BE 

IMPRECISE OR UNRELIABLE 

Chair 

Qinru Qiu - Syracuse Univ., Syracuse, NY 

For some applications, it is sometimes worth giving up a limited amount of precision 

or reliability if that leads to significant power savings. Similarly, being able to operate 

“off the grid” means one needs to give up the certainty of traditional power sources 

to enable power harvesting opportunities. The papers in this session illustrate the 

trade-offs inherent in operating in extreme low-power regimes. 

9:00 - 10:30am 

OPTIMIZATION TO THE RESCUE OF ANALOG 

Chair 

Trent McConaghy - Solido Design Automation, Inc., Saskatoon, CA 

Today, analog circuit design is a daunting task even for seasoned designers, 

involving careful sizing of transistors, characterization of RF/microwave elements, 

and physical placement/routing with extra constraints, all under ever-worsening 

variabilities and uncertainties. The papers in this session demonstrate how 

optimization techniques can be leveraged to address these analog design 

challenges. Interestingly, the papers employ rather non-traditional approaches for 

analog, such as Gaussian process surrogate model from machine learning, robust 

optimization with non-fixed uncertainty budget, discrete grid-based optimization, 

and integer linear programming. 

9:00 - 10:30am 

XTERMINATING BUGS 

Chair 

Sharad Kumar - Freescale Semiconductor, Inc., Noida, India 

Post-silicon debug impacts production cost and test times, calling for innovative 

work in on-line error detection. The papers in this session cover issues related to 

optimizing testing times and data volumes, detecting difficult bugs, and performing 

concurrent error detection in AES cryptographic circuitry. 

24.1 X-Tracer: A Reconfigurable X-Tolerant Trace 

Compressor for Silicon Debug (9:00am) 

Feng Yuan, Xiao Liu, Qiang Xu - 

The Chinese Univ. of Hong Kong, Shatin, Hong Kong 

Room: 306 

Room: 308 

Room: 310 

22.3 Near-Optimal, Dynamic Module Reconfiguration in a 

Photovoltaic System to Combat Partial Shading Effects (9:30am) 

Xue Lin, Yanzhi Wang, Siyu Yue, Massoud Pedram - 

Univ. of Southern California, Los Angeles, CA 

Donghwa Shin, Naehyuck Chang - Seoul National 

Univ., Seoul, Republic of Korea 

22.4 Networked Architecture for Hybrid Electrical 

Energy Storage Systems (9:45am) 

Younghyun Kim, Sangyoung Park, Naehyuck Chang - 

Seoul National Univ., Seoul, Republic of Korea 

Yanzhi Wang, Qing Xie, Massoud Pedram - 


23.1 A New Uncertainty Budgeting Based Method for 

Robust Analog/Mixed-Signal Design (9:00am) 

Janet Roveda - Univ. of Arizona, Tucson, AZ 

Jin Sun - Orora Design Technologies, Inc., Issaquah, WA 

Priyank Gupta - Cirrus Logic, Inc., Tucson, AZ 

23.2 Variability-Aware, Discrete Optimization for Analog Circuits (9:15am) 

Seobin Jung, Yunju Choi, Jaeha Kim - 

Seoul National Univ., Seoul, Republic of Korea 

23.3 Efficient Multi-Objective Synthesis for Microwave Components 

Based on Computational Intelligence Techniques (9:30am) 

Georges Gielen, Bo Liu, Hadi Aliakbarian, Soheil Radiom, 

Guy A. E. Vandenbosch - Katholieke Univ. Leuven, Belgium 

23.4 Non-Uniform Multilevel Analog Routing 

with Matching Constraints (9:45am) 

Hung-Chih Ou, Hsing-Chih Chang Chien, 

Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan 

24.2 Quick Detection of Difficult Bugs for Effective 

Post-Silicon Validation (9:15am) 

David H. Lin, Ted Hong, Farzan Fallah, 


Nagib Hakim - Intel Corp., Santa Clara, CA 

24.3 Test Data Volume Optimization for Diagnosis (9:30am) 

Hongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, 

Ibrahima Komara, Shawn Blanton - Carnegie Mellon Univ., Pittsburgh, PA 

24.4 Invariance-Based Concurrent Error Detection for 

Advanced Encryption Standard (9:45am) 

Xiaofei Guo, Ramesh Karri - 

Polytechnic Institute of New York Univ., Brooklyn, NY 



Analog/Mixed-Signal/RF Design 

Verification and Test



25 

1:30 - 3:00pm 

26 

1:30 - 3:00pm 

Chair 

Yiran Chen - Univ. of Pittsburgh, PA 

27 

SPECIAL SESSION: BRAIN-INSPIRED AUTONOMOUS 

COMPUTING AND MODELING 

A human brain weighs ~1.5kg, and is made up of 100 billion neurons connected 

via an incredibly dense and complex neuron network. The network contains 4km 

of wire in every cubic millimeter, offering >100-million MIPS computing capability 

and



28 

1:30 - 3:00pm 

29 

The need for ever-shorter turnaround design times calls for advancements in 

all aspects of system-level design, including formal modeling, optimization and 

synthesis. Memory hierarchy design and optimization is a key determinant of 

system-level performance and power consumption. This session presents a novel 

model of computation (MoC), synthesis and mapping approaches, as well as an 

innovative micro-architecture for system-level memory hierarchy design. The last 

presentation, a perspective, is a reality check for our EDA community: are we 

on track for embedded system and software development to effectively serve our 

society? 

29.1 Static Dataflow with Access Patterns: 

Semantics and Analysis (1:30pm) 

Arkadeb Ghosal, Rhishikesh S. Limaye, Kaushik Ravindran, 

Ankita Prasad, Guoqiang Wang, Trung N. Tran, Hugo A. 

Andrade - National Instruments Corp., Berkeley, CA 

Stavros Tripakis - Univ. of California, Berkeley, CA 

30 

20 

STAYING COOL: 

MODELING THERMAL EFFECTS IN 3-D AND MULTICORE 

Chair 

Dhireesha Kudithipudi - Rochester Institute of Technology, Rochester, NY 

Power consumption and high junction temperatures are major challenges 

towards improving the performance of future computing devices. To address 

these challenges, new effective techniques are needed for design-time modeling 

and for runtime management. This session proposes new design techniques, 

such as thermal-sensor allocation and power-modeling validation. For runtime 

management, new techniques are proposed to improve the spatial thermal 

estimation from sensor measurements and for maximizing the performance of 3-D 

processors under thermal and power constraints. 

28.1 PowerField: A Transient Temperature-to-Power Technique 

based on Markov Random Field Theory (1:30pm) 

Seungwook Paek, Wongyu Shin, Jaehyeong Sim, Lee- 

Sup Kim - KAIST, Daejeon, Republic of Korea 

Seok-Hwan Moon - Electronics and Telecommunications 

Research Institute, Daejeon, Republic of Korea 

1:30 - 3:00pm 

SOS: SPECIFICATION, OPTIMIZATION, AND SYNTHESIS 

IN SYSTEM-LEVEL DESIGN 

Chair 

Brett Meyer - McGill Univ., Montréal, QC, Canada 

1:30 - 3:00pm 

FUTURE OF IC RELIABILITY 

Chair 

Alesandro Pinto - United Technologies Research Center, Berkeley, CA 

Reliable computation of embedded devices mandates hardware to be trustworthy 

and protected from various issues: counterfeit and confidentiality attacks, 

performance failures, and manufacturing defects. The session includes current 

innovation techniques that address the above-mentioned issues. The papers 

in the session cover various advancements made using formal and statistical 

analysis: fingerprinting ICs, dependable computation using ultra-risc processors, 

obfuscating data for computation in un-trusted cloud, and performance verification. 

30.1 A Hybrid Approach to Cyber-Physical Systems Verification (1:30pm) 

Pratyush Kumar, Kai Lampka, Lothar Thiele - Eidgenössische 

Technische Hochschule Zürich, Zürich, Switzerland 

Dip Goswami, Samarjit Chakraborty - Technische Univ. München, Germany 

Anuradha Annaswamy - Massachusetts Institute of Technology, Boston, MA 

Room: 306 

Room: 308 

Room: 310 


28.2 EigenMaps: Algorithms for Optimal Thermal Maps Extraction 

and Sensor Placement on Multicore Processors (1:45pm) 

Juri Ranieri, Alessandro Vincenzi, Amina Chebira, David Atienza, Martin 

Vetterli - Ecole Polytechnique Fédérale de Lausanne, Switzerland 

28.3 An Information-Theoretic Framework for Optimal Temperature 

Sensor Allocation and Full-Chip Thermal Monitoring (2:00pm) 

Xin Li, Huapeng Zhou, Shi-Chune Yao - Carnegie Mellon Univ., Pittsburgh, PA 

Chen-Yong Cher, Eren Kursun, Haifeng Qian - IBM T.J. 

Watson Research Ctr., Yorktown Heights, NY 

28.4 Optimizing Energy Efficiency of 3-D Multicore Systems with 

Stacked DRAM under Power and Thermal Constraints (2:15pm) 

Jie Meng, Katsutoshi Kawakami, Ayse K. Coskun - Boston Univ., Boston, MA 


29.2 Executing Synchronous Dataflow Graphs on a 

SPM-Based Multicore Architecture (1:45pm) 

Junchul Choi, Soonhoi Ha - Seoul National Univ., Seoul, Republic of Korea 

Hyunok Oh - Hanyang Univ., Seoul, Republic of Korea 

Sungchan Kim - Chonbuk National Univ., Jeonju, Republic of Korea 

29.3 System-Level Synthesis of Memory Architecture for 

Stream Processing Sub-Systems of a MPSoC (2:00pm) 

Glenn Leary, Weijia Che, Karam S. Chatha - Arizona State Univ., Tempe, AZ 

29.4 Courteous Cache Sharing: Being Nice to 

Others in Capacity Management (2:15pm) 

Akbar Sharifi, Shekhar Srikantaiah, Mahmut Kandemir, Mary 

Jane Irwin - Pennsylvania State Univ., University Park, PA 

29.5 Embedded Systems - The Neural Backbone of Society (2:30pm) 

Rolf Ernst - Technische Univ. Braunschweig, Germany 


30.2 Reliable Computing with Ultra-Reduced 

Instruction Set Co-Processors (1:45pm) 

Hiren D. Patel, Aravindkumar Rajendiran, Sundaram 

Ananthanarayanan, Mahesh V. Tripunitara, Siddharth 

Garg - Univ. of Waterloo, Waterloo, ON, Canada 

30.3 Identification of Recovered ICs using Fingerprints 

from a Light-Weight On-Chip Sensor (2:00pm) 

Xuehui Zhang, Nicholas Tuzzio, Mohammad 

Tehranipoor - Univ. of Connecticut, Storrs, CT 

30.4 Confidentiality Preserving Integer Programming 

for Global Routing (2:15pm) 

Azadeh Davoodi, Hamid Shojaei, Parameswaran 

Ramanathan - Univ. of Wisconsin, Madison, WI 




31 

4:00 - 6:00pm 

32 

4:00 - 6:00pm 

33 

SPECIAL SESSION: BREAKING OUT OF EDA: HOW TO 

APPLY EDA TECHNIQUES TO BROADER APPLICATIONS 

Chair 

Jason Cong - Univ. of California, Los Angeles, CA 

Throughout its history, myriads of innovations in EDA (Electronic Design 

Automation) have enabled high performance semiconductor products with leading 

edge technology. Lately we have observed several research activities where EDA 

innovations have been applied to broader applications with complex nature and 

the large scale of data sets. The session provides some tangible results of these 

multi-disciplinary works where non-traditional EDA problems directly benefit from 

the innovation of EDA research. The examples of non-EDA applications vary from 

bio-medical applications to smart water to human computing. 

4:00 - 6:00pm 

PANEL: HOT APPS, COOL PHONES: 

POWER-EFFICIENT MOBILE DESIGN 

Chair 

Ed Sperling - Low Power Engineering, San Jose, CA 

Speakers: 

Jan Rabaey - Univ. of California, Berkeley, CA 

Emily Shriver - Intel Corp., Hillsboro, OR 

Alan Gibbons - Synopsys, Inc., Mountain View, CA 

Narendra Konda - NVIDIA Corp., Santa Clara, CA 

Barry Pangrle - Mentor Graphics Corp., Fremont, CA 

David Greenhill - Texas Instruments, Inc., Dallas, TX 

THE RIGHT PLACEMENT AT THE RIGHT TIMING 

Chair 

Saurabh Adya - Magma Design Automation, Inc., Sunnyvale, CA 

Great chips need great placements; without this, little else matters. The papers in 

this session push the state of the art forward, leveraging stacked TSVs to improve 

cooling, and better numerical techniques for analytic placement. Underlying 

structure and regularity is deciphered, giving new ways to tame large designs. 

The session concludes with new benchmarks and metrics for placement, and the 

results of the 2012 DAC placement contest, where teams from around the world 

compete head-to-head for the title of Best Placer Ever. 

33.1 Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement (4:00pm) 

Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim - 

Georgia Institute of Technology, Atlanta, GA 

33.2 ComPLx: A Competitive Primal-Dual Lagrange 

Optimization for Global Placement (4:15pm) 

Myung-Chul Kim, Igor L. Markov - Univ. of Michigan, Ann Arbor, MI 

Room: 305 Low-Power Design and Power Analysis 

Room: 304 

Room: 300 

Recently, we have focused on techniques for low-power hardware design. But it is 

not enough. With the advent of app-driven mobile devices, battery life is paramount. 

We must now consider the impact of software on power consumption, and the EDA 

industry must look to providing environments that enable modeling, measuring and 

optimizing the impact of hardware and software interaction on power consumption 

at the system level. Our panelists explore the technical challenges and potential 

solutions for designing and verifying these complex power efficient systems. 


32.1 Design Tools for Artificial Nervous Systems 

Lou Scheffer - Howard Hughes Medical Institute, Chevy Chase, MD 

32.2 Dynamic River Network Simulation at Large Scale 

Frank Liu - IBM Research - Austin, TX 

Ben R. Hodges - Univ. of Texas, Austin, TX 

32.3 Humans for EDA and EDA for Humans 

Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI 

32.4 Application of Logic Synthesis to the 

Understanding and Cure of Genetic Diseases 

Sunil P. Khatri, Pey-Chang Kent Lin - Texas A&M Univ., College Station, TX 


33.3 PADE: A High-Performance Placer with Automatic Datapath Extraction 

and Evaluation through High-Dimensional Data Learning (4:30pm) 

Samuel Ward, Duo Ding, David Z. Pan - Univ. of Texas, Austin, TX 

33.4 Structure-Aware Placement for Datapath 

Intensive Circuit Designs (4:45pm) 

Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang - 

National Taiwan Univ., Taipei, Taiwan 

33.5 GLARE: Global and Local Wiring Aware Routability Evaluation (5:00pm) 

Yaoguang Wei, Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN 

Cliff Sze, Zhuo Li, Charles J. Alpert - IBM Research - Austin, TX 

Natarajan Viswanathan, Lakshmi Reddy, Andrew D. Huber, Gustavo E. Tellez, 

Douglas Keller - IBM Systems and Technology Group, Hopewell Jct., NY 

33.6 The DAC 2012 Routability-Driven Placement 

Contest and Benchmark Suite (5:15pm) 

Natarajan Viswanathan, Charles J. Alpert, Cliff Sze, 

Zhuo Li, Yaoguang Wei - IBM Corp., Austin, TX 




34 

4:00 - 6:00pm 

35 

22 

GLOBAL VIEWS OF SYNTHESIS: 

BROADENING THE SCOPE 

Chair 

Herman Schmit - Altera Corp., Santa Clara, CA 

Researchers are starting to investigate exciting avenues linking traditional synthesis 

to the global design environment. We present a selection of papers exploring 

several new directions. Static logic analysis can be used to simultaneously achieve 

both portable and efficient module interfaces, while logic synthesis is redirected to 

support approximate computing, and a high-level analysis presents new insights 

into the scalability of multi-function designs. For the early stages of the design 

flow, we present a method for RTL-based NBTI aging prediction, while for later in 

the flow we offer a new approach to post-mapping optimization and a new form of 

timing ECO optimization. 

34.1 Removing Overhead from High-Level Interfaces (4:00pm) 

Kyle Kelley, Megan Wachs, John P. Stevenson, 

Stephen Richardson, Mark Horowitz - Stanford Univ., Stanford, CA 

34.2 On the Asymptotic Costs of Multiplexer- 

Based Reconfigurability (4:15pm) 

Johnathan A. York, Derek Chiou - Univ. of Texas, Austin, TX 

4:00 - 6:00pm 

ADAPTIVE COMPUTING: WHEN, WHERE, WHY, HOW? 

Chair 

Philip Brisk - Univ. of California, Riverside, CA 

Embedded systems are increasingly expected to support a dynamic and diverse 

application landscape under tight power-performance constraints, thus mandating 

runtime adaptivity. The need for adaptivity is multifarious: seamless hiding of 

variation induced errors, trading accuracy versus energy through approximate 

arithmetic, trading power versus performance via hybrid on-chip network, 

offloading computation to a rich set of accelerators for higher efficiency, satisfying 

QoS through adaptive resource management. This session addresses adaptivity 

at different layers of an embedded computing system starting from the silicon all 

the way to the system-level. 

35.1 Accuracy-Configurable Adder for Approximate 

Arithmetic Designs (4:00pm) 

Seokhyeong Kang, Andrew B. Kahng - 

Univ. of California at San Diego, La Jolla, CA 

35.2* Recovery-Based Design for Variation-Tolerant SoCs (4:15pm) 

Vivek J. Kozhikkottu, Anand Raghunathan - Purdue Univ., West Lafayette, IN 

Sujit Dey - Univ. of California at San Diego, La Jolla, CA 

Room: 306 

Room: 308 

34.3 SALSA: Systematic Logic Synthesis of Approximate Circuits (4:30pm) 

Swagath Venkataramani, Amit Sabne, Vivek Kozhikkottu, 

Kaushik Roy, Anand Raghunathan - Purdue Univ., West Lafayette, IN 

34.4 Timing ECO Optimization Using Metal- 

Configurable Gate-Array Spare Cells (4:45pm) 

Iris Hui-Ru Jiang - National Chiao Tung Univ., Hsinchu, Taiwan, 

Hua-Yu Chang, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan 

34.5 Early Prediction of NBTI Effects Using RTL 

Source Code Analysis (5:00pm) 

Jayanand Asok Kumar, Heesoo Kim, Shobha Vasudevan 

- Univ. of Illinois at Urbana-Champaign, Urbana, IL 

Kenneth M. Butler - Texas Instruments, Inc., Dallas, TX 

34.6 Generalized SAT-Sweeping for Post-Mapping Optimization (5:15pm) 

Tobias Welp - Univ. of California, Berkeley, CA 

Smita Krishnaswamy - Columbia Univ., New York, NY 

Andreas Kuehlmann - Coverity, Inc., San Francisco, CA 

35.3 A Hybrid NoC Design for Cache Coherence 

Optimization for Chip Multiprocessors (4:30pm) 

Hui Zhao, Ohyoung Jang, Wei Ding, Mahmut Kandemir, 

Mary Jane Irwin - Pennsylvania State Univ., University Park, PA 

Yuanrui Zhang - Pennsylvania State Univ., University Park, PA 

35.4 Architecture Support for Accelerator-Rich CMPs (4:45pm) 

Mohammad Ali Ghodrat, Jason Cong, Michael Gill, Beayna 

Grigorian, Glenn Reinman - Univ. of California, Los Angeles, CA 

35.5 A QoS-Aware Memory Controller for Dynamically Balancing 

GPU and CPU Bandwidth Use in an MPSoC (5:00pm) 

Min Kyu Jeong, Mattan Erez - Univ. of Texas, Austin, TX 

Chander Sudanthi, Nigel Paver - ARM, Inc., Austin, TX 

35.6 Metronome: Operating System-Level Performance 

Management via Self-Adaptive Computing (5:15pm) 

Filippo Sironi, Davide Basilio Bartolini, Fabio Cancaré, Donatella 

Sciuto, Marco D. Santambrogio - Politecnico di Milano, Milano, Italy 

Simone Campanoni - Harvard Univ., Cambridge, MA 

Henry Hoffmann - Massachusetts Institute of Technology, Cambridge, MA 



Embedded Architecture & Platforms



36 

4:00 - 6:00pm 

Chair 

Yiran Chen - Univ. of Pittsburgh, PA 

YIN AND YANG OF MEMORIES: 

THE POWER-PERFORMANCE TRADE-OFF 

Emerging memory technologies, along with their conventional counterparts (SRAM 

and DRAM,) present a plethora of options to design future memory hierarchies. A 

critical question to address is how to pick the right technologies and where to 

place them in the storage hierarchy. Answering this question demands a thorough 

exploration of power-performance tradeoffs. The papers in this session address 

different aspects of this problem, and explore a variety of solutions ranging from 

DRAM/PRAM based heterogeneous memory design, to multi-level STTRAMs, to 

power/performance tradeoffs in video memories. The session not only highlights 

efforts on these fronts and reveals interesting power-performance tradeoffs, but 

also highlights possible future directions. 

36.1 Adaptive Power Management of On-Chip Video 

Memory for Multiview Video Coding (4:00pm) 

Muhammad Shafique, Bruno Zatt, Joerg Henkel - 

Karlsruhe Institute of Technology, Karlsruhe, Germany 

Fábio Leandro Walter, Sergio Bampi - 

Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil 

36.2 Heterogeneous Multi-Channel: Fine-Grained DRAM Control 

for Both System Performance and Power Efficiency (4:15pm) 

Guangfei Zhang, Xinke Chen, Peng Li - 

Institute of Computing Tech., Beijing, China 

Huandong Wang - Loongson Technology Corp., Ltd., Beijing, China 

Shuai Huang - Loongson Technology Corp., Ltd., Beijing, China 

Room: 310 

Embedded Architecture & Platforms 

36.3 Joint Management of RAM and Flash Memory 

with Access Pattern Considerations (4:30pm) 

Po-Chun Huang - National Taiwan Univ., Taipei, Taiwan 

Yuan-Hao Chang - Academia Sinica, Taipei, Taiwan 

Tei-Wei Kuo - National Taiwan Univ., Academia Sinica, Taipei, Taiwan 

36.4 Hybrid DRAM/PRAM-Based Main Memory 

for Single-Chip CPU/GPU (4:45pm) 

Dongki Kim, Sungkwang Lee, Sungjoo Yoo, Sunggu Lee - 

Pohang Univ. of Science and Technology, Pohang, Republic of Korea 

Jaewoong Chung, Dong Hyuk Woo - Intel Corp., Santa Clara, CA 

DaeHyun Kim - Magma Design Automation, Inc., San Jose, CA 

36.5 Write Performance Improvement by Hiding R Drift 

Latency in Phase-Change RAM (5:00pm) 

Youngsik Kim, Sungjoo Yoo, Sunggu Lee - 

Pohang Univ. of Science and Technology, Pohang, Republic of Korea 

36.6 Constructing Large and Fast Multi-Level Cell STT-MRAM 

Based Cache for Embedded Processors (5:15pm) 

Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang - Univ. of Pittsburgh, PA 



THURSDAY, JUNE 7 

37 

9:00 - 10:30am 

38 

39 SIMULATION-BASED VERIFICATION: 

NEW WAYS TO HARNESS THE WORKHORSE 

9:00 - 10:30am Room: 300 Verification and Test 

Chair 

Kerstin Eder - Univ. of Bristol, United Kingdom 

As the complexity of designs grows and time-to-market shrinks, new (and 

old) verification problems arise. Simulation-based verification continues to be the 

main workhorse for dealing with these problems. This session introduces novel 

applications of simulation-based and hybrid techniques to address many of these 

problems including: improving simulation accuracy by eliminating extraneous don’t 

cares in 3-valued simulation, applying SAT solvers to assist in bug localization, 

extracting functionality from simulation runs, and adding checking capabilities to 

emulation and acceleration platforms. 

39.1 Improving Gate-Level Simulation Accuracy 

when Unknowns Exist (9:00am) 

Kai-hui Chang, Chris Browy - Avery Design Systems, Inc., Andover, MA 

24 

PANEL: IS 3-D READY FOR THE NEXT LEVEL? 

Chair 

Sachin Sapatnekar - Univ. of Minnesota, Minneapolis, MN 

Speakers: 

Subramanian S. Iyer - IBM Corp., Fishkill, NY 

Shekhar Borkar - Intel Corp., Hillsboro, OR 

A.J. Incorvaia - Cadence Design Systems, Inc., Chelmsford, MA 

Liam Madden - Xilinx, Inc., San Jose, CA 

Suk Lee - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA 

9:00 - 10:30am 

SPECIAL SESSION: 

PROBABILISTIC EMBEDDED COMPUTING 

Chair 

Vincent Mooney - Georgia Institute of Technology, Atlanta, GA 

Probabilistic Embedded Computing (PEC) provides dramatic, low-cost 

performance boosts at the expense of guaranteed correctness and may even 

help overcome fundamental barriers that can otherwise not be resolved. Giving 

up guaranteed correctness opens up a vast challenge and solution space on all 

levels of embedded computing. The session presents the state of the art in PECrelated 

work involving hardware, hardware-software interfaces, and software. 

38.1 Incorrect Systems: It’s not the Problem, It’s the Solution 

Christoph Kirsch, Hannes Payer - Univ. of Salzburg, Austria 

Room: 305 

Room: 304 


Early promises of 3-D IC integration - memory bandwidth and power (wide-IO 

memory stacks in consumer products), or yield and cost (FPGA die integrated 

with a silicon interposer) - have now been realized in volume production. What 

have the design and supply chains learned from the experience of enabling these 

applications? What will be the next killer applications for 3-D, how will these be 

enabled across the semiconductor industry, and what key technologies must the 

EDA industry contribute? Come hear the experts discuss how to “take 3-D to the 

next level.” 


38.2 On Software Design for Stochastic Processors 

Rakesh Kumar, Joseph Sloan, John Sartori - 

Univ. of Illinois at Urbana-Champaign, Urbana, IL 

38.3 What to Do About the End of Moore’s Law, Probably! 

Krishna Palem - Nanyang Technological Univ., Rice Univ., Singapore 

Avinash Lingamneni - Rice Univ., Houston, TX 

38.4 Obtaining and Reasoning About Good Enough Software 

Martin Rinard - Massachusetts Institute of Technology, Boston, MA 

39.2 Automated Feature Localization for Hardware 

Designs Using Coverage Metrics (9:15am) 

Jan Malburg, Alexander Finder - Univ. of Bremen, Germany 

Goerschwin Fey - German Aerospace Center, Bremen, Germany 

39.3 Path Directed Abstraction and Refinement in 

SAT-Based Design Debugging (9:30am) 

Brian Keng, Andreas Veneris - Univ. of Toronto, Toronto, ON, Canada 

39.4 Checking Architectural Outputs Instruction-by- 

Instruction on Acceleration Platforms (9:45am) 

Debapriya Chatterjee, Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI 

Anatoly Koyfman, Ronny Morad, Avi Ziv - IBM Haifa Research Lab., Haifa, Israel 

www.DAC.com Best Paper Nominees are Denoted in Orange



40 

9:00 - 10:30am 

41 

ULTRA-LOW POWER USING SUBTHRESHOLD AND 

NEARTHRESHOLD OPERATION 

Chair 

Mahadev Nemani - Intel Corp., Hillsboro, OR 

Ultra-low power operation can be achieved by aggressively scaling the supply 

voltage to values near or below the threshold voltage, but there are interesting 

trade-offs that show up in this regime. Designers need to revisit methodologies like in 

the first two papers in this session (circuit sizing and decoupling cap placement), or 

have to deal with the increased impact of process variations, as in the last two papers 

in the session (completion detection and trade-offs for SIMD architectures). 

40.1 Standard Cell Sizing for Subthreshold Operation (9:00am) 

Bo Liu, Jose Pineda de Gyvez - Technische Univ. Eindhoven, The Netherlands 

Maryam Ashouei, Jos Huisken - Holst Centre, Eindhoven, The Netherlands 

9:00 - 10:30am 

TOP PICKS OF RUN-TIME POWER 

MANAGEMENT TECHNIQUES 

Chair(s): 

Jian-Jia Chen - Karlsruhe Institute of Technology, Karlsruhe, Germany 

Run-time adaptivity is facing increasing interest in application-specific embedded 

systems. Run-time monitoring and management of system resources are 

necessary to meet system-level requirements. This session explores advanced 

strategies for power and temperature management at run-time in several 

application scenarios. 

41.1 Run-Time Power-Down Strategies for Real- 

Time SDRAM Memory Controllers (9:00am) 

Karthik Chandrasekar - Delft Univ. of Technology, Delft, The Netherlands 

Benny Akesson, Kees Goossens - Technische 

Univ. Eindhoven, The Netherlands 

42 

9:00 - 10:30am 

Room: 306 

Room: 308 

THE DARK SIDE OF TEST 

Chair 

Shreyas Sen - Intel Corp., Portland, OR 

Here are some things you don’t know: how are we going to test TSVs and how 

good are your analog and DRAM tests? This session presents innovative methods 

for dealing with TSV defects in 3-D ICs, testing DRAM memory, and verifying 

analog tests. 

42.1 Alternate Hammering Test for Application-Specific 

DRAMs and an Industrial Case Study (9:00am) 

Rei-Fu Huang - MediaTek, Inc., Hsinchu, Taiwan 

Hao-Yu Yang, Mango C.-T. Chao - National Chiao Tung Univ., Hsinchu, Taiwan 

Shih-Chin Lin - United Microelectronics Corp., Hsinchu, Taiwan 

Room: 310 


40.2 Decoupling Capacitor Design Strategy for Minimizing 

Supply Noise of Ultra-Low Voltage Circuits (9:15am) 

Mingoo Seok - Columbia Univ., New York, NY 

40.3 Regaining Throughput Using Completion Detection 

for Error-Resilient, Near-Threshold Logic (9:30am) 

Joseph Crop, Robert Pawlowski, Patrick Y. Chiang 

- Oregon State Univ., Corvallis, OR 

40.4 Process Variation in Near-Threshold Wide SIMD Architectures (9:45am) 

Sangwon Seo, Ronald Dreslinski, Mark Woh, Yongjun Park, Scott Mahlke, 

David Blaauw, Trevor Mudge - Univ. of Michigan, Ann Arbor, MI 

Chaitali Chakrabarti - Arizona State Univ., Tempe, AZ 


41.2 Embedding Statistical Tests for On-Chip Dynamic 

Voltage and Temperature Monitoring (9:15am) 

Lionel Vincent, Suzanne Lesecq, Edith Beigne - 

CEA-LETI Minatec, Grenoble, France 

Maurine Philippe - Univ. Montpellier 2, France 

41.3 Quality-Retaining OLED Dynamic Voltage Scaling for Video 

Streaming Applications on Mobile Devices (9:30am) 

Xiang Chen, Jian Zeng, Yiran Chen - Univ. of Pittsburgh, PA 

Mengying Zhao, Chun Jason Xue - 

City Univ. of Hong Kong, Kowloon, Hong Kong 

41.4 Traffic-Aware Power Optimization for Network 

Applications on Multicore Servers (9:45am) 

Jilong Kuang, Laxmi Bhuyan, Raymond Klefstad 

- Univ. of California, Riverside, CA 


42.2 Goal-Oriented Stimulus Generation for Analog Circuits (9:15am) 

Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, 

Shobha Vasudevan - Univ. of Illinois at Urbana-Champaign, Urbana, IL 

42.3 TSV Open Defects in 3-D Integrated Circuits: Characterization, 

Test, and Optimal Spare Allocation (9:30am) 

Fangming Ye, Krishnendu Chakrabarty - Duke Univ., Durham, NC 

42.4 Small Delay Testing for TSVs in 3-D ICs (9:45am) 

Shi-Yu Huang, Yu-Hsiang Lin - National Tsing Hua Univ., HsinChu, Taiwan 

Kun-Han Tsai, Wu-Tung Cheng, Stephen Sunter - 

Mentor Graphics Corp., Kanata, ON, Canada 

Yung-Fa Chou, Ding-Ming Kwai - 

Industrial Technology Research Institute, Hsinchu, Taiwan 




43 

1:30 - 3:00pm 

44 

45 SURVIVING TIMING CHALLENGES IN 

NANOMETER DESIGNS 

1:30 - 3:00pm Room: 300 Circuit and Interconnect Analysis 

Chair 

Florentin Dartu - Synopsys, Inc., Hillsboro, OR 

Technology scaling and escalation of design complexity has made assurance 

of timing performance under various process and environmental conditions an 

increasing challenge. Advances in design-time timing analysis and verification 

and in run-time timing failure detection are vital avenues for developing current 

and future nanometer designs. This session highlights recent advancements in 

functional and static timing analysis where novel techniques are developed to 

account for statistical and deterministic sources of timing variations and their 

interactions in an efficient and incremental manner. The session also recognizes 

research geared towards leveraging microarchitectural-level simulation and 

gate-level logic analysis for prediction and tolerance of timing violations in high 

performance processors. 

45.1 Functional Timing Analysis Made Fast and General (1:30pm) 

Yi-Ting Chung, Jie-Hong Roland Jiang - National Taiwan Univ., Taipei, Taiwan 

26 

PANEL: IT’S THE SOFTWARE, STUPID! TRUTH OR MYTH? 

Chair 

Chris Edwards - Tech Design Forum, London, United Kingdom 

Speakers: 

Serge Leef - Mentor Graphics Corp., Wilsonville, OR 

Chris Rowen - Tensilica, Inc., Santa Clara, CA 

Debashis Bhattacharya - FutureWei Technologies, Inc., Plano, TX 

Kathryn S. McKinley - Microsoft Research, Univ. of Texas, Austin, TX 

Eli Savransky - NVIDIA Corp., Santa Clara, CA 

1:30 - 3:00pm 

SPECIAL SESSION: DESIGN CHALLENGES AND EDA 

SOLUTIONS FOR WIRELESS SENSOR NETWORKS 

Chair 

Roman Hermida - Complutense Univ., Madrid, Spain 

The objective of this session is to present a complete overview of the state-of-theart 

technologies and key research challenges for the design and optimization of 

wireless sensor networks (WSN). Thus, it will specifically cover ultra-low-power 

(ULP) computing architectures and circuits, system-level design methods, power 

management, and energy-scavenging mechanisms for WSN. A key aspect of 

this special session is the interdisciplinary nature of the discussed challenges 

in WSN conception, which go from basic hardware components to software 

conception, which requires an active engagement of both academic and industrial 

professionals in the EDA field, computer and electrical engineering, computer 

science, and telecommunication engineering. 

44.1 Circuit and System Design Guidelines for Ultra-Low Power Processing 

Dennis Sylvester, Yoonmyung Lee, Yejoong Kim, 

Dongmin Yoon, David Blaauw - Univ. of Michigan, Ann Arbor, MI 

Room: 305 

Room: 304 

45.2 Timing Analysis with Nonseparable Statistical 

and Deterministic Variations (1:45pm) 

Vladimir Zolotov, Jinjun Xiong - 


Debjit Sinha, Chandu Visweswariah, Jeffrey G. Hemmett, 

Jeremy Leitzen, Natesan Venkateswaran - 

IBM Systems and Technology Group, Hopewell Junction, NY 

Eric Foreman - IBM Corp., Essex Junction, VT 

45.3 Reversible Statistical Max/Min Operation: 

Concept and Applications to Timing (2:00pm) 

Vladimir Zolotov, Jinjun Xiong - 


Debjit Sinha, Chandu Visweswariah - 


Natesan Venkateswaran - 


45.4 Predicting Timing Violations Through Instruction- 

Level Path Sensitization Analysis (2:15pm) 

Sanghamitra Roy, Koushik Chakraborty - Utah State Univ., Logan, UT 



It’s tough to differentiate products with hardware. Everyone uses the same 

processors, third party IP and foundries; now it’s all about software. But, is this 

true? Since user response, power consumption and support of standards rely 

on hardware, one camp claims software is only as good as the hardware it sits 

on. Opponents argue that software differentiates mediocre products from great 

ones. A third view says only exceptional design of both hardware and software 

creates great products - and the tradeoffs make great designers. Watch industry 

experts debate whether it’s really all about software. 


44.2 Design Exploration of Energy-Performance 

Trade-Offs for Wireless Sensor Networks 

Vincenzo Rana, Ivan Beretta, David Atienza - 


Francisco Rincon - Univ. Complutense Madrid, Spain 

Nadia Khaled - Nestlé Research Center, Lausanne, Switzerland 

Paolo R. Grassi - Politecnico di Milano, Italy 

44.3 Energy Harvesting and Power Management 

for Autonomous Sensor Nodes 

Edith Beigné, Jean-Frederic Christmann, Cyril Condemine, 

Jerome Willemin - CEA-LETI, Grenoble, France 

Christian Piguet - Centre Suisse d’Electronique et 

Microtechnique SA, Neuchatel, Switzerland



46 

1:30 - 3:00pm 

47 

48 

1:30 - 3:00pm 

SPECIAL DELIVERY: CHALLENGES IN PACKAGING 

Chair 

Tan Yan - Synopsys, Inc., Mountain View, CA 

Delivering the next generation technologies requires addressing PCB design, 

3-D methodology, and most importantly, packaging. The first three papers in this 

session explore the collaborative design between the chip, package and board, as 

well as IP re-use in 3-D ICs. These methodologies deliver the promise of footprint 

scaling at the packaging level. Pin access can however limit the scaling at the chip 

level. The last paper in the session overcomes that limitation. 

46.1 A Chip-Package-Board Co-Design Methodology (1:30pm) 

Hsu-Chieh Lee, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan 

1:30 - 3:00pm 

RENOVATE ANALOG AND MIXED-SIGNAL 

CIRCUIT SIMULATIONS 

Chair 

Chenjie Gu - Intel Corp., Hillsboro, OR 

This session presents several advanced analysis methodologies for analog and 

mixed-signal circuits. The first topic is fast Monte Carlo analysis for parametric 

yield estimation. Two papers in this area aim to accurately estimate the failure rate 

with a minimum number of transistor-level simulation runs. The second topic is fast 

circuit simulation. This goal is pursued through two different avenues: novel preconditioning 

for iterative solvers and parallel simulation based on GPUs. 

47.1 Yield Estimation via Multi-Cones (1:30pm) 

Rouwaida Kanj - American Univ. of Beirut, New York, NY 

Rajiv Joshi - IBM T.J. Watson Research Ctr., Yorktown Heights, NY 

Zhuo Li, Sani Nassif - IBM Research - Austin, TX 

Jerry Hayes - IBM Research - Austin, TX 

SPECIAL SESSION: HETEROGENOUS PLATFORMS: 

CHALLENGES AND OPPORTUNITIES 

Chair 

Norbert Wehn - Univ. of Kaiserslautern, Germany 

Designing heterogeneous multicore architectures provides many challenges at the 

hardware and software levels. This session will present three different solutions to 

some of these problems, in which the aim of power-efficiency is one of the driving 

factors, while approaching different application areas. 

48.1 Is Dark Silicon Useful? Harnessing the Four 

Horsemen of the Coming Dark Silicon Apocalypse 

Michael B. Taylor - Univ. of California at San Diego, La Jolla, CA 

Room: 306 

Room: 308 

Room: 310 


46.2 Obstacle-Avoiding Free-Assignment Routing 

for Flip-Chip Designs (1:45pm) 

Po-Wei Lee, Hsu-Chieh Lee, Yao-Wen Chang, 

Yuan-Kai Ho - National Taiwan Univ., Taipei, Taiwan 

Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen - Synopsys, Inc., Taipei, Taiwan 

46.3 Clock Tree Synthesis with Methodology of Re-Use in 3-D IC (2:00pm) 

Fu-Wei Chen, TingTing Hwang - National Tsing Hua Univ., Hsinchu, Taiwan 

46.4 Can Pin Access Limit the Footprint Scaling? (2:15pm) 

Xiang Qiu, Malgorzata Marek-Sadowska - 

Univ. of California, Santa Barbara, CA 


47.2 Efficient Trimmed-Sample Monte Carlo Methodology and 

Yield-Aware Design Flow for Analog Circuits (1:45pm) 

Chin-Cheng Kuo, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng - 

Taiwan Semiconductor Manufacturing Co., Ltd., HsinChu, Taiwan 

Wei-Yi Hu - Taiwan Semiconductor Manufacturing Co., Ltd., 

National Taiwan Univ., Hsinchu, Taiwan 

47.3 Towards Efficient SPICE-Accurate Nonlinear Circuit Simulation 

with On-the-Fly Support-Circuit Preconditioners (2:00pm) 

Xueqian Zhao, Zhuo Feng - Michigan Technological Univ., Houghton, MI 

47.4 Sparse LU Factorization for Parallel Circuit 

Simulation on GPU (2:15pm) 

Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, 

Huazhong Yang - Tsinghua Univ., Beijing, China 


48.2 Platform 2012 - A Many-Core Computing Accelerator for Embedded 

SoCs: Performance Evaluation of Visual Analytics Applications 

Diego Melpignano, Eric Flamand, Bruno Jego, Thierry Lepley, 

Germain Haugou - STMicroelectronics, Grenoble, France 

Luca Benini - Univ. di Bologna, STMicrolectronics, Bologna, Italy 

Fabien Clermidy, Denis Dutoit - STMicroelectronics, 

CEA-LETI, Grenoble, France 

48.3 Big.LITTLE System Architecture from ARM: Saving Power through 

Heterogeneous Multiprocessing and Task Context Migration 

Brian Jeff - ARM, Ltd., Austin, TX 




49 

3:30 - 5:30pm 

50 

51 YIELDING IN AN UNCERTAIN WORLD 

3:30 - 5:30pm Room: 300 Design for Manufacturability 

Chair 

Rob Aitken - ARM, Inc., San Jose, CA 

As Moore’s Law marches into the sub-22nm regime, designers are surrounded 

by many uncertainties, such as lithography choices, new device architectures, 

and 3-D integration. These challenges have to be addressed by collective design 

and process integration techniques at multiple abstraction levels. EDA can play a 

pivotal role in bridging these disciplines. To improve yield in the uncertain world, 

this session covers new advancements in pattern recognition, triple patterning, 

EUV, novel memory, and 3-D architecture. 

51.1 Accurate Process-Hotspot Detection Using 

Critical Design Rule Extraction (3:30pm) 

Yen-Ting Yu, Iris Hui-Ru Jiang - National Chiao Tung Univ., Hsinchu, Taiwan 

Ya-Chung Chan - Mstar Semiconductor, Chupei, Taiwan 

Subarna Sinha - Stanford Univ., Stanford, CA 

Charles Chiang - Synopsys, Inc., Mountain View, CA 

51.2 Improved Tangent Space-Based Distance Metric for 

Accurate Lithographic Hotspot Classification (3:45pm) 

Jing Guo, Fan Yang, Xuan Zeng - Fudan Univ., Shanghai, China 

Subarna Sinha - Stanford Univ., Stanford, CA 

Charles Chiang - Synopsys, Inc., Mountain View, CA 

28 

PANEL: PARALLELIZATION AND SOFTWARE 

DEVELOPMENT: HOPE, HYPE, OR HORROR? 

Chair 

Igor Markov - Univ. of Michigan, Ann Arbor, MI 

Speakers: 

Anirudh Devgan - Magma Design Automation, Inc., Austin, TX 

Kunle Olukotun - Stanford Univ., Stanford, CA 

Daniel Beece - IBM Research, Yorktown Heights, NY 

Joao Geada - CLK Design Automation, Inc., Littleton, MA 

Alan J. Hu - Univ. of British Columbia, Vancouver, BC, Canada 

With the fear that the death of scaling is imminent, hope is widespread that 

parallelism will save us. Many EDA applications are described as “embarrassingly 

parallel,” and parallel approaches have certainly been effectively applied in many 

3:30 - 5:30pm 

SPECIAL SESSION: HOT CHIPS RUNNING COOL - 

ENERGY EFFICIENT NEAR-THRESHOLD 

COMPUTING AND ITS BARRIERS 

Chair 

David Brooks - Harvard Univ., Cambridge, MA 

Transistor threshold voltages have stagnated in recent technologies, deviating 

from constant-voltage scaling theory and limiting voltage scalability. Consequently, 

power and energy no longer improve as expected and the semiconductor 

industry now faces a power wall. To overcome this barrier, energy-efficiency must 

radically improve by lowering supply voltage and operating “near threshold,” 

where appreciable energy gains are achieved with modest performance losses. 

Near-threshold computing (NTC) poses new circuit and architectural challenges, 

including performance loss and increased variability. This special session quantifies 

NTC benefits and limitations, offers opinions on its suitability to commercial ICs, 

and suggests techniques to overcome associated challenges. 

50.1 Assessing the Performance Limits of 

Parallelized Near-Threshold Computing 

David Blaauw, Nathaniel Pinckney, Kory Sewell, Ronald G. Dreslinski, 

David Fick, Dennis Sylvester, Trevor Mudge - Univ. of Michigan, Ann Arbor, MI 

Room: 305 


areas. Before the panel begins, come hear perspective on software development 

and the challenges associated with writing good software that are only exacerbated 

by the growing need to write robust, testable, and efficient parallel applications. 

Then watch the panelists debate future productive directions and dead ends to 

developing and deploying parallel algorithms. Find out if claims to super speedups 

are exaggerated and if the investment in parallel algorithms is worth the high 

development cost. 

Room: 304 

49.1 PhD or MD - Who is Better Trained for Building 

Successful Software Development Tools? (3:30pm) 



50.2 Near-Threshold Voltage (NTV) Design - Opportunities and Challenges 

Shekhar Borkar, Himanshu Kaul, Mark Anders, Steven Hsu, 

Amit Agarwal, Ram Krishnamurthy - Intel Corp., Hillsboro, OR 

50.3 Near-Threshold Operation for Power Efficient Computing? It Depends... 

Leland Chang, Wilfried Haensch - 


50.4 Not so Fast my Friend: Is Near-Threshold Computing 

the Answer for Power Reduction of Wireless Devices? 

Matt Severson - Qualcomm, Inc., Austin, TX 

Kendrick Yuen, Yang Du - Qualcomm, Inc., San Diego, CA 

51.3 Simultaneous Flare Level and Flare Variation 

Minimization with Dummification in EUVL (4:00pm) 

Shao-Yun Fang, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan 

51.4 A Novel Layout Decomposition Algorithm for 

Triple Patterning Lithography (4:15pm) 

Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen 

- National Taiwan Univ., Taipei, Taiwan 

51.5 PS3-RAM: A Fast, Portable, and Scalable Statistical 

STT-RAM Reliability Analysis Method (4:30pm) 

Wujie Wen, YaoJun Zhang, Yiran Chen - Univ. of Pittsburgh, PA 

Yu Wang - Tsinghua Univ., Beijing, China 

Yuan Xie - Pennsylvania State Univ., University Park, PA 

51.6 Exploiting Narrow-Width Values for Process 

Variation-Tolerant 3-D Microprocessors (4:45pm) 

Joonho Kong, Sung Woo Chung - Korea Univ., Seoul, Republic of Korea 




52 

HIGH-LEVEL SYNTHESIS IS NOT JUST 

ABOUT TRANSLATION! 

3:30 - 5:30pm Room: 306 High-Level and Logic Synthesis 

Chair 

Satnam Singh - Google, Inc., Mountain View, CA 

High-level synthesis aims to improve the end result of hardware generation by 

allowing exploration of architecture and algorithm, rather than logic structure 

and connectivity. HLS is not just about translation: the interesting problems aim 

to convert designer intent into efficient and correct hardware realization. The 

papers in this session cover issues related to languages to express and generate 

hardware, synthesis of software constructs such as recursion, hardware checkpointing 

for resiliency, optimizing memory access, synthesizing layout-friendly 

hardware, and design-space exploration of sorting networks. 

52.1 Hardware Synthesis of Recursive Functions 

through Partial Stream Rewriting (3:30pm) 

Lars Middendorf, Christian Haubelt - Univ. of Rostock, 

Rostock-Warnemuende, Germany 

Christophe Bobda - Univ. of Arkansas, Fayetteville, AR 

53 

WILD AND CRAZY IDEAS 

3:30 - 5:30pm 

Chair 


It cannot get any crazier! Your friends on Facebook verify your designs. Your 

sister is eavesdropping on your specification. Do not take “no” for implication. Build 

satisfying circuits with noise. Let spin-based synapses make your head spin. Use 

parasitics to build 3-D brains. 

53.1 CrowdMine: Towards Crowdsourced Human- 

Assisted Verification (3:30pm) 

Wenchao Li, Sanjit A. Seshia - Univ. of California, Berkeley, CA 

Somesh Jha - Univ. of Wisconsin, Madison, WI 

53.2 Extracting Design Information from Natural 

Language Specifications (3:45pm) 

Ian G. Harris - Univ. of California, Irvine, CA 

54.1 Communication-Aware Mapping of KPN Applications 

onto Heterogeneous MPSoCs (3:30pm) 

Jeronimo Castrillon, Andreas Tretter, Rainer Leupers, 

Gerd Ascheid - RWTH Aachen Univ., Aachen, Germany 

54.2 Unrolling and Retiming of Stream Applications 

onto Embedded Multicore Processors (3:45pm) 

Weijia Che, Karam S. Chatha - Arizona State Univ., Tempe, AZ 

52.2 Chisel: Constructing Hardware in a Scala 

Embedded Language (3:45pm) 

Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, 

Andrew Waterman, Rimas Avizienis, John Wawrzynek, 

Krste Asanovic - Univ. of California, Berkeley, CA 

52.3 Specification and Synthesis of Hardware 

Checkpointing and Rollback Mechanisms (4:00pm) 

Carven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, 

Sharad Malik - Princeton Univ., Princeton, NJ 

52.4 Optimizing Memory Hierarchy Allocation with Loop 

Transformations for High-Level Synthesis (4:15pm) 

Peng Zhang, Jason Cong, Yi Zou - Univ. of California, Los Angeles, CA 

52.5 A Metric for Layout-Friendly Microarchitecture 

Optimization in High-Level Synthesis (4:30pm) 

Bin Liu, Jason Cong - Univ. of California, Los Angeles, CA 

52.6 Computer Generation of Streaming Sorting Networks (4:45pm) 

Marcela Zuluaga, Markus Püschel - 

Eidgenössische Technische Hochschule, Zürich,Switzerland 

Peter Milder - Carnegie Mellon Univ., Pittsburgh, PA 

Room: 308 

WACI 

53.3 Material Implication in CMOS: A New Kind of Logic (4:00pm) 

Elkim Roa, Wu-Hsin Chen, Byunghoo Jung - Purdue Univ., West Lafayette, IN 

53.4 Boolean Satisfiability Using Noise-Based Logic (4:15pm) 

Sunil Khatri, Pey-Chang Kent Lin, Ayan Mandal - 

Texas A&M Univ., College Station, TX 

53.5 Cognitive Computing with Spin-Based Neural Networks (4:30pm) 

Charles Augustine - Intel Corp., Hillsboro, OR 

Mrigank Sharad, Georgios Panagopoulos, 

Kaushik Roy - Purdue Univ., West Lafayette, IN 

53.6 Capacitance of TSVs in 3-D Stacked Chips a Problem? 

Not for Neuromorphic Systems! (4:45pm) 

Rodolphe Héliot, Antoine Joubert, Bilel Belhadj - 

CEA-LETI Minatec, Grenoble, France 

Marc Duranton - CEA-LIST, Gif-sur-Yvette Cedex, France 

Olivier Temam - INRIA, Saclay, France 

54 OPTIMIZING EMBEDDED SOFTWARE FOR 

HIGH PERFORMANCE AND RELIABILITY 

3:30 - 5:30pm Room: 310 


Chair 

54.3 Exploiting Spatiotemporal and Device Contexts for 

Rodric Rabbah - IBM Research, Hawthorne, NY 

Energy-Efficient Mobile Embedded Systems (4:00pm) 

The need to consider multiple objectives is a characteristics of embedded systems. 

Average performance, precise timing, energy consumption, thermal behavior, and 

reliability are among objectives to consider. The multitude of objectives is a key 

challenge in embedded system design. The papers in this session push forward 

the state of the art in performance- and reliability-aware embedded software 

Brad K. Donohoo, Chris Ohlsen, Sudeep Pasricha, 

Charles W. Anderson - Colorado State Univ., Fort Collins, CO 

54.4 EPIMap: Using Epimorphism to Map Applications on CGRAs (4:15pm) 

Mahdi Hamzeh, Aviral Shrivastava, 

Sarma Vrudhula - Arizona State Univ., Tempe, AZ 

design, with an emphasis on code generation. 

54.5 Instruction Scheduling for Reliability-Aware Compilation (4:30pm) 

Semeen Rehman, Muhammad Shafique, 

Joerg Henkel - Karlsruhe Institute of Technology, Karlsruhe, Germany 

54.6 Compiling for Energy Efficiency on Timing 

Speculative Processors (4:45pm) 

John Sartori, Rakesh Kumar - 

Univ. of Illinois at Urbana-Champaign, Urbana, IL 


USER TRACK 


1 

30 


Sponsored by: 

SOFTWARE AND FIRMWARE ENGINEERING FOR 

COMPLEX SOCS 

10:00 - 11:30am 

Chair: 

Pat Brouillette - Roku, Inc., Scottsdale, AZ 

Early software development is crucial for today’s complex SoCs, where the overall 

software effort typically eclipses the hardware effort. Further, delays in software 

directly impact the time to market of the end product. The presentations in this 

session explore how to architect ASIPs for wireless applications, how to bridge RTL 

and firmware development, and approaches in pre-silicon software development. 

2 

12:30 - 1:30pm 

Room: 106 - Exhibit Floor 

USER TRACK POSTER SESSION 

Front-End Silicon Design Topics / Back-End Silicon Design Topics 


2.1 An RTL Developers Guide to the HLS Galaxy 

Stefen Boyd - TLM Systems, Morgan Hill, CA 

Sergio Ramirez - Cadence Design Systems, Inc., Austin, TX 

2.2 Maximizing the Reuse of UVM Components by 

Leveraging UVM Configuration DB Mechanism 

Manikandan S, Sunil Kumar, Ashish Kumar - LSI Corp., Bangalore, India 

2.3 Practical Application of Model Checking 

– A Taxonomy of Methodologies 

Michael G. Bartley, Anthony McIsaac - 

Test and Verification Solutions, United Kingdom 

Laurent Arditi, Bryan Dickman, Daryl Stewart - 

ARM, Inc., Cambridge, United Kingdom 

Lawrence Loh - Jasper Design Automation, Inc., Mountain View, CA 

2.4 A Subsystem Design Methodology Using High Level Synthesis 

Gagan Midha - STMicroelectronics, Greater Noida, India 

Nitin Chawla, Bryan Bowyer - Calypto Design Systems, Inc., Wilsonville, OR 

2.5 Logic Power Reduction in Data Path Oriented 

Designs by Re-Structuring Standard Cells 

Vinay S. Adavani - Infinera Corp., Bangalore, India 

2.6 SoC Power Budgeting and Optimization Using RTL- 

Spreadsheet Power Estimation of ASICs 

Udupi Harisharan, Jaga Shanmugavadivelu - 

Cisco Systems, Inc., San jose, CA 

Narayana Koduri - Atrenta, Inc., San jose, CA 

2.7 Billion Gate Semiconductor Design and Simulation and 

the Next Phase of the Cloud Computing Evolution 

James Colgan - Xuropa, Inc., San Francisco, CA 

Naresh K. Sehgal, Mrittika Ganguli - Intel Corp., Bangalore, India 

2.8 Effortless, Quick and Accurate Data Entry of IPXACT Based 

SoC Connectivity Information Using Exce-Based VBA Macros 

Saurin Patel, Silvia Costantini, 

Sparsh Arun - STMicroelectronics, Greater Noida, India 

2.9 Development of a Unified Platform for Accelerated 

SoC Verification and Validation 

Maruthy Vedam, Suman Kasam - Qualcomm, Inc., San Diego, CA 

Hemant K. Sharma, Anoop Saha, Hans van der Schoot 

- Mentor Graphics Corp., Ottawa, ON, Canada 

2.10 UVM Based Configurable Testbench for Verifying a Configurable IP 

Pusuluri V. Giri Kumar, Pramodh M. Kumar - Synopsys, Inc., Bangalore, India 

2.11 An Efficient Design Approach of Control Logic with the Use 

of High Level Synthesis for a Video Signal Conversion FPGA 

Ryo Yamamoto - Mitsubishi Electric Corp., Kamakura, Japan 

User Track - Embedded Systems and Software 

1.1 Finding the Right mix of Parallelism in a Coarse- 

Grained Array Baseband Processor (10:00am) 

Tom Vander Aa, Praveen Raghavan, Raf Appeltans, Martin Palkovic, 

Min Li, Antoine Dejonghe, Liesbet Van der Perre - IMEC, Leuven, Belgium 

1.2 Two for the Price of One - An Affordable Solution That Bridges 

the gap Between Firmware and RTL Implementations (10:15am) 

Alicia Strang, Robert C. Carden IV, Pei Suen - 

Marvell Semiconductor, Inc., Aliso Viejo, CA 

1.3 Enabling SoC Products with Pre-Si SW Development (10:30am) 

Ken Knowlson - Intel Corp., Hillsboro, OR 

User Track 

2.12 RTL Restructuring with Atrenta GenSys 

Cyril Vartanian, Olivier Florent - STMicroelectronics, Grenoble, France 

2.13 Framework and Automation for Effective 

Adoption of a Third Party Verification IP 

Abhisek Verma, Amit Sharma, Varun S - Synopsys, Inc., Bangalore, India 

Bhavik Vyas - Reliance Consulting, Sunnyvale, CA 

2.14 Extending UVM Methodology for Verifying Mixed-Signal Components 

Abhisek Verma, Fabian Delguste, Adiel Khan - 

Synopsys, Inc., Mountain View, CA 

2.15 Exploring AES Design Variants with C-to- 

Gates for FPGA at Gb/s Line Rates 

Kees Vissers, Fernando Martinez Vallina, 

Stephen Neuendorffer - Xilinx, Inc., San Jose, CA 

Kristof Denolf, Ronny Dewaele - Barco, Kortrijk, Belgium 

2.16 Real Value Modeling Enables Metric Driven 

Verification of Mixed Signal Design 

Kishore Karnane, Walter Hartong - 

Cadence Design Systems, Inc., Feldkirchen, Germany 

Thomas Fuchs, Ronald Nerlich - Texas Instruments, Inc., Freising, Germany 

2.17 Verification of Massive Advanced Node SoCs 

Daeseo Cha - Samsung, Youngin, Republic of Korea 

Adam Sherer - Cadence Design Systems, Inc., Chelmsford, MA 

2.18 Challenges and Recommendations for 

Modeling Complex Verification IP 

Imran Ali, Anuradha I. Tambad, Subashini Rajan, 

Shivani Upasani, Prashanth Srinivasa - LSI Corp., Bangalore, India 

2.19 Electrostatic Discharge Analysis on a Fullchip SoC Design 

Nitin S. Navale, Warren Anderson - 

Advanced Micro Devices, Inc., Boxborough, MA 

2.20 Advanced ESD Tool Flow, Testing, and Design Verification Results 

Mujahid Muhammad, Nicholas Palmer, Souvick Mitra, James Montstream, 

Robert Gauthier - IBM Systems and Technology Group, Essex Junction, VT 

2.21 Using Fast, High-Capacity, Attofarad-Accurate 3-D Extraction for 

Successful Design of High-Performance IPs in Advanced CMOS Nodes 

Atul Bhargava, Chittoor Parthasarthy, Srisurya Konduri 

- STMicroelectronics, Greater Noida, India 

Kiran Joseph, Claudia Relyea - Mentor Graphics Corp., Wilsonville, OR 

2.22 CirCAD: Technique of Intelligent Custom Design 

Sanjeev KR, Sumit Goswami - Intel Corp., Bangalore, India 

2.23 Practical Optimization Method for Multi-Corner 

Multi-Mode Timing Closure in 32 nm 

Xiaoyue Wang - STMicroelectronics, Ottawa, ON, Canada

USER TRACK 


2.24 eClock: Easy Clock Generation via 

All-Digital Phase-Locked Loop Compiler 

Shi-Yu Huang, Chao-Wen Tzeng - National Tsing Hua Univ., Hsinchu, Taiwan 

Pei-Ying Chao, Ruo-Ting Ding - TinnoTek Inc., Hsinchu, Taiwan 

Ding-Ming Kwai - Industrial Technology Research Institute, Hsinchu, Taiwan 

Nian-Shyang Chang, Chien-Lin Huang - 

National Chip Implementation Center, Hsinchu, Taiwan 

2.25 LDE (Layout Dependent Effects) Aware Design 

Solution in Advanced Technologies 

M.J. Huang, Sharon Jiang, Steven Chen - Taiwan 

Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan 

Cliff Hung, Captain Liu - SpringSoft, Inc., Hsin-chu, Taiwan 

2.26 Coupling-Aware Statistical Timing Analysis 

Henry Chan, Nathan Buck, Brian Dreibelbis, John Dubuque, Eric Foreman, 

Peter A. Habitz, David J. Hathaway, 

Gregory M. Schaeffer - IBM Corp., Hopewell Junction, NY 

Chandu Visweswariah - IBM Systems and Technology Group, 

Hopewell Junction, NY 

2.27 3-D Transient Field Simulator for Chip-Level 

Analysis of Electro-Thermal Coupling 

Dundar Dumlugol, Wim Schoenmaker, Peter Meuris, 

Olivier Dupuis - Magwel NV, Leuven, Belgium 

Aarnout Wieers, Joseph Rhayem, Yves Depret - 

ON Semiconductor, Oudenaarde, Belgium 

2.28 Adoption of Static Timing Analysis with 

Advanced On-Chip Variation at 28nm 

Steven C. Chan, Adrian Au Yeung, Tze Haw Liew, 

Karsten Matt - GLOBALFOUNDRIES, Milpitas, CA 

Ning Jin - Univ. of California, Los Angeles, CA 

3 

1:30 - 3:00pm 

POWER ANALYSIS AND OPTIMIZATION 

Chair: 

Laurent Chaouat - Samsung, Austin, TX 

Power is now one of the most critical aspects of system design. Presentations 

in this session include a framework for design decision making and its application 

to power analysis, a power-aware verification framework, approaches to make 

gate-level power analysis easier, and a design and verification suite for clock gating. 

3.1 DesignDB - A Framework for Design Decision Making 

and its Application to Power Analysis (1:30pm) 

Mosur K. Mohan, Eric Donkoh - Intel Corp., Hillsboro, OR 

4 


CIRCUIT ANALYSIS AND OPTIMIZATION 

4:00 - 6:00pm 

Chair: 

Nagaraj NS - Texas Instruments, Inc., Dallas, TX 

Variability and other circuit effects constitute a significant challenge and optimization 

opportunity in deep submicron design. This session features circuit analysis and 

optimization for various electrical effects. These complex techniques extend the 

capabilities of existing design methods. Presentations discuss the effect of stress 

on variability, improving accuracy in extraction, early fast and efficient analysis for 

IR drop and dynamic voltage drop, and hierarchical robustness analysis. 

4.1 40nm and 28nm Variability-Aware Digital Designs (4:00pm) 

Philippe Hurat, Chris Pitchford - Cadence Design Systems, Inc., 

Bracknell, United Kingdom 

Andrew Appleby - Cambridge Silicon Radio, Cambridge, United Kingdom 

Mark Zwolinski, Yangang Wang - 

Univ. of Southampton, Southampton, United Kingdom 

Mark Scoones, Sonia Caldwell, Touqeer Azam - 

CSR, Cambridge, United Kingdom 

Sponsored by: 

2.29 A Novel Power-Grid Early Analysis Capability and Flow for 

Ensuring Efficient, Robust, and Reliable Power-Grid Designs 

Efrat Rachevsky - Marvell Semiconductor, Inc., Adanim, Israel 

2.30 Symbolic SRAM Layout Analysis for 

Design and Technology Exploration 

Paul Zuber, Miguel Miranda, Petr Dobrovolny, Peter De Bisschop, 

Mustafa Badaroglu, Diederik Verkest - IMEC, Leuven, Belgium 

2.31 Variation-Aware Design Techniques for the Advanced 28nm Node 

Suresh Raman, Shashank Bhonge - Xilinx, Inc., Hyderabad, India 

2.32 Prevention of Data Loss in Physical Implementation 

of FIFOs and Data Path Synchronizers 

Ramesh Rajagopalan, Ajay Bhandari - Cisco Systems, Inc., San Jose, CA 

Namit Gupta - Atrenta, Inc., San Jose, CA 

2.33 Single Pass Stitched Metal Filling Technique 

for Multi-Power Domain SoCs 

Dibyendu Goswami, Swami Gangadharan - Intel Corp., Bangalore, India 

2.34 Incremental Fill: Metal Fill Legalization for ECO Layout Convergence 

Dibyendu Goswami, Suryanarayana Prekke, 

Rajesh Karturi - Intel Corp., Bangalore, India 

2.35 Case Study on Diagnosing Intermittent Scan Chain Hold-Time Defects 

Wu-Tung Cheng, Yu Huang, Dragon Hsu - 

Mentor Graphics Corp., HsinChu, Taiwan 

Augusli Kifli, Yu-Wei Chen - Faraday Technology Corp., Hsinchu City, Taiwan 

2.36 Clock Tree Synthesis Careabouts for Complex SoCs 

Rivu Das, Vishweshwara R, Venkatraman Ramakrishnan, Santhosh 

Thiyagaraja, Mahita Nagabhiru - Texas Instruments, Inc., Bangalore, India 

2.37 Modeling of Near-Device Parasitics in MOSFETs 

and BJTs Using 3-D Fieldsolver 

Prasanna Bekal, Weiping Shi - Texas A&M Univ., College Station, TX 

User Track - Front End 

3.2 Proven Techniques for a Seamless Power- 

Aware Verification Framework (1:45pm) 

Anees Sutarwala, Osama Neiroukh - Intel Corp., Haifa, Israel 

3.3 Taking the Pain out of Gate-Level Power Analysis (2:00pm) 

Krishnan Sundaresan, Ke Zhong, Wei-Lun Hung, Jaewon Oh, 

Mohd Jamil Mohd, Rob Mains - Oracle, Santa Clara, CA 

3.4 Clock Gating Design and Verification Suite (2:15pm) 

Masanori Kurimoto, Naoshi Ishikawa, Koichi Ishimi, Masaya Kitao, Teruyuki 

Ito, Satoshi Kaneko, Hiroyuki Kondo - Renesas Electronics Corp., Itami, Japan 


User Track - Back End 

4.2 Accuracy Analysis of Parasitic Extraction for 

Advanced Nodes (28nm) (4:15pm) 

Hendrik T. Mau - GLOBALFOUNDRIES, Dresden, Germany 

4.3 HVCOM Model for Graphics IP IR Drop Analysis (4:30pm) 

Anand Ananthanarayanan, Basavaraj Kanthi, 

Srikrishnan Venkataraman, Nitin Jain - Intel Corp., Folsom, CA 

4.4 Rapid IR Hotspot Diffusion Using 

In-Design Power Grid Analysis (4:45pm) 

Sumit Goswami, Mysore Sriram, 

Srikrishnan Venkataraman - Intel Corp., Bangalore, India 

4.5 Hierarchical Thermal and Electromigration 

Analysis for Cell-Based Designs (5:00pm) 

Srini Krishnamoorthy, Vishak Venkatraman, Thomas Burd, James Pistole, 

Yuri Apanovich, Rajit Chandra - Advanced Micro Devices, Inc., Sunnyvale, CA 

4.6 A Novel Method for Effective Early Dynamic 

Voltage Drop Analysis (5:15pm) 

Khusro Sajid, Sorin A. Dobre, Mamta Bansal, 

Karim Arabi - Qualcomm, Inc., San Diego, CA 


USER TRACK 


5 

9:00 - 10:30am 

32 


Sponsored by: 

PACKAGING AND AUTOMATIC PLACE AND 

ROUTE MINI SESSIONS 

Chair: 

Thomas Brandtner - Infineon Technologies, Villach, Austria 

With the increase in integration and smaller form factor products, package design 

is a hot topic. The first two presentations discuss embedded packaging and 

package level power models. Physical design optimization constitutes a significant 

part of the design process, particularly in the face of increasing rule complexity in 

advanced semiconductor processes. The final two presentations discuss place 

and route methods for hierarchical mixed-signal design and for structured designs. 

5.1 Embedding Bare Die and Discrete Passives in an Organic 

Substrate Package Design, Assembly, and Fabrication (9:00am) 

Charles Pfeil - Mentor Graphics Corp., Longmont, CO 

6 

12:30 - 1:30pm 

USER TRACK POSTER SESSION 

Embedded Systems and Software, Front-End, and Back-End Silicon Design Topics 

6.1 FPGA-Based ASIC Prototyping 

Zied Marrakchi, Ramsis Farhat - 

FLEXRAS Technologies Sas., Saint-Denis, France 

Ramine Roane - Xilinx, Inc., San Jose, CA 

6.2 A Next Generation IP and SoC Development Platform 

Fergus Slorach, Simon M. Butler - Methodics, Inc., San Francisco, CA 

Bertrand Blanc - Altera Corp., San Jose, CA 

6.3 Nexus 5001 - Instrumentation Architectures and the New Specification 

Neal Stollon - HDL Dynamics, Dallas, TX 

6.4 Deployment of Virtual Technology for Cave Creek Network Connection 

Qun Wan, Alan Carew - Intel Corp., Shannon, Ireland 

6.5 Reusable XML-Based Methodology and Tool Chain for 

Concept Development and Product Verification 

Bas Arts - NXP Semiconductors, Eindhoven, The Netherlands 

6.6 Cloud-Based Parallel Design Space Exploration Using EDAxtend 

Harnhua Ng - Plunify, Inc., Sunnyvale, CA 

Cristopher Magalang - Plunify Pte., Ltd., Singapore 

6.7 Making Verification Environment Performance 

Efficient - Case Studies and Guidelines 

Sarath C. Valapala, Prashanth Srinivasa - LSI Corp., Bangalore, India 

6.8 Register Verification on a Fast Lane: Using Automation 

to Converge on UVM REG Coverage Models 

Abhisek Verma, Varun S, Amit Sharma - Synopsys, Inc., Bangalore, India 

6.9 Automated Monitoring and Checking of Real-Valued 

Behavior in Mixed-Signal Designs Using UVM 

Alexander W. Rath, Volkan Esen, Wolfgang Ecker - 

Infineon Technologies AG, Neubiberg, Germany 

6.10 Using Higher-Level VHDL Style in High-End Processor Design 

Ariel J. Birnbaum, Ilia Averbouch, Gil Shurek, 

Ilan Beer - IBM Haifa Research Lab., Haifa, Israel 

6.11 A Unified Design and Simulation Environment Using Spreadsheet 

Young-Il Kim, Wooseung Yang, Ju Hwan Yi, 

Hoon Choi - Silicon Image, Inc., Sunnyvale, CA 

6.12 Functional and Performance Verification of a Rate- 

Controlled QoS-Based Arbiter Using Formal Methods 

Yirng-An Chen, Saeed Shamshiri, Michael Hsieh - 

Marvell Semiconductor, Inc., Santa Clara, CA 




5.2 Package Modeling and Verification for On- 

Chip Power Integrity Analysis (9:15am) 

Hang Li, Eileen You, Harpreet Gill - Samsung, San Jose, CA 

5.3 Hierarchical APR Approach for Mixed Signal Designs (9:30am) 

Atul Walimbe,Sumit Goswami, Victoria Kolesov, 

Raj Varada - Intel Corp., Santa Clara, CA 

5.4 Structured APR: A Hybrid Approach for 

Efficient Custom Design (9:45am) 

Sumit Goswami, Atul Walimbe, Victoria Kolesov, 

Raj Varada - Intel Corp., Santa Clara, CA 

User Track 

6.13 Challenges in Verifying USB3.0 Host and Device Controller 

Abbas Khalili, Ryan Rhodes, Adrian Yu - 

Broadcom Corp., Richmond, BC, Canada 

6.14 Utilizing Acceleration Platforms Using Off- 

Platform Generated Test-Cases 

Dmitry Krestyashyn, Wisam Kadry, Shimon Landa, 

Vitali Sokhin - IBM Haifa Research Lab., Haifa, Israel 

Amir Nahir - IBM Corp., Haifa, Israel 

6.15 Are You Managing Your Registers Data or Barely Striving to 

Manage...(Or: Executable Specification of Registers Data) 

Arik Shmayovitsh - Sigma Designs, Inc., Tel Aviv, Israel 

Doron Meiraz - Synopsys, Inc., Herzelia, Israel 

6.16 Architectural Coverage for Post-Silicon Exercisers 

Nirmal M. Kumar, Varun Mallikarjunan, Subrat K. Panda - 

IBM Systems and Technology Group, Bangalore, India 

Amir Nahir - IBM Corp., Haifa, Israel 

Vitali Sokhin, Avi Ziv - IBM Haifa Research Lab., Haifa, Israel 

6.17 Coverage Driven Requirements Management 

Andre Winkelmann - Wolfson Microelectronics plc, Edinburgh, United Kingdom 

Jason Sprott - Verilab, Inc., Glasgow, United Kingdom 

6.18 Effective Functional Vectors in a Partial Scan 

Paradigm – Challenges and Learning 

Ballori Banerjee - LSI Corp., Bangalore, India 

6.19 Starting CDC from SDC 

YoungChan Lee, Namdo Kim, Byeong Min - 

Samsung, Yongin-City, Republic of Korea 

Wesley Park - Mentor Graphics Corp., San Jose, CA 

6.20 Facilitating Debug in ESL Design with Automated Root-Cause Analysis 

Katsunobu Natori, Yuichi Soejima, 

Tetsuya Nakajima - Hitachi Ltd., Yokohama-shi, Japan 

6.21 Property Checking of Datapath Using Word- 

Level Formal Equivalency Tools 

Theo Drane - Imagination Technologies Ltd., Kings Langley, United Kingdom 

Himanshu Jain - Synopsys, Inc., Hillsboro, OR 

6.22 Integration of Enterprise Manager SQL Database in Verification Cockpit 

Mickael M. Moreau - STMicroelectronics, Grenoble, France 

6.23 A Structured Power Grid Design Methodology and Analysis 

Considerations for a Low Cost, High Performance SoC 

Siva Srinivas Kothamasu, Stalin SM - 

Texas Instruments, Inc., Bangalore, India

USER TRACK 


6.24 Full-Chip ESD Network Extraction and Verification 

Dundar Dumlugol, Jiri Ocenasek, Wim Schoenmaker, Bart De Smedt, 

Peter Meuris, Olivier Dupuis - Magwel NV, Leuven, Belgium 

Edgardo Laber - Intersil Americas, Inc., Milpitas, CA 

6.25 Understanding and Designing for Variation in 

GLOBALFOUNDRIES 28-nm Technology 

Pei Yao, Richard Trihy - GLOBALFOUNDRIES, Milpitas, CA 

Jiandong Ge, Kristopher Breen, Trent McConaghy - 

Solido Design Automation, Inc., Saskatoon, SK, Canada 

6.26 Sensitivity Analysis of CMOS Devices Using a Field Solver 

Karen Chow, Yasu Nariki - Mentor Graphics Corp., Tokyo, Japan 

Kunihiko Tsuboi - STARC, Yokohama, Japan 

6.27 Congestion Analysis at Various Design Phases of a 

Complex Multi-Domain SoC and Avoidance Techniques to 

Improve Design Convergence and Cycle Time Improvement 

Rivu Das, Stalin SM, Arun Koithyar - Texas Instruments, Inc., Bangalore, India 

6.28 Qualcomm DSP Tool Agnostic Relative Placement Design Flow 

Nadeem Eleyan, Shahid Imam, Tung Pham, Dwight Galbi, 

Ken Lin, Paul Bassett - Qualcomm, Inc., Austin, TX 

Dan Bui - Ciranova, Inc., Santa Clara, CA 

6.29 Design Workflow Management for SoC Implementation 

Albert Li, Louis Liu, Reed Lee, Neil Liang, Chien-Chu(Alex) Kuo, 

Mei-Lin Liang - Global Unichip Corp., Yokohama, Japan 

6.30 Novel Inizialization and Implementation Method for HBM 

ESD Compliance Automated Check on Smart Power ICs 

Mauro Fragnoli, Eleonora Gevinti, Antonio Bogani, 

Lorenzo Cerati - STMicroelectronics, Agrate Brianza, Italy 

7 

1:30 - 3:00pm 

Chair: 

Gary Smith - Gary Smith EDA, Santa Clara, CA 

Speakers: 

Joshua Friedrich - IBM Server and Technology Group, Austin, TX 

Viresh Paruthi - IBM Server and Technology Group, Austin, TX 

Stephen Shuma - IBM Server and Technology Group, Austin, TX 

Brad Heaney - Intel Corp., Folsom, CA 

Madhu Ponnada - Intel Corp., Folsom, CA 

Rama Ramakrishnan - Intel Corp., Folsom, CA 

Artour Levin - Intel Corp., Folsom, CA 

Omar Malik - Intel Corp., Folsom, CA 

8 

4:00 - 6:00pm 

PRACTICAL FORMAL METHODS 

Sponsored by: 

6.31 Performance Path Test Statistical Methodology 

Jinjun Xiong, Vladimir Zolotov - 


Jeanne P. Bickford, Anthony Polson, Pamela S. Gillis, Jose M. Martinez, 

Francis Woytowich - IBM Systems and Technology Group, Essex Junction, VT 

Vikram Iyengar - IBM Systems and Technology Group, Pittsburgh, PA 

Kevin Bercaw - IBM Systems and Technology Group, 

Research Triangle Park, NC 

Chandu Visweswariah - IBM Systems and Technology Group, 

Hopewell Junction, NY 

6.32 Impact of Lithography and Stress on 28nm Design Performance 

Edward Teoh, Jianhao Zhu - GLOBALFOUNDRIES, Singapore 

Philippe Hurat - Cadence Design Systems, Inc., San Jose, CA 

6.33 On-Chip Noise Coupling Analysis 

Jacob Bakker, Sergei Kapora, Marcel Pelgrom, Boris Ljevar, Andries 

van der Veen - NXP Semiconductors, Eindhoven, The Netherlands 

Keith A. Sabine - ANSYS, Inc, Chinnor, United Kingdom 

Jerome Toublanc - Apache Design, Inc. a subsidiary of ANSYS, Inc., 

Grenoble, France 

Ying-Shiun Li - Apache Design, Inc. a subsidiary of ANSYS, Inc., San Jose, CA 

6.34 Substrate and Metal Layer Noise “Heat Maps” 

Generated with Apache Totem Predict Improved Noise 

Performance in a Mass-Produced Image Sensor Chip 

Kenneth F. Boorom - Aptina Imaging Corp., Corvallis, OR 

Shaan Awasthi - ANSYS, Inc, San Jose, CA 

6.35 Design and Use of Stress Managing Cells for Timing Closure 

Puneet Sharma - Freescale Semiconductor, Inc., Austin, TX 

6.36 Stable Physical Synthesis for Design Iterations 

Cliff Sze, Gi-Joon Nam - IBM Research - Austin, TX 

Paul Villarrubia - IBM Corp., Austin, TX 

Natarajan Viswanathan - IBM Systems and Technology Group, Austin, TX 

DESIGNER PANEL - INTERACTIVE KEYNOTE 

QUESTION AND ANSWER SESSION 



User Track 

This special session is an interactive follow-up to the morning keynotes by Joshua 

Friedrich (IBM) and Brad Heaney (Intel). Senior leaders from both design teams 

will sit for a moderated Q/A panel session with the audience. The first half of the 

session will be with the IBM team; the second half will be with the Intel team. Take 

advantage of this unusual opportunity! 


Chair: 

8.3 Functional vs. Structural Verification - Case Study (4:30pm) 

Krishnan Sundaresan - Oracle, Santa Clara, CA 

Gadiel Auerbach, Hana Chocler, Shiri Moran - 

Formal methods are now successfully deployed in a variety of practical 

applications. But, significant challenges must be overcome to enable wider 

adoption. Presentations include verification of arbitration logic and bypass logic, a 

case study of formal versus structural verification, engineers’ suggestions for FV 

research, verification of a complex design with just three assertions, and formal 

IBM Haifa Research Lab., Haifa, Israel 

Viresh Paruthi - IBM Systems and Technology Group, Austin, TX 

8.4 The Wiggler’s Manifesto: What Formal Verification 

Engineers Really Need from EDA Research (4:45pm) 

Erik Seligman, Prakash Math, Tom Schubert - Intel Corp., Hillsboro, OR 

equivalence checking challenges of a supercomputer on chip. 

8.5 How we Verified 5000 Lines of a Complex Multiplexing 

8.1 Formal Verification of Arbitration Logic (4:00pm) 

Gadiel Auerbach, Fady Copty, Katia Patkin - 

IBM Haifa Research Lab., Haifa, Israel 

Krishnan Kailas - IBM T.J. Watson Research Ctr., Yorktown Heights, NY 

Viresh Paruthi - IBM Systems and Technology Group, Austin, TX 

Code with Three Assertions (5:00pm) 

Nalin Nimavat - Cisco Systems, Inc., San Jose, CA 

Vigyan Singhal - Oski Technology, Inc., Mountain View, CA 

8.6 Formal Equivalence Verification (FEV) Challenges 

of a Supercomputer-On-A-Chip (5:15pm) 

8.2 Deploying Model Checking for Bypass Verification (4:15pm) 

Vigyan Singhal, Prashant Aggarwal - Oski Technology, Inc., Gurgaon, India 

Amrendra Kumar, Pei-Wen Wu, Joonyoung Kim - Intel Corp., Santa Clara, CA 

Michelle Liu, Wanli Wu - Cisco Systems, Inc., San Jose, CA www.DAC.com 

33

USER TRACK 


9 

9:00 - 10:30am 

3:30 - 5:30pm 

Chair: 

Srinivas Nori - GLOBALFOUNDRIES, Sunnyvale, CA 

Complex clocking design and timing convergence continue to be top priorities in 

IC design. IBM, Samsung, and Juniper Networks showcase their approaches and 

successes in clock network design and timing analysis/convergence for advanced 

nodes. Presentations in this session include clock grid construction, clock mesh 

tuning, SSTA topics on pessimism removal and flexibility, and two convergence 

approaches for ECO routing and timing window reduction. 

11.1 Robust Clock Grid Construction for Non-Uniform Clock Loads (3:30pm) 

Nancy Y. Zhou, Joseph Palumbo, Joseph Kozhaya - IBM 

Systems and Technology Group, Durham, NC 

Zhuo Li, Cliff Sze - IBM Research - Austin, TX 

Haifeng Qian, Phillip Restle - IBM T.J. Watson 

Research Ctr., Yorktown Heights, NY 

34 

VERIFICATION METHODOLOGIES 

Chair: 

Rob Aitken - ARM, Inc., San Jose, CA 

As the scope of system integration increases, functional verification consumes an 

increasing percentage of design resources. This session includes presentations 

on several verification Methodologies. Topics include a discussion on what can be 

gained in moving from OVM to UVM, dealing with the lack of written specifications, 

solving SoC verification challenges with a UVM configuration mechanism, and 

optimizing transaction-based co-emulation performance. 

9.1 The Big Question - Stay with OVM or Move to UVM? (9:00am) 

Manikandan S, Suleesh Rajendran, Sunil Kumar - LSI Corp., Bangalore, India 

10 

1:30 - 3:00pm 

10.1 An ESL Power Flow for Optimizing and Validating the 

Power Management Strategy on a MultiCore SoC (1:30pm) 

Xiaotao Chen - Huawei Technologies Co., Ltd., Bridgewater, NJ 

Philippe Garrault, Sylvian Kaiser - DOCEA Power SAS, Moirans, France 

10.2 SyMX -- Model Crossover between Simics and 

SystemC/TLM Virtual System Platforms (1:45pm) 

Christian Sauer, Hans-Peter Loeb - 

Cadence Design Systems, Inc., Munich, Germany 

11 

CLOCKS AND TIMING 

Room: 303 


Sponsored by: 

APPLICATIONS OF VIRTUAL PLATFORMS 

Chair: 

Ismed Hartanto - Xilinx, Inc., San Jose, CA 

Room: 303 

Room: 303 

Virtual platforms are crucial for pre-silicon software development. They can also 

be used for architectural evaluation and exploration, as well as power modeling 

and optimization. This session includes two different ways of combining virtual 

platforms with a power modeling tool, along with a methodology for allowing reuse 

of models across both Simics and SystemC/TLM, and a system for creating and 

evaluating multiprocessor SoC platforms. 


9.2 “Spec is in Designer’s Head!” Problem Demystified (9:15am) 

Terry Lam, Viba Viswanathan, Yirng-An Chen - 

Marvell Semiconductor, Inc., Santa Clara, CA 

Nitin Mhaske - NextOp Software, Inc., Santa Clara, CA 

9.3 Advanced Applications of Resources: How we Solved our SoC 

Verification Challenges with UVM Configuration Mechanism (9:30am) 

Abhisek Verma, Parag Goel, Amit Sharma - Synopsys, Inc., Bangalore, India 

9.4 Optimizing Transaction-Based Co-Emulation Performance (9:45am) 

Takashi Kawabe - Konica Minolta Holdings, Inc., Hachioji-shi, Japan 

Mitsuhiro Matsumoto - Nihon EVE K.K., Yokohama-shi, Japan 

User Track - Embedded Systems and Software 

10.3 SiMPLiFy: An Abstract MPSoC Platform Framework for 

Enabling Fast Functional/Behavioral Simulation (2:00pm) 

Michael Huebner - Ruhr - Univ. of Bochum, Germany 

Gabriel M. Almeida, Jurgen Becker - 

Karlsruhe Institute of Technology, Karlsruhe, Germany 

Oliver B. Longhi, Fabiano Hessel - 

Pontifíca Univ. Católica do Rio Grande do Sul, Porto Alegre, Brazil 

10.4 Co-Simulation of a SystemC TLM Virtual Platform with a Power 

Simulator at the Architectural Level: Case of a Set-Top Box (2:15pm) 

Jerome Cornet, Laurent Maillet-Contoz - 

STMicroelectronics, Grenoble Cedex, France 

Ilija Materic, Hela Boussetta - DOCEA Power, Moirans, France 

Sylvian Kaiser - DOCEA Power SAS, Moirans, France 

Tayeb Bouhadiba - Verimag, Gieres, France 

Matthieu Moy, Florence Maraninchi - 

Grenoble Institute of Technology, Verimag, Gieres, France 


11.2 Design and Tuning of a Tree-Mesh Clock Distribution (3:45pm) 

Nikhil Jayakumar, Dave Murata, Valery Kugel - 

Juniper Networks, Inc., Sunnyvale, CA 

11.3 Pessimism Reduction in Statistical Timing Analysis Using 

Liberty Standard Extensions to Model OCV (4:00pm) 

Dileep Netrabile, Eric A. Foreman, Jeffrey G. Hemmett, Hemlata Gupta - 


11.4 The Flexibility of Statistical Timing (4:15pm) 

Stephen Shuma, Eric Foreman - IBM Corp., Essex Junction, VT 

11.5 ECO Routing Methodology for Timing Improvement (4:30pm) 

Gi-Joon Nam, Zhuo Li - IBM Research - Austin, TX 

Nancy Zhou, Mike Kazda - 

IBM Server and Technology Group, Hopewell Junction, NY 

11.6 A New Design Closure Methodology for Semicustom 

Circuit by Window Reduction (4:45pm) 

Hyung-Ock Kim - Samsung, Yongin, Republic of Korea

PERSPECTIVE PAPERS AT DAC 

“Perspectives” is a new submission category that solicits content traditionally not present in the conference: surveys, new problem 

formulations, critiques, comparative studies, and position papers. A Perspectives presentation provides a broader view than a traditional 

presentation, and brings excellent speakers to the conference. This year’s Perspectives include: 

3 

DESIGN AUTOMATION FOR THINGS WET, 

SMALL, SPOOKY, AND TAMABLE 

Tuesday, June 5 - 10:00 - 11:30am 

3.5 A Microgrid View of Energy Efficient Systems (11:00am) 


11 

FACING DEPENDABILITY: SYSTEM-LEVEL SOLUTIONS AND 

CYBERCAR CHALLENGES 

Tuesday, June 5 - 1:30 - 3:00pm 

11.5 EDA for Secure and Dependable Cybercars: Challenges and Opportunities (2:30pm) 


Ing. Ahmad-Reza Sadeghi, Hervé Seudié - Technische Univ. Darmstadt, Germany 

16 

IS FORMAL VERIFICATION READY FOR 

THE SYSTEM LEVEL? 

Tuesday, June 5 - 4:00 - 6:00pm 

16.5 Sciduction: Combining Induction, Deduction, and Structure for Verification and Synthesis (5:00pm) 

Sanjit A. Seshia - Univ. of California, Berkeley, CA 

27 

DESIGN, THE NEXT GENERATION: 

FROM ROUTING TO CAPTURING DESIGN EXPERTISE 

Wednesday, June 6 - 1:30 - 3:00pm 

27.5 Avoiding Game Over: Bringing Design to the Next Level (2:30pm) 

Mark Horowitz, Ofer Shacham, Megan Wachs, Andrew Danowitz, Sameh Galal, John Brunhaver, Wajahat Qadeer, 

Sabarish Sankaranarayanan, Artem Vassillev, Steve Richardson - Stanford Univ., Stanford, CA 

29 

SOS: SPECIFICATION, OPTIMIZATION, AND SYNTHESIS IN 

SYSTEM-LEVEL DESIGN 

Wednesday, June 6 - 1:30 - 3:00pm 

29.5 Embedded Systems - The Neural Backbone of Society (2:30pm) 


49 

PANEL: PARALLELIZATION AND SOFTWARE 

DEVELOPMENT: HOPE, HYPE, OR HORROR? 

Thursday, June 7 - 3:30 - 5:30pm 

Room: 300 

Room: 308 

Room: 306 

Room: 300 

Room: 308 

Room: 305 

49.1 PhD or MD - Who is Better Trained for Building Successful Software Development Tools? (2:45pm) 









TUTORIALS 

MONDAY, JUNE 4 

1 

36 

SYNTHESIZING SYSTEMC TO LAYOUT 

8:30 - 10:30am, 11:30am - 1:30pm, 

3:30 - 5:30pm 

Speaker: 

Michael A. Bohm - Intel Corp., Hillsboro, OR 

Capturing digital designs as RTL and synthesizing to layout has been the 

defacto standard for thirty years. Over the years our industry has been quite 

successful refining this process, driving industrial growth in SoC, ASIC, and 

FPGA implementations. At this point, significant further refinements of the 

RTL methodology are difficult to achieve. Further advancements in our design 

efficiency will require employing new methods. 

2 

Each tutorial below is presented multiple times to allow you to cover multiple topics. 

Additional Registration Fees Apply 

ENOUGH TALK! PRACTICAL APPROACHES TO 3-D IC - 

TSV/SILICON INTERPOSER AND WIDE IO IMPLEMENTATION 

FROM PEOPLE WHO HAVE BEEN THERE AND DONE THAT 

8:30 - 10:30am, 11:30am - 1:30pm, 

3:30 - 5:30pm 

Speakers: 

Frank Lee - Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan 

Marc Greenberg - Cadence Design Systems, Inc., Austin, TX 

3-D IC and Silicon Interposer with Through Silicon Via (TSV) and wide IO type 

of DRAMs have been hot topics for the last few years, because they offer 

a revolutionary increase in bandwidth and reduction in power for inter-chip 

communication especially for the critical GPU/CPU to DRAM connection. While 

there is some information available on what could be achieved with 3-D IC, the 

question is what is the most practical approach to utilizing the best of both worlds - 

3-D IC and Silicon Interposer with TSVs and wide IO technology. Given challenges 

with designing 3-D stacks with TSVs, testing 3-D stacks, the production process 

and the state of the ecosystem, the most practical solution today may be using 

Silicon Interposers to integrate wide IO memory with the logic device. 

3 

SYSTEM-LEVEL EXPLORATION OF POWER, TEMPERATURE, 

PERFORMANCE, AND AREA FOR MULTICORE ARCHITECTURES 

8:30 - 10:30am, 11:30am - 1:30pm, 

3:30 - 5:30pm 

Speakers: 

Houman Homayoun - Univ. of California at San Diego, La Jolla, CA 

Manish Arora - Univ. of California at San Diego, La Jolla, CA 

Amin Ansari - Univ. of Illinois at Urbana-Champaign, Urbana, IL 

Room: 310 

Room: 302 

Room: 305 

With the proliferation of multicore architectures, system designers critically need 

simulation tools to perform early design space exploration of different architectural 

configurations. Designers typically need to evaluate the effect of different applications 

on power, performance, temperature, area, and reliability of multicore architectures. 

While architectural simulators such as Simplescalar integrated with HotSpot and 

Wattch have been used in the past to perform design space evaluation, several 

factors drive the need for new tools to address both changes in technology as 

well as the proliferation of multicore processor architectures. Many new simulation 

frameworks are emerging that attempt to accurately model power, temperature, 



Many companies have had success building chips using the current third 

generation High-Level Synthesis (HLS) tools which accept SystemC as the input 

language. Leveraging these quite robust HLS tools facilitates an automated 

approach for developing digital designs where the HLS scheduling engine accepts 

the timing, power, and physical constraint information early in the design process, 

allowing efficient semi-automatic exploration of a circuits design space with tight 

correlation to the final layout. 

Building further on this process, we are moving test, power, and reliability issues 

earlier into the design flow in order to optimize a design directly for manufacturability. 

This tutorial will demonstrate a methodology that defines a recommended flow and 

identifies the issues and pitfalls involved in synthesizing a High-Level SystemC 

model to a placed gates layout. 


This tutorial session walks participants through what they really need to know to 

be successful in their first 3-D design project. We present a practical approach 

to helping them prepare for and execute a successful TSV design project utilizing 

Silicon Interposer and wide IO memory. We start at chip planning, die, IP, and tool 

selection, continue through thermal planning, chip design, inter-chip routing and/ 

or silicon interposer design, and finish with physical verification, manufacturing, 

assembly, packaging, and test. 


area, and timing characteristics. These tools allow accurate modeling the effects 

of deep-submicron technologies, as well as all accurately model the various 

subcomponents of these complex multicore platforms. 

This tutorial first briefly reviews the state of the art in simulators and modeling tools 

including; SMTSIM, GEM5, SESC as representative cycle accurate processor core 

performance simulators; DARSIM for cache interconnection network modeling 

and evaluation; HotSpot for thermal estimation; and CACTI and NVSIM for power 

and area modeling of various SRAM and NVM memory technologies and McPAT 

(Multicore Power, Area, and Timing) to model power, area, and timing of multicore 

architectures. The tutorial then presents example frameworks and workflows 

integrating these tools to allow the accurate modeling of various parameters of 

interest for state of the art multicore architectures.

TUTORIALS 

MONDAY, JUNE 4 

4 

Each tutorial below is presented multiple times to allow you to cover multiple topics. 


UNDERSTANDING AND OVERCOMING PATTERNING-INDUCED 

DESIGN CHALLENGES IN THE 20NM AND 

14NM TECHNOLOGY NODES 

8:30 - 10:30am, 11:30am - 1:30pm, 

3:30 - 5:30pm 

Speakers: 

Kuang-Kuo Lin - Samsung, San Jose, CA 

Vassilios Gerousis - Cadence Design Systems, Inc., San Jose, CA 

Lars Liebmann - IBM Corp., Hopewell Junction, NY 

Andres Torres - Mentor Graphics Corp., Wilsonville, OR 

5 

ANALOG AND MIXED-SIGNAL DESIGN AT 

ADVANCED PROCESS NODES 

8:30 - 10:30am, 11:30am - 1:30pm, 

3:30 - 5:30pm 

Speakers: 

Jim McMahon - Cadence Design Systems, Inc., San Jose, CA 

Erik Wanta - Freescale Semiconductor, Inc., Tempe, AZ 

Robert (Bob) Mullen - Taiwan Semiconductor 

Manufacturing Co., Ltd., San Jose, CA 

Stacy Whiteman - Cadence Design Systems, Inc., San Jose, CA 

Fang-Cheng Chang - Cadence Design Systems, Inc., San Jose, CA 

To take advantage of area and power reduction in advanced process node, analog 

designers must consider many issues not required in the past to be successful in 

realizing analog and mixed-signal circuits in silicon. Parametric variation, parasitic, 

layout dependent effects, and double patterning have a significant impact on 

performance of circuits at these geometries. Previously these were secondary, 

post design clean up issues; now they must be addressed from the earliest stages 

of the design in order to predict performance of the circuits in silicon and avoid 

costly design iterations. 

Scaling the devices down to 28/20nm and meeting specifications requires an 

advanced design flow which enables designers to explore the impact of the 

different effects during circuit design and make educated tradeoffs leading to 

design convergence through the layout and signoff stage. The flow must provide 

acceptable productivity and turn-around-time to meet the demanding-time-tomarket 

schedules. 

6 

PRE-SILICON, NATIVE EMBEDDED 

SOFTWARE DEVELOPMENT SOLUTIONS 

8:30 - 10:30am, 11:30am - 1:30pm, 

3:30 - 5:30pm 

Speakers: 

Robert Kaye - ARM, Inc., Cambridge, United Kingdom 

Jon McDonald - Mentor Graphics Corp., Wilsonville, OR 

Mark Mitchell - Mentor Graphics Corp., San Jose, CA 

Room: 307 

Room: 306 

Room: 309 

Emulation and virtual platforms enable hardware design teams to begin verification 

ahead of silicon. However, embedded software development and verification is 

increasingly a bottleneck. The challenge is to find a way for software developers 

to work within their native software environment, while relying on virtual and 

emulated representations of the design. 

This session will detail a process that enables the software and hardware teams to 

work in parallel, without requiring them to become experts in each other’s domain. 


With the delayed availability of extreme ultraviolet (EUV) lithography and other 

non-optical patterning techniques, the semiconductor industry is faced with having 

to manufacture deep below the resolution limit of existing lithography tools. Much 

attention is given to wafer cost increase for these aggressively scaled technologies, 

but the potential loss of design efficiency is equally daunting. This tutorial will 

provide insight into patterning challenges, the computational scaling techniques 

used to overcome these challenges, and the design implications resulting from 

these techniques, helping designers become more efficient with these leadingedge 

technology nodes. The tutorial will also review design and enablement 

infrastructure being put in place to minimize the impact that resolution-challenged 

technology nodes have on design efficiency and quality. 

This tutorial will present methodologies and techniques for: 

• Advanced statistical analysis 

• Early parasitic estimation and parasitic-aware implementation 

• Circuit sensitivity to Layout Dependent Effects (LDE) and LDE-aware layout 

• Identifying and addressing device reliability issues 

• Digitally assisted analog design 

Results of a 28/20nm analog/mixed signal flow validation as part of TSMC AMS 

initiative will be presented, as well. 

Participants completing this tutorial will understand the issues impacting scaling 

of analog circuits and a methodology to address them in order to be successful 

designing analog and mixed signal circuits at these advanced process nodes. 

Specifically, the tutorial will cover: 




Hardware: defining a system based on platform subsystem IP, the development 

and integration of hardware acceleration blocks, analyzing hardware performance 

criteria, verification of the SoC functionality, leveraging the embedded software to 

drive hardware verification. 

Software: the parallel development and validation of software within a native 

software development (ide, compile, debug) environment, enabling software 

developers to move seamlessly between various representations of the hardware 

flow, including virtual prototypes, emulation, simulation, prototypes, and real 

hardware. 

37

WORKSHOPS 

SUNDAY, JUNE 3 

38 


DAC INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL DESIGN OF 

AUTOMOTIVE ELECTRONICS/SOFTWARE 

8:30am - 5:30pm 

Organizers: 

Paolo Giusto - General Motors Company, Palo Alto, CA 

Arkadeb Ghosal - National Instruments Corp., Berkeley, CA 

Haibo Zeng - McGill Univ., Montreal, Quebec, Canada 

Workshop Chair: 

Alberto Sangiovanni-Vincentelli- Univ. of California, Berkeley, CA 

Workshop Advisory Board: 

Raj Rajkumar - Carnegie Mellon Univ., Pittsburgh, PA 


Marco Di Natale - Scuola Superiore Sant’Anna, Pisa, Italy 

Speakers: 

Roger Melen - Toyota Motor Corp., Mountain View, CA 

Christopher Oster - Lockheed Martin Corp., Philadelphia, PA 

Raj Rajkumar - Carnegie Mellon Univ., Pittsburgh, PA 

Marco Di Natale - Scuola Superiore Sant’Anna, Pisa, Italy 

Graham Hellestrand - EST Embedded Systems Technology, Los Altos, CA 

In the last two decades, in-vehicle electronics and software content have increased 

at a faster rate than ever to address market demands for increasingly complex 

customer features (e.g., lane keeping) as well as tighter government regulations 

(e.g., fuel economy). The entire in-vehicle electronics and software eco-system 

(industry and academia) has been impacted. The automotive industry has faced 

Room: 306 


design and business challenges to address the market and government regulations, 

while maintaining profitability. The challenges include changing supply chain roles 

(e.g., adding new AUTOSAR software providers), increasing the amount of software 

integration with several parties involved, and providing the ability to control the 

system-level requirements in the context of IP-protected/black-box supply chains. 

While some of these challenges have been addressed in other markets (such as in 

aerospace and by the EDA/ESL tool industry) in the past, others are quite automotivespecific. 

Academia has researched and developed methods and tools in this area for 

many years. 

Standardization efforts to enable competition on customer features and remove it 

from infrastructure software and networking have emerged (e.g., FlexRay, AUTOSAR, 

and ISO26262). Standards can enable re-use of software components, and enable 

system-level modeling, analysis, simulation, and optimization of hardware and 

software for in-vehicle architectures prior to the availability of the actual components. 

This workshop focuses on the past, present, and potential future landscape of systemlevel 

design with emphasis on the potential opportunities for the EDA/ESL industry and 

academia in providing tool support for modeling, analysis, simulation, and optimization 

of hardware and software automotive architectures. The workshop will cover the 

automotive industry requirements, the relationships and similarities with the aerospace 

industry, as well as the EDA/ESL industry and academia efforts in this area. 

DAC WORKSHOP ON THE FOURTH INTERNATIONAL WORKSHOP 

ON BIO-DESIGN AUTOMATION AT DAC 

Sunday, 9:00am - 5:00pm - 

Monday, 10:30am - 6:30pm 

General Chair: 

Natasa Miskov-Zivanov - Univ. of Pittsburgh, PA 

General Secretary: 

Laura Adam - Virginia Polytechnic Institute and State Univ., Blacksburg, VA 

Program Committee Chairs: 

Xiling Shen - Cornell Univ., Ithaca, NY, Deepak 

Chandran - Univ. of Washington, Seattle, WA 

Leonidas Bleris - Univ. of Texas, Dallas, TX 

Publication Chair: 

Chris Myers - Univ. of Utah, Salt Lake City, UT 

Industry Liaison Chair: 

Jonathan Babb - Massachusetts Institute of Technology, Cambridge, MA 

Finance Chair: 

Aaron Adler - BBN Technologies, Cambridge, MA 

Fusun Yaman - BBN Technologies, Cambridge, MA 

DAC Liaison: 

Smita Krishnaswamy - Columbia Univ., New York, NY 

Speakers: 

Jasmin Fisher - Microsoft Corp., Cambridge, United Kingdom 

William Shih - Harvard Univ., Boston, MA 

Milan Stojanovic - Columbia Univ., New York, NY 

Room: 308 


The Fourth International Workshop on Bio-Design Automation (IWBDA) brings 

together researchers from the synthetic biology, systems biology, and design 

automation communities. The focus is on concepts, methodologies and software 

tools for the computational analysis of biological systems and the synthesis of novel 

biological systems. 

Still in its early stages, the field of synthetic biology has been driven by experimental 

expertise; much of its success has been attributable to the skill of the researchers 

in specific domains of biology. There has been a concerted effort to assemble 

repositories of standardized components. However, creating and integrating synthetic 

components remains an ad hoc process. The field has now reached a stage where 

it calls for computer-aided design tools. The electronic design automation (EDA) 

community has unique expertise to contribute to this endeavor. This workshop offers a 

forum for cross-disciplinary discussion, with the aim of seeding collaboration between 

the research communities. 

Topics of interest include: 

• Design methodologies for synthetic biology. 

• Standardization of biological components. 

• Automated assembly techniques. 

• Computer-aided modeling and abstraction techniques. 

• Engineering methods inspired by biology. 

DAC WORKSHOP ON CMOS DESIGN AT 60 GHZ AND BEYOND: 

CAPABILITIES AND CHALLENGES 

8:30am - 12:30pm Room: 305 Analog/Mixed-Signal/RF Design 

Organizers: 

Sotiris Bantas - Helic, Inc., San Francisco, CA 

Robert Mullen - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA 

Speakers: 

Robert Mullen - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA 

Sohrab Emami - Silicon Image, Inc., Sunnyvale, CA 

Sotiris Bantas - Helic, Inc., San Francisco, CA 

Georges Gielen - Katholieke Univ. Leuven, Belgium 

Sharad Kapur - Integrand Software, Inc., Berkeley Heights, NJ 

The anticipated proliferation of multi-gigabit applications in the 60GHz band 

(e.g. uncompressed video transmission, rapid file transfers) marks an uptick in 

millimeter-wave CMOS design. But are EDA vendors and silicon foundries ready to 

resolve the related challenges? This workshop brings together stakeholders from 

across the silicon design ecosystem to provide the audience with a comprehensive 

treatment of the subject. 

The workshop will address the challenges posed by CMOS design in the 60-GHz 

band and beyond, as well as the techniques being developed to address them by the 

ecosystem of IC designers, silicon providers, EDA tool vendors and research institutions. 

Presenters will offer examples from real silicon cases, discuss system-level aspects, 

outline design tool methodologies and address areas for further research. 

www.DAC.com

WORKSHOPS 



DAC WORKSHOP ON MORE THAN MOORE TECHNOLOGIES 

8:30am - 6:00pm 

Organizer: 

Rasit Topaloglu - IBM Corp., East Fishkill, NY 

Speakers: 

Kaushik Roy - Purdue Univ., Lafayette, IN 

Tim Cheng - Univ. of California, Santa Barbara, CA 

Andrew Kahng - Univ. of California at San Diego, La Jolla, CA 

Sung Kyu Lim - Georgia Institute of Technology, Atlanta, GA 

Yuan Xie - Pennsylvania State Univ., University Park, PA 

Yiyu Shi - Missouri Univ. of Science and Technology, Rolla, MO 

Paul Franzon - North Carolina State Univ., Raleigh, NC 

Mike Garner - Stanford Univ., Stanford, CA 

Luca Carloni - Columbia Univ., New York, NY 

Rajiv Joshi - IBM Corp., Yorktown Heights, NY 

Seung Kang - Qualcomm, Inc., San Diego, CA 

Keren Bergman - Columbia Univ., New York, NY 

Onur Mutlu - Carnegie Mellon Univ., Pittsburgh, PA 

In order to align with system and device performance roadmaps and expectations, 

semiconductor devices scale to smaller dimensions with each generation. During 

scaling, electrical performance such as drive current needs to improve as well. 

While engineers have been successful to help devices scale, various innovations 

have been implemented along with algorithmic, computational, modeling solutions 

to the problems that they bring along. Examples of such important innovations 

that have been most relevant to the EDA and modeling domain have been stress 

modeling and optimization since 65 nm or double patterning since 22 nm. 

Reaching 10 nm technology may require extreme ultra violet lithography and 

there is not much certainty into what may lead us below 10 nm. Even if such 

a transition occurs, there seems to be an increasing gap between what can be 

achieved with traditional scaling versus system-level expectations. For example, 

memory latencies and hierarchies are lagging due to large interconnect delays in 

larger systems. Such system-level challenges cannot be targeted by traditional 

Moore scaling. 

DAC WORKSHOP ON COMPUTING IN HETEROGENEOUS, 

AUTONOMOUS ‘N’ GOAL-ORIENTED ENVIRONMENTS - (CHANGE) 

8:30am - 6:00pm 

Organizers: 

Marco Santambrogio - Politecnico di Milano, Italy 

Hank Hoffmann - Massachusetts Institute of Technology, Boston, MA 

Simone Campanoni - Harvard Univ., Boston, MA 

Martina Maggio - Lund Univ., Sweden 

Speakers: 

Satnam Singh - Google, Inc., Mountain View, CA 

Jonathan Eastep - Intel Corp., Portland, OR 

John Kubiatowicz - Univ. of California, Berkeley, CA 

Jian Li - IBM Research - Austin, TX 

Xiaoyuan Zhu - VMware, Inc., San Francisco, CA 

Heterogeneous, adaptable multicore systems can be considered the established 

trend in modern computing architectures. Silicon resources are increasingly 

abundant, runtime reconfigurable elements can be combined together with 

heterogeneous processing elements and many cores on a chip by processor 

designers. Such architectures provide important improvements in system 

performance, but also pose new research questions to be answered, i.e. will 

current processor interconnection mechanisms scale to thousands of cores? How 

can the runtime behavior, which cannot be fully understood at design time, be 

captured to be reflected into a physical implementation to extract high performance 

from the underlying hardware architecture? 

In this scenario, imagine a revolutionary computing system that can observe its 

own execution and optimize its behavior around a user’s or application’s needs. 

Imagine a programming capability by which users can specify their desired goals 

rather than how to perform a task, along with constraints in terms of an energy 

budget, accuracy and execution time. Imagine further a computing system that 

Room: 309 

Room: 307 

We propose a workshop with the key goal of discussing about potential More-than- 

Moore solutions and modeling and EDA challenges they bring. After identifying 

such challenges, we then discuss about potential solutions to such EDA problems. 

The workshop enables multiple More-than-Moore solutions to be discussed in the 

same place, thereby giving the opportunity to evaluate their impact at the system level. 

For this workshop, we have identified three particular areas to focus on based 

on their likelihood and potential impact. These are 1) 3-D integration, 2) Novel 

memories, and 3) On-chip optics. From each area, we invite leading experts from 

industry and academia for presentations. These presentations are followed by a 

panel and a poster session, where additional contributions outside our invitee list 

will have a chance to be represented. 

Presented papers and posters will be considered for a special issue magazine or 

journal at a later date. 

Panel: “Are Models and Design Flows Ready for More than Moore?” 

Panelists: 

Samta Bansal - Cadence Design Systems, Inc., San Jose, CA 

Herb Reiter - eda2asic Consulting, Inc., San Jose, CA 

Seung Kang - Qualcomm, Inc., San Diego, CA 

Leon Stok - IBM Corp., Hopewell Junction, NY 

Valeriy Sukharev - Mentor Graphics Corp., San Jose, CA 

Noel Menezes - Intel Corp., Hillsboro, OR 



executes more efficiently the longer it runs an application. Such a system will 

enable, for example, a handheld radio or a cell phone that can run cooler the 

longer the connection time, a computer-farm that save energy autonomously 

based on the computation, a recycling spot that improve its way of managing and 

treating different kind of waste the longer it works. 

Self-aware computer systems are the key technology to succeed in doing this. 

They will be able to configure, heal, optimize, improve interaction and protect 

themselves without the need for human intervention, exploiting abilities that 

allow them to automatically find the best way to accomplish a given goal with the 

resources at hand. Within this context, imagine a revolutionary computing system 

that can observe its own execution and optimize its behavior around the external 

environment, user’s and application’s needs. 

The Self-aware computing research leverages the new balance of resources 

to improve performance, utilization, reliability and programmability. Within this 

context, the proposed workshop is intended to present innovative works describing: 

• Self-aware Operating Systems 

• Autonomous self-aware computer architecture 

• Adaptive algorithm and distributed self-training algorithms 

• Biologically inspired systems 

• Surveys and/or prospective papers in self-aware computing systems 


WORKSHOPS 


40 


DAC WORKSHOP ON EDA ON PROCESS AUTOMATION 

9:00am - 4:00pm 

Organizer: 

Michael Hübner - Ruhr - Univ. of Bochum, Germany 

Speakers: 

Joris Pascal - ABB Group, Daetwil, Switzerland 

Diana Göhringer - Karlsruhe Institute of Technology, Karlsruhe, Germany 

Dagan White - Xilinx, Inc., San Jose, CA 

Process automation is a worldwide growing topic in industrial and academic 

research and development. Especially the hard constraints for power consumption, 

real-time, extreme high reliability and low costs lead to a nearly unlimited design 

space which needs to be handled with novel design methodologies from EDA. 

Room: 310 

YOUNG FACULTY WORKSHOP AT DAC 

Organizers: 

Steven Levitan - Univ. of Pittsburgh, PA 

Soha Hassoun - Tufts Univ., Medford, MA 

Kartik Mohanram - Univ. of Pittsburgh, PA 

This is a special workshop organized for current, or soon to be, young faculty in 

the fields of electronic design automation (EDA). The workshop will be organized 

as presentations by EDA senior professionals around six themes, with additional 

opportunities to network with some of the established researchers and funding 

officers in the field of Electronic Design Automation. 



This workshop is about the latest technologies for highly energy efficient hardware 

and the required design tools. Design and technology in process automation is at 

its limit. Novel technologies coming from ultra low power multicore technologies, 

also reconfigurable hardware are a relevant topic in industrial and academic 

research and development. 

The design space, even if limited by hard constraints, are no longer manageable 

by the designer. Especially if also novel processor cores, sometimes a number 

of heterogeneous cores are used to run a system. Hardware / software codesign 

will be in future a topic in this domain and opens a variety of scientific questions 

to be answered. 

9:00am - 6:00pm Room: 301 Other 


The themes this year include: Getting an Academic Job, Research - papers, 

conferences and grants, The NSF proposal process for CAREER and other 

programs, Teaching - Best practices, Special Issues and a “Speed Networking” 

lunch event. There is a limited budget for travel support for attendees. 

Visit DAC website for additional event details. 

DAC WORKSHOP ON POST-SILICON DEBUG: 

TECHNOLOGIES, METHODOLOGIES, AND BEST-PRACTICES 

9:00am - 3:00pm Room: 309 Verification and Test 

Moderator: 

Harry Foster - Mentor Graphics Corp., Plano, TX 

Organizer: 

Amir Nahir - IBM Haifa Research Lab., Haifa, Israel 

Speakers: 

Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada 


Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI 

Sharad Kumar - Freescale Semiconductor, Inc., Noida, India 

Bradley Quinton - Tektronix, Inc., Vancouver, BC, Canada 

Eric Rentschler - Advanced Micro Devices, Inc., Fort Collins, CO 

Keshavan Tiruvallur - Intel Corp., Portland, OR 


Kevin Reick - IBM Corp., Austin, TX 

Wisam Kadry - IBM Haifa Research Lab., Haifa, Israel 

As the complexity of digital systems grow, designing and manufacturing a fully 

functional system becomes harder and harder. Despite on-going improvements 

to pre-silicon verification practices and technologies, they alone can no longer 

meet the verification goals. As a result, a significant part of the verification is now 

executed on actual silicon, as part of the system’s bring-up. 

special interest group on 

design automation 

Performing verification on real silicon introduces new and different challenges. 

On the one hand, real silicon offers great execution speed; on the other hand, 

it is lacking the controllability and observability which serve an important role in 

pre-silicon verification. 

The lack of observability into the design makes the task of debugging a fail 

observed in the lab to be of extreme complexity. Current practice significantly 

relies on designer expertise, tremendous labor, and is in many cases - pure luck.In 

recent years several methods and mechanisms have been proposed for the sake 

of easing the debug task. Since adding debug logic to the actual silicon is costly 

(in area and power), this brings about the challenge of determining the optimal way 

of instrumenting the design for silicon debug while using the minimal amount of 

required additions to the logic. 

This workshop brings together experts from academia and industry to present 

different instrumentation strategies, as well as the methods of using the data 

collected by the debug logic to facilitate fast and efficient debug.

ROUTABILITY-DRIVEN PLACEMENT 

CONTEST POSTER PRESENTATION 

WEDNESDAY, JUNE 6 - 6:00 - 7:00pm - Esplanade Foyer 

1. Team Name: Ripple 

Team Affiliation: The Chinese University of Hong Kong 

Team Members: Xu He, Tao Huang, Wing-Kai, 

Chow, Yuan Jiang, Evangeline F.Y. Young 

2. Team Name: mPL12 

Team Affiliation: UCLA / Beijing University 

Team Members: Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao 

3. Team Name: SimPLR 

Team Affiliation: The University of Michigan, Ann Arbor 

Team Members: Myung-Chul Kim, Jin Hu, Igor Markov 

4. Team Name: NTUplace4 

Team Affiliation: National Taiwan University 

Team Members: Meng-Kai Hsu, Yao-Wen Chang 

5. Team Name: NCKU-Placer 

Team Affiliation: National Cheng Kung University 

Team Members: Chung-Lin Lee, Sheng-Wen 

Chen, Kai-Chung Chan, Jing-Chang Wang 

6. Team Name: VDAPlace 

Team Affiliation: National Chiao Tung University 

Team Members: Sean Shih-Ying Liu, Ching-Yu Chin, Sheng-De Hu 

Co-Sponsored by: 

7. Team Name: LUCASTE_PDT 

Team Affiliation: Politecnico di Torino 

Team Members: Luca Sterpone 

8. Team Name: Allecon 

Team Affiliation: Tsinghua University 

Team Members: Zhongdong Qi, Wenchao Gao, Sifei Wang, Zekun Wu 

9. Team Name: UIPlacer 

Team Affiliation: University of Illinois at Urbana-Champaign 

Team Members: Haitong Tian, Zigang Xiao 

10. Team Name: Goal 

Team Affiliation: Department of Computer Science, 

National Chiao Tung University 

Team Members: Tsung-Han Wu, Shih-Tsang Liao, Ke-Ren Dai 

11. Team Name: NCUplacer 

Team Affiliation: Department of Electrical 

Engineering, National Central University 

Team Members: Tai-Chen Chen, Kuo-Ting Liu, Pei-Yu Lee 


WORK-IN-PROGRESS (WIP) 

WEDNESDAY, JUNE 6 6:00 - 7:00pm Esplanade Foyer 

Chair: 

Tajana Simunic - Univ. of California at San Diego, La Jolla, CA 

55.1 CaaS: Core as a ServiceBring SOA to 

Reconfigurable MPSoC for Chip Level Parallelization 

Chao Wang, Peng Chen, Xi Li, Junneng Zhang, Xiaojing Feng, Xuehai 

Zhou - Univ. of Science and Technology of China, Suzhou, China 

55.2 TSV-Based On-Chip Spiral Inductor and 

Near-Field Wireless Communications 

Khaled Mohamed, Alaa E. El-Rouby - Mentor 

Graphics Corp., Cairo, Egypt 

Yehea Ismail, Hani Ragai - American Univ. of Cairo, Egypt 

55.3 Splogd: An Open Source Hardware Description 

Language for Android OS Platform 

Anirban Chatterjee - BITS Pilani, Bangalore, India 

55.4 Systematic Comparison of Analog Circuits 

Through Dual Topological-Symbolic Matching 

Alex Doboli, Cristian Ferent - State Univ.of New York, 

Stony Brook, NY 

55.5 Two New Finite-State Machine-Based Topologies for 

Synthesizing Target Functions in Stochastic Computing 

Peng Li, David J. Lilja, Marc Riedel, Kia Bazargan 

- Univ. of Minnesota, Minneapolis, MN 

Weikang Qian - Shanghai Jiao Tong Univ., Shanghai, China 

55.6 A Multicore Architecture for Control and Emulation 

of Power Electronics and Smart Grid Systems 

Michel A. Kinsy, Jason Poon, Ivan Celanovic, Omer Khan, Srinivas 

Devadas - Massachusetts Institute of Technology, Cambridge, MA 

55.7 Addressing FPGA Design, Verification, and Debug 

Productivity Challenges through Increased Abstraction 

Bradley R. Quinton, Steven Wilton - Tektronix, Inc., 

Vancouver, BC, Canada 

Eddie Hung - Univ. of British Columbia, Vancouver, BC, Canada 

55.8 Breaking the Curse of High Dimensionality: An Efficient 

Rare-Event Estimation Algorithm in High Dimension 


Fang Gong, Lara Dolecek, Lei He - Univ. of California, 

Los Angeles, CA 

55.9 Co-Synthesis of Data Paths and Clock 

Control Paths for Clock Period Minimization 

Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng - 

Chung Yuan Christian Univ., Chung Li, Taiwan 

55.10 ODT - Dependence Tracking in Multicore 

Processors for Post-Silicon Debug 

Matteo Monchiero, Intel Corp., Santa Clara, CA 

Javier Carretero Casado,Tanausu Ramirez, Enric Herrero, Xavier Vera 

- Intel Corp., Barcelona, Spain 

Charan Sundararaman - Intel Corp., Hillsboro, OR 

55.11 Register and Thread Parallelism 

Optimization for GPGPU 

Yun Liang, Zheng Cui, Kyle Rupnow - Advanced 

Digital Sciences Center, Singapore 

Deming Chen - Univ. of Illinois at Urbana-Champaign, Urbana, IL 

42 


55.12 A Regression-Based Entropy Distiller for RO PUFs 

Chi-En Yin, Gang Qu - Univ. of Maryland, College Park, MD 

55.13 LASIC: Loop-Aware Sleepy Instruction 

Caches Based on STT-RAM Technology 

Junwhan Ahn, Kiyoung Choi - Seoul National Univ., 

Seoul, Republic of Korea 

55.14 Vertical Arbitration-free 3-D NoCs 

Ankit More, Baris Taskin - Drexel Univ., Philadelphia, PA 

55.15 Compiler Techniques for Energy 

Efficiency and Real-Time Guarantees 

Emilio Wuerges, Romulo Silva de Oliveira, Luiz C.V. Santos 

- Univ. Federal de Santa Catarina, Florianopolis, Brazil 

55.16 Extend Amdahl?s Law to Achieve Loading 

Balance in Heterogeneous On-Chip Clusters 

Chao Wang, Xi Li, Junneng Zhang, Xuehai Zhou - Univ. 

of Science and Technology of China, Suzhou, China 

55.17 Segmented and Adaptive NoC Architecture for 

Multi-Systems on Chip with Scalable Multicore 

Hsiang-Jen Tsai, Tien-Fu Chen, Chien-Chih Chen 

- National Chiao Tung Univ., HsinChu, Taiwan 

55.18 Using a Hardware Description Language as an 

Alternative to Printed Circuit Board Schematic Capture 

Bradley Riching, Brent E. Nelson, Richard Black - 

Brigham Young Univ., Provo, UT 

55.19 Towards Symbolic Loop Parallelization 

for Tightly-Coupled Processor Arrays 

Frank Hannig, Alexandru Tanase, Jürgen Teich - 

Univ. of Erlangen-Nuremberg, Germany 

55.20 Interactive Host-Assisted Execution 

Framework for Wireless Sensor Nodes 

Ahmad Abiri, Pai H. Chou - Univ. of California, Irvine, CA 

55.21 TinySPICE: A Parallel SPICE Simulator on GPU 

for Massively Repeated Small Circuit Simulations 

Lengfei Han, Xueqian Zhao, Zhuo Feng - Michigan 

Technological Univ., Houghton, MI 

55.22 Domain Wall Memory Based Cache 

Rangharajan Venkatesan, Vivek Kozhikkottu, Kaushik Roy, 

Anand Raghunathan - Purdue Univ., West Lafayette, IN 

Charles Augustine, Arijit Raychowdhury - Intel Corp., Hillsboro, OR 

55.23 Symbolic Analysis-Based Iterative 

Memory Partitioning for Generating Custom, 

Multi-Level Cache Hierarchies 

Emre Kultursay, Mahmut Kandemir - Pennsylvania 

State Univ., University Park, PA 

Kemal Ebcioglu - Global Supercomputing, Yorktown Heights, NY



55.24 Pin Density-Driven Placement for 

Routing Congestion Reduction 

Kalliopi Tsota, Jason Cong, Bingjun Xiao - 

Univ. of California, Los Angeles, CA 

Guojie Luo - Peking Univ., Beijing, China 

55.25 Relaxing Writes in Non-Volatile Processor 

Cache using Frequent Value Locality 

Mohammad Arjomand, Hamid Sarbazi-Azad, 

Amin Jadidi - Sharif Univ. of Technology, Tehran, Iran 

55.26 A Fine-Grained Dynamic Power Management 

of DRAM/PRAM-Based Main Memory 

Hyunsun Park, Sungjoo Yoo - Pohang Univ. of Science 

and Technology, Pohang, Republic of Korea 

55.27 Retiming for Soft Error Optimization 

Under Error-Latching Window Constraints 

Yinghai Lu - Synopsys, Inc., Mountain View, CA 

Hai Zhou - Northwestern Univ., Evanston, IL 

55.28 ARGO: An Application-Specific Run-Time Goal 

Management Framework for Multiprocessors Architectures 

Vittorio Zaccaria, Cristina Silvano, Vincenzo Consales, Gianluca 

Palermo, Andrea Di Gesare, Iyad Al Khatib - Politecnico di Milano, Italy 

Chantal Ykman-Couvreur - IMEC, Leuven, Belgium 

55.29 On Flexible Trace Interconnection 

Fabric Design for Silicon Debug 

Qiang Xu, Xiao Liu - The Chinese Univ. of Hong Kong, 

Shatin, Hong Kong 

55.30 Towards Cost Effective Multi-Core Processor 

Platforms Using 3-D Stacking Technology 

Alessandro Cevrero, Giulia Beanato, Panagiotis 

Athanasopoulos, Yusuf Leblebici - Ecole Polytechnique 

Fédérale de Lausanne, Switzerland 

55.31 DMR3D: Dynamic Memory Relocation 

in 3-D Multicore Systems 

Koushik Chakraborty, Dean Michael Ancajas, 

Sanghamitra Roy - Utah State Univ., Logan, UT 

55.32 Parallel Preconditioners Based on Fast Poisson 

Solvers for Efficient Large-Scale Power Grid Analysis 

Konstantis Daloukas, Maria-Aikaterini Rammou, George A. 

Drasidis, Michalis Tsiampas, Nestoras Evmorfopoulos, Panagiota 

Tsompanopoulou, George Stamoulis - Univ. of Thessaly, Volos, Greece 

55.33 Interval Arithmetic Based Input Vector Control 

for RTL Subthreshold Leakage Minimization 

Shilpa Pendyala, Srinivas Katkoori - Univ. of South Florida, Tampa, FL 

55.34 QoS-Aware Real-Time Scheduling 

for Energy Harvesting Systems 

Hessam Kooti, Nga Dang, Deepak Mishra, Eli Bozorgzadeh - 

Univ. of California, Irvine, CA 

55.35 A Multi-Controller Design for Solid-State Drives 

Chin-Hsien Wu, Jhih-Jian Liao - 

National Taiwan Univ. of Science and Technology, Taipei, Taiwan 

55.36 Automatic TLM Model Generation for 

Cycle-Count-Accurate Bus Simulation 

Chen-Kang Lo, Mao-Lin Li, Shu-Yung Chen, Ren-Song 

Tsay - National Tsing Hua Univ., HsinChu, Taiwan 

Jen-Chieh Yeh - Industrial Technology Research Institute, 

Hsinchu, Taiwan 

55.37 An RSM-Guided Exploration Framework 

for Custom Coprocessor Synthesis 

Vittorio Zaccaria, Cristina Silvano, Sotirios Xydis, 

Gianluca Palermo - Politecnico di Milano, Italy 

55.38 A Design Space Exploration Prototype for 

Run-Time Support on Manycore Architectures 

Cristina Silvano, Vittorio Zaccaria, Sotirios Xydis, Gianluca 

Palermo, Iyad Al Khatib - Politecnico di Milano, Italy 

Chantal Ykman-Couvreur - IMEC, Leuven, Belgium 

Alex Bartzas, Dimitrios Soudris - National 

Technical Univ. of Athens, Greece 

55.39 A Methodology for the High-Level 

Synthesis of Iterative Algorithms 

Alessandro A. Nacci, Francesco Bruschi, Vincenzo Rana - 

Politecnico di Milano, Italy 

55.40 VeriTrust: Verification for Hardware Trust 

Jie Zhang, Qiang Xu, Feng Yuan - The Chinese 

Univ. of Hong Kong, Shatin, Hong Kong 

55.41 Scalable Parallel Event-Driven 

HDL Simulation for Multi Cores 

Seiyang Yang - Pusan Univ., Pusan, Republic of Korea 

Tariq B. Ahmad, Maciej Ciesielski - 

Univ. of Massachusetts, Amherst, MA 

Namdo Kim, Byeong Min - Samsung, Yongin-City, Republic of Korea 

Apurva Kalia - Cadence Design Systems, Inc., Noida, India 

55.42 Electro-Thermal Analysis of 3-D 

Power Delivery Networks 

Aida Todri, Patrick Girard, Alberto Bosio, Luigi Dillilo, 

Arnaud Virazel - LIRMM, Montpellier, France 

Sandip Kundu - Univ. of Massachusetts, Amherst, MA 

55.43 Automated Architectural Synthesis of Flow- 

Based Microfluidic Large-Scale Integration Biochips 

Wajid H. Minhass, Paul Pop, Jan Madsen - 

Technical Univ. of Denmark, Kongens Lyngby, Denmark 

55.44 Efficient Software-Based Fault Tolerance 

Approach on Multicore Platforms 

Koen Bertels, Hamid Mushtaq - Delft Univ. of Technology, 

Delft, The Netherlands 

55.45 Detecting Delay Faults with Logic Implications 

Kundan Nepal - Univ. of St. Thomas, St. Paul, MN 

Jennifer Dworak - Southern Methodist Univ., Dallas, TX 

Iris Bahar - Brown Univ., Providence, RI 

55.46 A Virtual Write Buffer in Last Level 

Cache for STT-RAM Based Main Memory 

Younggeun Choi, Sungjoo Yoo - Pohang Univ. of Science 





55.47 Layout Small-Angle Rotation and 

Shift for EUV Defect Mitigation 

Hongbo Zhang, Yuelin Du, Martin D. F. Wong - Univ. 

of Illinois at Urbana-Champaign, Urbana, IL 

Yunfei Deng - GLOBALFOUNDRIES, Sunnyvale, CA 

Pawitter Mangat - GLOBALFOUNDRIES, Malta, NY 

55.48 Detecting Systematic Defects with 

Diagnosis-Based Comparison 

Bharath Seshadri, Puneet Gupta, Bruce Cory 

- NVIDIA Corp., Santa Clara, CA 

55.49 Exploiting the Task-Pipelined Parallelism 

of Stream Programs on Many-Core GPUs 

Shuai Mu, Yubei Chen, Yangdong Deng - 

Tsinghua Univ., Beijing, China 

Dongdong Li - Beihang Univ., Beijing, China 

55.50 Multi-Target Design Space Exploration 

for FPGA-Based Multiprocessors 

Peng Chen, Chao Wang, Xi Li, Junneng Zhang, 

Xiaojing Feng, Xuehai Zhou - Univ. of Science 

and Technology of China, Suzhou, China 

55.51 Game-Driven Discovery of New Mapping 

Strategies for Custom Domain-Specific Architectures 

Gayatri Mehta, Samuel Cook, Krunalkumar Patel, Brandon 

J. Rodgers, Anil Yadav - Univ. of North Texas, Denton, TX 

Carson Crawford - Univ. of Nebraska, Lincoln, NE 

Adeola Odunsi - Jackson State Univ., Decatur, IL 

55.52 SIMD Performance and Yield Optimization 

with Multi-Granularity Redundancy 

Brett H. Meyer - McGill Univ., Montréal, QC, Canada 

Daniel A. Epstein, Kevin Skadron - Univ. of Virginia, Charlottesville, VA 

55.53 Single Pin Redundancy for 

Robust Power Grid Delivery 

Sheldon Logan, Matthew Guthaus - Univ. of California, 

Santa Cruz, CA 

55.54 Emulating Analog/Mixed-Signal Circuits with a 

45nm Discrete-Sized Programmable Device Array 

Naveen Suda, Cheng Xu, Jounghyuk Suh, Yu Cao, 

Bertan Bakkaloglu - Arizona State Univ., Tempe, AZ 


55.55 OpenMP-Based Synergistic Parallelization 

and Hardware Acceleration for On-Chip 

Multi-Core Shared-Memory Clusters 

Andrea Marongiu, Paolo Burgio, Luca Benini - Univ. di Bologna, Italy 

Cyrille Chavet, Dominique Heller, Philippe Coussy 

- Univ. de Bretagne SUD, Lorient, France 

55.56 Deadline-Constrained Scheduling of Charge Migration 

Tasks in Hybrid Electrical Energy Storage Systems 

Di Zhu, Qing Xie, Yangzhi Wang, Massoud Pedram - 


Younghyun Kim, Naehyuck Chang - Seoul 

National Univ., Seoul, Republic of Korea 

44 


55.57 Kendall Syndrome Coding (KSC) for Group-Based 

Ring-Oscillator Physical Unclonable Functions 

Chi-En Yin, Gang Qu - Univ. of Maryland, College Park, MD 

55.58 Bias Runaway: An Emerging Reliability Threat 

in Scaled Analog and Mixed Signal Design 

Ketul B. Sutaria, Jyothi B. Velamala, Sule Ozev, 


55.59 InTimeFix: A Low-Cost and Scalable Technique 

for In-Situ Timing Error Masking in Logic Circuits 

Feng Yuan, Qiang Xu - The Chinese Univ. of Hong Kong, 

Shatin, Hong Kong 

55.60 Self-Aligned Double and Quadruple 

Patterning Aware Grid Routing Methods 

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, 

Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji 

Miyamoto - Toshiba Corp., Yokohama, Japan 

55.61 Redundancy and ECC Mechanisms to Improve 

Energy Efficiency of On-Die Interconnects 

Alaa R. Alameldeen - Intel Corp., Hillsboro, OR 

Amr Helmy - American Univ. of Cairo, Egypt 

55.62 Modeling and Synthesis of Energy- 

Optimal Approximate Adders 

Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky - 

Univ. of Texas, Austin, TX 

55.63 The Effects of Temperature on 

Timing in 3-D Integrated Circuits 

Sravan K. Marella, Sanjay V. Kumar, Sachin S. 

Sapatnekar - Univ. of Minnesota, Minneapolis, MN 

55.64 Efficient Retention Register 

Assignment for Power Gated Designs 


Yu-Guang Chen, Kuan-Yu Lai, Shih-Chieh Chang - 

National Tsing Hua Univ., Hsinchu, Taiwan 

55.65 A Fair Main Memory Subsystem for CPU/GPU 

Sungkwang Lee, Sungjoo Yoo - Pohang Univ. of Science 


55.66 Watermark-Based Identification and Implementation 

Efficiency of IP Embedded Processor Cores 

Jedrzej J. Kufel, Peter R. Wilson, Bashir Al-Hashimi 

- Univ. of Southampton, United Kingdom 

Stephen Hill - ARM, Ltd., Cambridge, United Kingdom 

55.67 Hybrid 3-D IC Cooling System Using 

Micro-Fluidic Cooling and Thermal TSVs 

Ankur Srivastava, Bing Shi - Univ. of Maryland, College Park, MD

ADJUNCT EVENTS 

IEEE CEDA PRESENTS: DIGITAL ANALOG DESIGN 

Tuesday, June 5 - 11:45am - 1:30pm 

Organizer: 

Joel Phillips - Cadence Design Systems, Inc., Berkeley, CA 

Speaker: 

Mark Horowitz - Stanford Univ., Stanford, CA 

Room: 303 

The past 30 years have seen an enormous growth in the power and sophistication 

of digital design tools, while progress in analog tools has been much more modest. 

Digital tools use many abstractions to allow them to validate that implementations 

match the functional models and the composition of cells matches the composition 

of the functional models. 

While there are many reasons why this is more difficult for analog circuits, it can be 

done. To prove this point, this talk presents how to leverage the fact that the result 

surface of analog designs is smooth to create ways to formally validate analog 

models to instances, define analog fault models, and even efficiently explore the 

effect of process variations. 

15TH ANNUAL SIGDA PH.D. FORUM/MEMBER MEETING 

Tuesday, June 5 - 7:00pm - 8:30pm 

Room: 303 

SIGDA invites you to attend our 15th annual Ph.D. Forum and Member Meeting 

at DAC 2012. SIGDA members are invited, as are all members of the EDA 

Community. We will begin with an overview of SIGDA programs, including newly 

created programs, followed by the presentation of this year’s ACM/SIGDA Awards. 


However, the main focus of the meeting will be the Ph.D. Forum. Aimed at 

strengthening ties between academia and industry, students will present posters 

and discuss their Ph.D. dissertation research with interested attendees. The Ph.D. 

Forum gives students feedback on their research and gives the EDA community a 

preview of work in progress. Light refreshments will be served. 

25TH ACM SIGDA UNIVERSITY BOOTH AT THE 49TH 

DESIGN AUTOMATION CONFERENCE 

Tuesday, June 5 - Wednesday, June 6 

10:00am - 5:00pm 

Booth Coordinators: 

Naehyuck Chang 

Baris Taskin 

Joe Zambreno 

South Lobby 



This year marks the 25th University Booth at the Design Automation Conference. 

The booth is an opportunity for university researchers to display their results 

and to interact with participants at DAC. Presenters and attendees at DAC are 

especially encouraged to participate, but participation is open to all members of 

the university community. The demonstrations include new EDA tools, EDA tool 

applications, design projects, and instructional materials. 


COLOCATED CONFERENCES 


In addition to DAC’s comprehensive technical program, there are other conferences hosting their events 

at DAC. There is a separate registration fee to attend these meetings. If you are attending one of the 

conferences below, your registration does include entrance to the DAC Exhibit Hall Monday-Wednesday. 

Please note that a DAC Conference Registration does not include the colocated conferences. 

INTERNATIONAL WORKSHOP ON LOGIC 

AND SYNTHESIS (IWLS) 

Friday, June 1- Sunday, June 3: 

8:00am - 6:00pm 

Organizers: 

Ilya Wagner - Intel Corp., Hillsboro, OR 

Philip Brisk - Univ. of California, Riverside, CA 

The International Workshop on Logic and Synthesis is the premier forum for 

research in synthesis, optimization, and verification of integrated circuits. 

Research on logic synthesis for emerging technologies and for novel computing 

platforms, such as nanoscale systems and biological systems, is also strongly 

encouraged. The workshop accepts complete papers as well as abstracts, 

highlighting important new problems in the early stages of development, without 

providing complete solutions. The emphasis is on novelty and intellectual rigor. 

Univ. of California, Berkeley 

ESLsyn 2012 - THE 2012 ELECTRONIC SYSTEM 

LEVEL SYNTHESIS CONFERENCE 

Saturday, June 2 - Sunday, June 3: 

9:00am - 5:00pm 

Organizers: 

Philippe Coussy - Lab-STICC, Lorient Cedex, France 

Sandeep Shukla - Virginia Polytechnic Institute and 

State University, Blacksburg, VA 

Jens Brandt - Technische Univ. Kaiserslautern, Germany 

Achim Rettberg - Univ. of Oldenburg, Germany 

Adam Morawiec - ECSI, Gieres, France 

The ever-increasing need for enhanced productivity in designing highly complex 

electronic systems drives the evolution of design methods beyond the traditional 

approaches. Virtual prototyping, design space exploration and system synthesis 

with the goal of optimized and functionally correct product implementations are 

needed for designing both HW and SW parts. ESL design does not only provide 

system architects with the right tools to make the right decisions about the system 


Topics of interest include (but are not limited to): synthesis and optimization; 

power and timing analysis; testing, validation and verification; architectures and 

compilation; and design experiences. Submissions on modeling, analysis and 

synthesis for emerging technologies and platforms are also encouraged. Both 

complete papers as well as extended abstracts highlighting new problems and 

new topics of research are welcomed. Only original and previously unpublished 

material is permitted. 

Accepted papers are distributed only to IWLS participants. The workshop format 

includes paper presentations, posters, invited talks, social lunch and dinner 

gatherings, and recreational activities. 

architecture, it includes the methodologies and techniques that correlate the ESL 

model. A well-connected ESL-to-implementation design flow is needed. 

The system design teams expect newer and more efficient methods and tools 

supporting better management of the design complexity and reduction of the 

design cycle time all together, breaking the trend to compromise on the evaluation 

of various design implementation options. Designing at higher levels of abstraction 

is a viable way to better cope with the system design complexity, to verify earlier in 

the design process and to increase code reuse. 

The Electronic System Level Synthesis Conference ESLsyn focuses on automated 

system design methods that enable efficient modelling of systems to provide 

the capability to synthesize HW platforms and embedded software with particular 

aspects related to synthesis. 

SYSTEM-LEVEL INTERCONNECT PREDICTION (SLIP) 

Sunday, June 3: 8:00am - 5:00pm 

Organizers: 

Deming Chen - Univ. of Illinois at Urbana-Champaign, Urbana, IL 

Mustafa Ozdal - Intel Corp., Portland, OR 

Rasit Topaloglu - IBM Corp., New York, NY 

Room: 303 

Room: 300 

The 14th International Workshop of System Level Interconnect Prediction (SLIP) 

will be colocated with the 49th IEEE/ACM Design Automation Conference on June 

3, 2012 at the Moscone Center, San Francisco, California. 

The general technical scope of the workshop is the design, analysis and prediction 

of interconnect and communication fabrics in electronic systems. The workshop 

themes would include keynote speech, regular paper sessions with paper 



discussion panels, interactive poster sessions, panels on hot research topics, and 

embedded tutorials and invited talks. 

Representative technical topics include, but are not limited to: interconnect 

prediction and optimization at various IC design stages, interconnect design 

challenges and system-level NoC design, design and analysis of power and clock 

networks, interconnect architecture of structural designs and FPGAs, interconnect 

fabrics of many-core architectures, design-for-manufacturing (DFM) techniques for 

interconnects, high speed chip-to-chip interconnect design, design and analysis of 

chip-package interfaces, interconnect topologies of multiprocessor systems, 3-D 

interconnect design and prediction, emerging interconnect technologies, sensor 

networks, and synergies between chip communication networks and networks 

arising in other contexts such as social networks, system biology, etc. 

IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE- 

ORIENTED SECURITY AND TRUST (HOST 2012) 

Sunday, June 3 - Monday, June 4: 

8:30am - 6:00pm 

Room: 304 


For example, secure electronic designs may be affected by malicious circuits, 

Organizers: 

Trojans that alter system operation. Furthermore, dedicated secure hardware 

Ken Mai - Carnegie Mellon Univ., Pittsburgh, PA 

implementations are susceptible to novel forms of attack that exploit side-channel 

Ramesh Karri - Polytechnic Institute of New York Univ., New York, NY 

leakage and faults. Third, the globalized, horizontal semiconductor business model 

A wide range of applications, from secure RFID tagging to high-end trusted 

raises concerns of trust and intellectual-property protection. 

computing, relies on dedicated and trusted hardware platforms. The security HOST 2012 is a forum for novel solutions to address these challenges. Innova- 

and trustworthiness of such hardware designs are critical to their successful tive test mechanisms may reveal Trojans in a design before they are able to 

deployment and operation. 

do harm. Implementation attacks may be thwarted using side-channel resistant 

Recent advances in tampering and reverse engineering show that important design or fault-tolerant designs. New security- aware design tools can assist a 

challenges lie ahead. 

designer in implementing critical and trusted functionality, quickly and efficiently. 

46 

www.DAC.com







IEEE DESIGN FOR MANUFACTURING AND 

YIELD (DFM&Y) WORKSHOP 

Monday, June 4 - 8:30am - 7:00pm 

Organizers: 

Nagaraj NS - Texas Instruments, Inc., Dallas, TX 

Amith Singhee - IBM T.J. Watson Research Ctr., Yorktown Heights, NY 

Will Conley - Dynamic Intelligence, Austin, TX 

Increased manufacturing susceptibility in today’s nanometer technologies 

requires up to date solutions for yield optimization. In fact, designing an 

SoC for manufacturability and yield aims at improving the manufacturing 

process and consequently its yield by enhancing communications across the 

“design”manufacturing interface. 

A wide range of Design-for-Manufacturability (DFM), Design-for-Yield (DFY) and 

Design-for-Test (DFT) methodologies and tools are proposed today. Some of 

SI2 ROUND-UP @ DAC: STANDARDS IN ACTION 

Monday, June 4 - 9:00am - 6:00pm 

Organizers: 

Sumit DasGupta - Si2, Austin, TX 

Nick English - Si2, Austin, TX 

Jake Buurma - Si2, Austin, TX 

Speaker(s): 

Jim Culp - IBM Corp., Hopewell Junction, NY 

Vito Dai - GLOBALFOUNDRIES, Sunnyvale, CA 

S.W. Paek - Samsung, Yongin-City, Republic of Korea 

Concetta Riccobene - LSI Corp., San Jose, CA 

Cathy Rogers - Synopsys, Inc., Mountain View, CA 

Riko Radojcic - Qualcomm, Inc., San Diego, CA 

Arif Rahman - Altera Corp., San Jose, CA 

Aveek Sarkar - Apache Design, Inc. a subsidiary of ANSYS, Inc., San Jose, CA 

Keith Felton - Cadence Design Systems, Inc., San Jose, CA 

Dusan Petranovic - Mentor Graphics Corp., San Jose, CA 

Gilles Namur - STMicroelectronics, Crolles, France 

James Masters - Intel Corp., Folsom, CA 

Gilles Lamant - Cadence Design Systems, Inc., San Jose, CA 

SI2 OPEN LUNCHEON, A CELEBRATION OF THE 

10TH ANNIVERSARY OF OPENACCESS 

Monday, June 4 -12:15 - 1:30pm 

This complimentary lunch will celebrate the 10th Anniversary of the first release of OpenAccess and will also serve as the annual open Si2 meeting that will include a 

short presentation on the “state-of-the-union” at Si2 and announcement of the results of the annual election of Si2’s board of directors. 

SI2 OPEN NETWORKING RECEPTION 

Monday, June 4 - 4:30 - 6:00pm 

Room: 300 

Room: 301 

Room: 303 

Room: 301 

This complimentary reception will continue the celebration for the 10th Anniversary of OpenAccess. Free hors d’oeuvres and refreshments will be provided. 



these are leveraged during the back-end design stages, and others have post 

design utilization, from lithography up to 3-D integration, wafer sort, packaging, 

final test and failure analysis. These solutions can dramatically impact the 

business performance of chip manufacturers. They can also significantly affect 

age-old chip design flows. 

Using a DFM/DFY/DFT solution is an investment and thus choosing the most cost 

effective one(s) requires trade-off analysis. The workshop will analyze key trends 

and challenges in DFM, DFY and DFT methodologies, and provide an opportunity 

to discuss a range of DFM, DFT and DFY solutions for SoC designs now and in 

the future, including practical case studies that demonstrate the successes and 

failures of such solutions. 


Standards have been proven to reduce cost of operations, drive greater process 

efficiencies and offer greater opportunities for start-up companies to infuse fresh 

technology in the design and manufacturing of IC’s. Si2 standards have been 

targeted to resolve “pinch-points” in the overall semiconductor food-chain with a 

steadfast focus on rapid adoption of these standards. 

This day-long program, consisting of 4 individual events, will showcase activities 

currently underway with an eye towards demonstrating the value of these programs 

to the program participants and to the overall semiconductor industry. Therefore, 

this day-long session should entice engineers and technologists working at both 

current and cutting-edge technology nodes and also managers responsible for 

driving both design and manufacturing strategy, and related financial and staffing 

decisions. A featured part of the program will celebrate the 10th Anniversary of 

OpenAccess. A complimentary luncheon and an afternoon reception will highlight 

this occasion. 



47







ACM STUDENT RESEARCH COMPETITION AT 

DESIGN AUTOMATION CONFERENCE 

Tuesday, June 5 - Wednesday, June 6: 

2:00 - 4:00pm 

Organizers: 

Naehyuck Chang - Seoul National Univ., Seoul, Republic of Korea 

Srinivas Katkoori - Univ. of South Florida, Tampa, FL 

Sponsored by Microsoft Research, the ACM Student Research Competition is an 

internationally recognized venue enabling undergraduate and graduate students 

who are ACM members to: 

• Experience the research world -- 

for many undergraduates this is a first! 

• Share research results and exchange ideas with other 

students, judges, and conference attendees 

• Rub shoulders with academic and industry luminaries 

• Understand the practical applications of their research 

• Perfect their communication skills 

• Receive prizes and gain recognition from ACM 

and the greater computing community. 

CELUG/EDAC ENTERPRISE 

LICENSING CONFERENCE 

48 

Room: 206 

Wednesday, June 6 - Thursday, June 7: Room: 236-238 

9:00am - 6:00pm 

Organizers: 

Lee Levenson - CELUG, Tarzana, CA 

EDA Licensing providers, ISVs, and users will come together at an event 

colocated with the Design Automation Conference in San Francisco, June 5, 6 & 

7, 2012. CELUG (Centralized Enterprise Licensing Users Group) and EDAC (EDA 

Consortium) are co-hosting this three-day event at DAC 2012. This interactive event 

will focus on Enterprise Licensing, with presentations and panels addressing current 

and future challenges to making high technology tools and users more productive. 


special interest group on 

design automation 


The ACM Special Interest Group on Design Automation is organizing such an 

event in conjunction with the Design Automation Conference. 

Authors of accepted submissions will get travel grants from ACM/Microsoft to 

attend the event at DAC. The event consists of several rounds, as described here 

and also here, where you can also find more details on student eligibility and timeline. 

Research projects from all areas of design automation are encouraged. The 

author submitting the abstract must still be a student at the time the abstract is 

due. Each submission should be made on the EasyChair submission link available 

here where details on submission format can also be found here. 


This colocated event will bring together Licensing Solution Providers, Independent 

Software Vendors face to face for interactive sessions with Enterprise Customers 

from key industries, including: 

• Academia 

• Aerospace 

• Automotive 

• Oil and Gas 

• Semiconductor 

• Life Sciences 

• Chemical Analysis 

• Electronic Test 

• Electronic Measurement 

The day-long program will be divided into 4 sessions, a luncheon, and a reception. 

Attendees can register for individual sessions or for the entire program. The 

sessions are considered colocated events; please click here to register.

PAVILION PANELS 

MONDAY, JUNE 4 BOOTH #310 


Sponsored by: 

GARY SMITH ON EDA: TRENDS AND WHAT’S HOT AT DAC 

9:15 - 10:15am 

Moderator: 

Robert Gardner - EDA Consortium, San Jose, CA 

Panelist: 

Gary Smith - Gary Smith EDA, Santa Clara, CA 

LOW POWER TO THE PEOPLE! 

10:30 - 11:15am 

Moderator: 

John Donovan - Low-Power Design, Austin, TX 

Panelists: 

Aveek Sarkar - Apache Design, Inc. a subsidiary of ANSYS, Inc., San Jose, CA 

Clive Bittlestone - Texas Instruments, Inc., Dallas, TX 

Robert Patti - Tezzaron Semiconductor, Naperville, IL 

IS “LIFECARE” THE NEXT KILLER APP? 

11:30am - 12:15pm 

Moderator: 

Rick Merritt - EE Times, San Jose, CA 

Panelists: 

James Bates - Maxim Integrated Products, Inc., Sunnyvale, CA 

Fabrice Hoerner - Qualcomm, Inc., San Diego, CA 

Greg Fawcett - Palo Alto Research Center, Inc., Palo Alto, CA 

THE MECHANICS OF CREATIVITY 

3:15 - 4:15pm 

Moderator: 

Karen Bartleson - Synopsys, Inc., Colorado Springs, CO 

Panelists: 

Dee McCrorey - Risktaking for Success LLC, Santa Clara, CA 

Sherry Hess - AWR Corp., El Segundo, CA 

Lillian Kvitko - Oracle, Santa Clara, CA 

INTERVIEW WITH DR. BELLE W. Y. WEI, 

2012 MARIE R. PISTILLI AWARD RECIPIENT 

4:30 - 5:15pm 

Moderator: 

Daya Nadamuni - Gary Smith EDA, San Jose, CA 

Panelist: 

Dr. Belle W. Y. Wei - San Jose State Univ., San Jose, CA 

Women have made important contributions and strides in the EDA industry. The 

DAC Executive Committee presents an annual award to honor an individual who has 

made significant contributions in helping women advance in EDA technology. Please 

join us for a conversation with this year’s 2012 Marie R. Pistilli Award recipient, Dr. 

Belle W. Y. Wei, Don Beall Dean of Engineering, San Jose State University. Since 

her 2002 appointment as Don Beall Dean of SJSU’s Charles W. Davidson College of 

Engineering, Dr. Belle W. Y. Wei has led a College dedicated to educating engineers 

who can take on today’s problems and produce tomorrow’s solutions. 


Longtime EDA analyst Gary Smith of Gary Smith EDA will give us his take on 

the EDA’s hottest technology trends. How will the dramatic changes in EDA, the 

semiconductor market and the design community affect you? What are the hot 

‘must sees’ at this year’s conference? Find out here! 


Power management has become the single biggest design challenge. Methods 

used to manage power will depend on the interaction among process technologies, 

IP, hardware design, and embedded software for the targeted application. New 

technologies such as 3-D present further power management opportunities and 

challenges. Come hear these experts discuss power management struggles and solutions. 

Business 

The world population hit 7 billion last fall, with a billion more expected in a dozen 

years. “Lifecare” represents an incredible opportunity for the semiconductor 

industry to promote health, energy conservation, safety and productivity. From 

smart city infrastructure to medical care advances, from sensors and controls to 

nanotechnology, what new EDA ecosystems will emerge to better model the real world? 


What does it take to be an idea machine? Design is an inherently creative process, 

but how can we be creative on demand? How can we rise above mundane tasks 

with flashes of brilliance? Discover secrets of technical and business creativity 

and calculated risk taking, and share stories of innovation. Sponsored by Women 

in Electronic Design. 


Dr. Wei began her career at SJSU in 1987 as an assistant professor in the 

Department of Electrical Engineering after completing an engineering M.S. from 

Harvard and an electrical engineering Ph.D. from U.C. Berkeley with specialties in 

VLSI circuit theory, special architectures, and sensor networks. Following a 1993- 

94 Stanford visiting associate professorship, Dr. Wei returned to SJSU where 

she was later elected Electrical Engineering Department Chair from 1998-2002. 

Thereafter, she accepted her current position as Dean (reappointed for a second 

six-year term in 2009). Dr. Wei is the first person in her College’s history to hold 

an endowed deanship. 

49


TUESDAY, JUNE 5 BOOTH #310 

HOGAN’S HEROES: LEARNING FROM APPLE 

10:00 - 11:00am 

Moderator: 

Jim Hogan - Tela Innovation, Inc., Campbell, CA 

Panelists: 

Jack Guedj - Tensilica, Inc., Santa Clara, CA 

Tom Collopy - Aggios, Inc., Irvine, CA 

Jan Rabaey - Univ. of California, Berkeley, CA 

50 


Sponsored by: 

CHEVY VOLT TEARDOWN: AUTOMOTIVE ELECTRONICS 

1:30 - 2:30pm 

Moderator: 

Brian Fuller - EE Times, San Francisco, CA 

Panelists: 

Al Steier - Munro & Associates, Inc., Troy, MI 

John Scott-Thomas - TechInsights, Ottawa, ON, Canada 

HERITAGE SERIES: INTERVIEW WITH JIM SOLOMON, 

1997 PHIL KAUFMAN AWARD RECIPIENT 

3:00 - 3:45pm 

Moderator: 

Steve Ohr - Gartner, Inc., San Jose, CA 

Panelist: 

Jim Solomon - Xulu Entertainment, Milpitas, CA 

CONQUERING NEW FRONTIERS IN ANALOG DESIGN 

- PLUNGING BELOW 28NM 

4:00 - 4:45pm 

Moderator: 

Mar Hershenson - Revel Touch, Inc., Los Altos, CA 

Panelists: 

Jose Alvarez - Freescale Semiconductor, Inc., Austin, TX 

KT Moore - Synopsys, Inc., Mountain View, CA 

Mahesh R. Tirupattur - Analog Bits, Inc., Mountain View, CA 

Business 

Apple. We admire their devices, worship their creators and praise their stock in 

our portfolios. Apple is synonymous with creative thinking, new opportunities, 

perseverance and wild success. Along the road, Apple set new technical and 

business standards. But how much has the electronics industry, in particular EDA, 

“where electronics begins,” learned from Apple? It depends. 

FOUNDRY, EDA AND IP: SOLVE TIME-TO-MARKET ALREADY! 

11:30am - 12:15pm 

Moderator: 

Ron Wilson - Altera Corp., San Jose, CA 

Panelists: 

Dr. Naveed Sherwani - Open-Silicon, Inc., Milpitas, CA 

Ritesh Saraf - MoSys, Inc., Santa Clara, CA 

John Koeter - Synopsys, Inc., Mountain View, CA 


Designing billion+ transistor SoCs for 20nm and below in 22 months is not fast 

enough! Challenges include qualifying and integrating IP blocks, custom logic, 

and achieving design closure. This panel will discuss what foundry, IP and EDA 

vendors are doing to step up and finally deliver plug-and-play solutions. 


The Chevy Volt, the most talked-about automotive innovation in recent years, has 

been peeled apart down to the board level. Watch and listen as experts analyze the 

Volt’s amazing design--assembly, boards, components, sensors and chips, not to 

mention its 360V lithium-ion battery--and offer a glimpse at the automobile’s future. 


The analog design tool segment has long lived in the shadow of its dazzling digital 

tool counterpart. But without analog, countless consumer electronics devices 

would not exist. No one has been more closely associated with the advances in 

analog tool creation than Jim Solomon, Phil Kaufman Award Recipient. Hear Jim 

illuminate the mystic world of analog. 


Analog design flows have not changed much in the past two decades, yet analog 

IP has been at the forefront of every new technology node breakthrough. This 

panel will discuss some of the major electrical, physical and process design 

challenges at 28nm and below, and what adjustments can be made in the design 

ecosystem to facilitate first-pass silicon success.


WEDNESDAY, JUNE 6 BOOTH #310 

TOWN HALL: DARK SIDE OF MOORE’S LAW 

9:15 - 10:15am 

Moderator: 

Lucio Lanza 

Panelists: 

John Chilton - Synopsys, Inc., Mountain View, CA 

Behrooz Abdi - Consultant, San Diego, CA 

Steve Glaser - Xilinx, Inc., San Jose, CA 

REAL WORLD HETEROGENEOUS MULTICORE 

2:30 - 3:15pm 

Moderator: 

Tom Halfhill - The Linley Group, Mountain View, CA 

Panelists: 

Ted Vucurevich - Enconcert, Inc., Los Gatos, CA 

Paul Tobin - Advanced Micro Devices, Inc., Boston, MA 

David Kramer - Freescale Semiconductor, Inc., Austin, TX 

TEENS TALK TECH 

3:30 - 4:15pm 

Moderator: 

Kathryn Kranen - Jasper Design Automation, Inc., Mountain View, CA 

Panelists: 

Josh Godfrey - Menlo High School, Atherton, CA 

Summer Schoof - Menlo High School, Atherton, CA 

Shuhei Nakata - Menlo High School, Atherton, CA 

Tara Basu-Trivedi - Menlo High School, Atherton, CA 


Sponsored by: 

HARDWARE-ASSISTED PROTOTYPING AND VERIFICATION: 

MAKE VS. BUY? 

4:30 - 5:15pm 

Moderator: 

Gabe Moretti - Gabe on EDA, Venice, FL 

Panelists: 

Albert Camilleri - Qualcomm, Inc., San Diego, CA 

Austin Lesea - Xilinx, Inc., San Jose, CA 

Mike Dini - The Dini Group, Inc., La Jolla, CA 

Business 

Semiconductor companies double transistor counts every 22 months, yet device 

prices stay relatively the same. This has been a windfall for customers but not for 

chip makers, who have exponentially increasing design costs every new cycle. 

Venture capitalist Lucio Lanza and panelists will discuss what it will take to bring 

design costs and profitability back into harmony with Moore’s Law. 

DIVIDE AND CONQUER - INTELLIGENT PARTITIONING 

1:30 - 2:15pm 

Moderator: 

Paul McLellan - SemiWiki, San Francisco, CA 

Panelists: 

Santosh Santosh - NVIDIA Corp., Santa Clara, CA 

Jonathan DeMent - IBM Systems and Technology Group, Austin, TX 

Hao Nham - eSilicon Corp., Sunnyvale, CA 


If you were assigned a 100+ million-instance 28-nm chip, what would you do? Hire 

more engineers, push out the delivery date, quit? Not if you could help it. Partition 

it! But how many blocks? This panel will discuss what’s needed from synthesis, 

verification and physical design tools to make partitioning work for today’s designs, 

budgets, resources and delivery schedules. 


What does heterogeneous multicore mean to you? Come hear experts discuss the 

challenges when implementing heterogeneous multicores describing real world 

experiences using both different core sizes and types as well as techniques and 

tools to develop systems that take advantage of these multicore architectures. 


High school students tell us how they use the latest tech gadgets, and what they 

expect to be using in three to five years. They give insights into the next killer 

applications and what they would like to see in the next generation of hot new 

electronics products that we should be designing now. 


As ASIC and ASSP designs reach billions of gates, hardware-assisted verification 

and/or prototyping is becoming essential, but what is the best approach? Should 

you buy an off-the-shelf system or build your own? What criteria – time-to-market, 

cost, performance, resources, quality, ease of use – are most important? Panelists 

will share their real world design trade-offs. 

51

ADDITIONAL MEETINGS Access 

Monday, June 4: 9:00am - 6:00pm 

52 


to these meetings is 

controlled by the organizing entity 

HIGH PERFORMANCE DESIGN SUCCESS WITH SYNOPSYS 

GALAXY TM IMPLEMENTATION PLATFORM 


Synopsys invites you to join us for highly informative sessions covering the latest high performance design trends, challenges and solutions. Listen to leading industry 

experts present best practices and their success designing for high performance using Synopsys implementation products. Learn about innovations in high performance 

technology that help address your Gigascale, GigaHz and advanced geometry design challenges. If you are a design engineer or manager, you won’t want to miss 

these special events. *Please stop by Synopsys Booth 1130 for presentation access. 

DESIGN AND IP MANAGEMENT SYMPOSIUM 

Monday, June 4: 1:30 - 2:30pm 

Chair(s): 

Dean Drako - IC Manage 

Speaker(s): 

Vincent Ross - Advanced Micro Devices, Inc. 

Jacob Rael - Broadcom Corp. 

Gary Smith - Gary Smith EDA 

Shiv Sikand - IC Manage 

Doug Quist - NVIDIA Corp. 

COOLEY’S TROUBLEMAKER PANEL 


Chair(s): 

John Cooley - Deepchip 

Speaker(s): 

Doug Aitelli - Calypto Design Systems, Inc. 

Joe Sawicki - Mentor Graphics Corp. 

Lauro Rizzatti - EVE-USA, Inc. 

Ravi Subramanian - Berkeley Design Automation 

Yunshan Zhu - NextOp Software, Inc. 

Jim Hogan - Vista Ventures LLC 

Gary Smith - Gary Smith EDA 

Room: 220 

BOOST PRODUCTIVITY USING SYNOPSYS’ AMS 

VERIFICATION SOLUTION 

Monday, June 4: 11:30am - 1:30pm 

San Francisco Marriott Marquis 

At this event, you will hear what industry leaders have to say about using Synopsys’ AMS verification solution in some of today’s most challenging designs. Panelists 

will also discuss their future verification needs as well as the methodology and tool requirements to support modern AMS verification. 

Room: 200 

Room: 256 


PRIMETIME SPECIAL INTEREST GROUP (SIG) RECEPTION 

FEATURING NEXT GENERATION HIERARCHICAL 

TIMING TECHNOLOGY - HYPERSCALE 



Panelists will discuss development goals, the Design and IP Management 

methodologies and best practices they use to support those goals, and the 

results achieved. 

Topics to include productivity improvements, bug management, and multi-site data 

exchange and collaboration. Audience Q&A to follow panel discussion. 

San Francisco Marriott Marquis 


Come watch EDA vendors squirm as they answer no-holds-barred, edgy, user-submitted 

questions about their businesses and tools. It’s an old style open Q&A from 

the days before corporate marketing took over every aspect of EDA 

company images. 


Synopsys hosts an annual dinner event for the PrimeTime Special Interest Group at DAC, providing an opportunity for PrimeTime users to stay connected with the latest 

developments in timing analysis. This year, the event will feature Synopsys’ next generation hierarchical timing technology, HyperScale. Synopsys’ R&D team will unveil 

the new underlying engines and industry experts will share their experience on this innovative new technology resulting in up to 10X faster and smaller full-chip timing 

analysis runs, with the same signoff quality results compared to flat analysis. The event will be held at the San Francisco Marriott Marquis.

ADDITIONAL MEETINGS Access 

SAMSUNG-GLOBALFOUNDRIES - SYNOPSYS BREAKFAST 

Tuesday, June 5: 7:15 - 8:25am 

INDUSTRY LEADERS VERIFY WITH SYNOPSYS 

Tuesday, June 5: 11:30am - 1:00pm San Francisco Marriott Marquis 

Synopsys hosts an annual lunch event at DAC, providing an opportunity for 

verification engineers, manager, and executives to stay connected with the latest 

developments in the verification landscape and advanced technology. This year, 

the event will cover the latest verification trends, challenges and solutions. You 

BIRDS-OF-A-FEATHER MEETING: AT A CROSSROADS 

– DEVELOPING THE NEXT GENERATION 

ANALOG/MIXED-SIGNAL LANGUAGE STANDARD(S) 

Tuesday, June 5: 7:00 - 8:30pm 

Organizer(s): 

Martin Barnasconi - NXP Semiconductors, Eindhoven, The Netherlands 

Lynn Bannister - Accellera Systems Initiative, Napa, CA 

Today’s embedded and integrated systems interact more and more tightly with 

the analog physical environment, where digital HW/SW subsystems become 

functionally interwoven with analog/mixed-signal (AMS) blocks such as radio 

frequency (RF) interfaces, power electronics, or sensors and actuators. 

Examples are software defined radios, wireless sensor networks, and automotive 

applications, in which analog electronics are controlled, configured, or calibrated 

using digital techniques in hardware or software. 

Historically, the hardware description languages Verilog-AMS and VHDL-AMS 

have addressed the analog implementation aspects but have limited capabilities 

to address the system-level design and verification challenges. From the digital 

perspective, SystemC and SystemVerilog focus on system-level design and 

verification, respectively. The SystemC AMS extensions are positioned to 

address the mixed-signal architectural design challenges, whereas SystemVerilog 

extensions are under development to include abstract analog signal representation 

in functional verification. Obviously, we are at a crossroads, where Verilog- 

to these meetings is 

controlled by the organizing entity 


IPL ALLIANCE LUNCHEON - REAPING THE BENEFITS OF IPDKS 

NORTH AMERICAN SYSTEMC USERS GROUP MEETING - 

NASCUG 18 

Wednesday, June 6: 1:00 - 5:00pm 

The North American SystemC Users Group (NASCUG) accelerates the use 

of SystemC for both new and established users by providing open venues for 

users to contribute, learn, and interact. A central component of the half-day 

meeting is a number of user experience presentations discussing techniques of 

design, modeling and verification using SystemC. Topics include (but not limited 

San Francisco Marriott Marquis: 

Golden Gate Ballroom 

Room: 300 

Room: 250 & 262 


Industry experts from Samsung, GLOBALFOUNDRIES and Synopsys discuss our unique design enablement collaboration that delivers proven design, IP and manufacturing 

solutions for advanced high-k metal-gate (HKMG) process technologies. 

will hear leading industry experts share their viewpoints on what is driving SoC 

complexity and how their teams have achieved success. The event will be held 

at the San Francisco Marriott Marquis. 

Tuesday, June 5: 12:00 - 1:30pm San Francisco Marriott Marquis: Analog/Mixed-Signal/RF Design 

Golden Gate Ballroom 

Interoperable PDKs (iPDKs) benefit the entire custom design ecosystem. improved productivity. At the 6th Annual IPL Luncheon, presenters from multiple 

Semiconductor foundries and IDMs create iPDKs to reduce their PDK development, foundries will highlight the benefits of iPDK standard and their experiences in 

validation, support and distribution costs while enabling advanced design flows developing and deploying foundry iPDKs. The IPL Alliance will present an update 

and multiple EDA tool support. All leading foundries today are delivering iPDKs. 

Chip designers now enjoy access to best-in-class tools, interoperable flows, and 

on current and future IPL projects. 

Analog/Mixed Signal 

AMS and VHDL-AMS are being updated and at the same time SystemC and 

SystemVerilog are expanding to support abstract AMS modeling styles. Should 

all of these AMS extensions remain compatible? Which elements are not yet 

addressed in the mixed-signal modeling and simulation domain but are essential 

for a next generation mixed-signal language? Can we focus on only one “mother 

HDL”, or do we need more? 

We would like to discuss and answer these questions, to explore viable directions for 

the next step in AMS standards, at this Birds-of-a-Feather session. We invite AMS and 

RF system-level designers, circuit designers, verification engineers, and EDA vendors 

to discuss the requirements and needs for the next-generation AMS languages. 

Accellera Systems Initiative, the independent non-profit organization focused on 

the creation and adoption of electronic design automation (EDA) and intellectual 

property (IP) standards for design and verification, will moderate this session to 

emphasize the importance of standardization in this domain. The intent is to foster 

the creation of next generation mixed-signal languages standards to describe 

hardware as well as system-level behavior. 


to) architectural modeling; transaction-level modeling; virtual prototypes; analog 

modeling with SystemC AMS; integrating SystemC into the design flow; and 

platform design using SystemC. To find out more and register for this free event, 

visit www.nascug.org

TUESDAY KEYNOTE MIKE MULLER - DAC

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