37th Adv.Prg - DAC

H i g h l i g h t s
Technical Program - details
o n
 pgs.
 27-49
Two Exciting
Keynotes
details
 on
pgs. 2
2 & 2
3
TUESDAY
 KEYNOTE
Theo
 Classen
Chief
 Technical
 Officer,
 Philips
 Semiconductors
Eindhoven,
 The
 Netherlands
Tuesday,
 June
 6
 -
 9:00
 AM
Room:
 Concourse
 Hall
THURSDAY
 KEYNOTE
Hugo
 De
 Man
Professor,
 Katholieke
 Univ.
Leuven,
 Belgium
Thursday,
 June
 8
 -
 1:00
 PM
Room:
 Concourse
 Hall
Embedded Systems Day - Wednesday, June 7 -
 See
 sessions
 18-20,
 23-25,
 28-30
Recognizing
 the
 increasing
 role
 of
 embedded
 software
 in
 complex
 SoC
 designs,
 we
 have
designated
 Wednesday
 as
 Embedded
 Systems
 (ES)
 Day.
 Three
 parallel
 tracks
 will
 cover
 topics
such
 as
 embedded
 compilation,
 hardware/software
 co-design,
 system
 modeling
 and
 power
optimization.
 A
 special
 session
 will
 focus
 on
 ES
 research
 and
 educational
 programs
 within
universities.
 In
 addition,
 an
 ES
 CEO/CTO
 panel
 will
 examine
 challenges
 and
 potential
 solutions
as
 seen
 from
 the
 prespective
 of
 the
 CAD
 tool
 and
 system
 chip
 vendors.
Tutorials - Friday, June 9 - details
 on
 pgs.
 50-55
1)
 The
 Quest
 for
 Synthesis
 and
 Layout
 Timing
 Closure
2)
 Static
 Timing
 Analysis
 and
 Optimization
 for
 High-Performance
 Digital
 Design
 Success
3)
 System
 Level
 Design
 with
 Embedded
 Platforms
4)
 Signal
 Integrity
 in
 Deep
 Submicron
 Designs
5)
 Design
 Technology
 for
 Building
 Wireless
 Systems-on-Chip
6)
 Low-Power
 System
 Design:
 Applications,
 Architectures,
 and
 Design
 Methodologies
W o r k s h op for Women in Des i g n A u t o m a t i o n- Sunday,June 4 - details
o n
 pg.
 18
Strategies
 for
 Success -
 This
 unique
 program
 affords
 the
 opportunity
 to
 hear
 successful
women
 speak
 on
 topics
 relevant
 to
 their
 careers.
Workshop for VLSI Design Educators - Sunday, June 4 -
 details
 on
 pg.
 19
This
p rogram
a ffords
 a
f orum
f or
e ducators
t o
i mprove
t he
i nstruction
o f
V LSI
D esign
 courses.
Interoperability Workshop - Sunday, June 4 -
 details
 on
 pg.
 20
This
 workshop
 invites
 leading
 Semiconductor,
 System
 and
 EDA
 companies
 to
 discuss
 the
 need
for
 a
 new
 design
 system
 architecture
 and
 supporting
 standard
 data
 model
 API.
Ph.D Forum - Tuesday, June 6 -
 details
 on
 pg.
 21
A chance
 for
 Ph.D
 students
 and
 industry
 representatives
 to
 get
 together.
 Students
 get
 feedback
on
t heir
r esearch
p roposals;
i ndustry
g ets
a 
c hance
t o
p review
s tudents
a nd
t heir
w ork.
Sponsors :
IEEE
Networking
the World
Program Highlights
The
 technical
 program
 covers
 over
 160
 papers,
 panels
 and
 embedded
 tutorials
 in
 five
 parallel
tracks
 covering
 system
 level
 design,
 synthesis,
 physical
 design,
 verification,
 modeling,
interconnect,
 power
 and
 IP
 issues.
 Highlights
 include
 a
 focus
 on
 embedded
 systems
 (see
below)
 and
 also
 a
 number
 of
 sessions
 on
 fault
 and
 parasitic
 modeling
 in
 deep
 submicron
technologies.
 The
 program
 includes
 a
 number
 of
 special
 sessions
 with
 invited
 tutorial
presentations
 on
 the
 limitations
 of
 MOSFET
 modeling,
 closing
 the
 ASIC/full
 custom
 design
 gap
and
 an
 exciting
 preview
 of
 life
 at
 35nm
 and
 beyond.
exhibitor
info
e
x
h
i
b
i
t
o
r
p
r
e
s
e
n
t
a
t
i
o
n
s
conference
at
 a
 glance
t
e
c
h
n
i
c
a
l
p
r
o
g
r
a
m
t
u
t
o
r
i
a
l
s
sponsors
t
r
a
n
s
p
o
r
t
a
t
i
o
n
h
o
u
s
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registration
1

2
H i g h l i g h t s
Silicon Village - The
 area
 features
 silicon
 vendors
 offering
 ASIC,
 programmable
 logic,
 foundry
and
I P
 solutions.
Exhibit Highlights
Silicon Exhibitors
3
 DSP
 CORP.
ALBA
 CENTRE
 (THE)
ALCATEL
 MICROELECTRONICS
 USA
AMERICAN
 MICROSYSTEMS,
 INC.
ARM,
 INC.
AUSTRIA
 MIKRO
 SYSTEME
 INTERNATIONAL
 AG
BILLIONS
 OF
 OPERATIONS
 PER
 SECOND
 (BOPS)
CHIP
 EXPRESS
 CORP.
CMP
FRONTEC
 MICORELECTRONICS
 AB
GLOBAL
 UNICHIP
 CORP.
IBM
 MICROELECTRONICS
 CORP.
IMEC/EUROPRACTICE
MIPS
 TECHNOLOGIES,
 INC.
MOSIS
NORDIC
 VLSI
 ASA
PIVOTAL
TECHNOLOGIES
QUICKLOGIC
 CORP.
SILICONX
SLICEX,
 INC.
TRISCEND
 CORP.
TSMC
 NORTH
 AMERICA
UNITED
 MICROELECTRONICS
 CORP.
 GROUP
VAUTOMATION,
 INC.
VSI
 ALLIANCE
WESTERN
 DESIGN
 CENTER
The
 latest
 innovations
 at
 your
 fingertips
 with
 exhibitors
 highlighting
 their
 latest
 products.
Exhibitor
 Listing ................................................Pages
6-7
Exhibitor
 Presentation
 Schedule ................................Page
8
Exhibitor
 Presentation
 Abstracts ..........................Pages
9-17
No
 badge
 needed
 to
 attend
 Exhibitor
 Presentations.
Exhibit-Only and Exhibitor Presentations - Monday,
 June
 5
•
 A
 full
 day
 of
 20-minute
 Exhibitor
 Presentations
 -
 choose
 from
 126
 presentations;
 see
 pages
9-17
 for
 details.
•
 Free
 Monday
 Exhibit-Only
 Passes
 -
 call
 toll-free
 1-800-321-4573,
 or
 on
 line
 at
www.dac.com/freemon.html.
•
 $40
 full
 exhibit-only
 registration
 will
 allow
 you
 to
 attend
 exhibits
 Monday
 through
Wednesday.
Demo Suite Hours:
Monday
 -
 Wednesday,
 June
 5-7,
 2000 ............8:00
 AM
 -
 9:00
 PM
Thursday,
 June
 8,
 2000 ..............................8:00
AM
-
5:00
PM
•
 Demo
 Suites
 will
 be
 in
 the
 West
 Hall
 of
 the
 Los
 Angeles
 Convention
 Center.
•
 Exhibiting
 companies
 will
 have
 the
 opportunity
 to
 give
 their
 customers
 private
 demos
without
 leaving
 the
 Convention
 Center.
•
 Demo
 Suites
 are
 available
 by
 invitation
 only.
Information -
 Call
 toll
 free:
 1-800-321-4573,
 or
 visit
 our
 web
 page
 (www.dac.com)
 for
updated
 conference
 information
 and
 other
 information
 of
 interest
 to
 the
 DA
 community.

s I n
Important
f o
Information
r m
At-A-Glance
a t i o n
Exhibit Hours: Demo Suite Hours:
(badge
 required) (by
 invitation
 only)
Monday,
 June
 5 10:00
 AM
 to
 6:00
 PM 8:00
 AM
 to
 9:00
 PM
Tuesday,
 June
 6 10:00
 AM
 to
 6:00
 PM 8:00
 AM
 to
 9:00
 PM
Wednesday,
 June
 7 10:00
 AM
 to
 6:00
 PM 8:00
 AM
 to
 9:00
 PM
Thursday,
 June
 8 – 8:00
 AM
 to
 5:00
 PM
Children
 under
 14
 years
 of
 age
 will
 not
 be
 admitted
 into
 the
 exhibit
 hall
 or
 demo
 suite
 area.
At-Conference Registration Hours
The
 registration
 desk
 will
 be
 located
 in
 the
 lower
 level,
 South
 Lobby
 of
 the
 Los
 Angeles
Convention
 Center
 and
 will
 be
 open
 at
 the
 following
 times:
Sunday,
 June
 4 8:00
 AM
 to
 10:00
 AM Tuesday,
 June
 6 7:30
 AM
 to
 5:00
 PM
Sunday,
 June
 4 3:00
 PM
 to
 5:00
 PM Wednesday,
 June
 7 7:30
 AM
 to
 5:00
 PM
Monday,
 June
 5 8:00
 AM
 to
 6:00
 PM Thursday,
 June
 8 7:30
 AM
 to
 3:00
 PM
To
 avoid
 long
 lines
 advance
 register
 by
 May
 8,
 2000.
On-Site Information Desk
The
 information
 desk
 will
 be
 located
 in
 the
 South
 lobby
 on
 the
 first
 floor.
 (213)
 765-4300.
Free Monday Exhibit-Only Passes
Register
 by
 May
 18,
 2000,
 and
 receive
 your
 badge
 via
 the
 US
 mail
 for
 immediate
 access
 to
 the
exhibit
 hall
 at
 10:00
 AM,
 June
 5.
 Call
 1-800-321-4573
 or
 1-303-530-4333,
 or
 visit
 the
 DAC
 web
at
 www.dac.com/freemon.html.
Conference Survey
Again
 this
 year
 we
 would
 like
 you
 to
 voice
 your
 opinion
 on
 various
 aspects
 of
 the
 conference.
DAC is
 conducting
 surveys
 to
 determine
 how
 to
 best
 serve
 your
 needs.
 Please
 take
 a
 few
moments
 to
 participate
 if
 you
 are
 approached
 by
 one
 of
 our
 surveyors.
 Look
 for
 interviewers
wearing
 “???”
 buttons
 at
 various
 locations
 around
 the
 show.
 Help
 make
 a
 difference
 in
 DAC
 and
receive
 a
 surprise
 gift
 for
 participating.
Best Paper Awards
Best
 Paper
 Awards
 of
 $500
 each
 will
 be
 announced
 at
 the
 Tuesday
 morning
 General
 Session.
Papers
 eligible
 for
 awards
 in
 this
 category
 are
 nominated
 by
 the
 Program
 Committee
 and
selected
 by
 a
 referee
 process.
 Awards
 will
 be
 given
 in
 each
 of
 the
 following
 categories:
1.
 Design
 Synthesis,
 Test
 and
 Validation
2.
 Analog/RF/Electrical
 Modeling
 and
 Simulation
3.
 Design
 Methodology
 (2)
4.
 Embedded
 Systems
3

4
I n
Conference
f o r
Information
m a t i o n
About the Conference
The
 37th
 Design
 Automation
 Conference
 provides
 a
 high-quality
 program
 facilitating
 technology
interchange
 among
 design
 automation
 researchers
 and
 developers,
 the
 engineers
 who
 use
 DA
systems
 to
 design,
 test
 and
 manufacture
 circuits
 and
 systems,
 and
 the
 vendors
 who
 provide
 both
electronic
 design
 automation
 (EDA)
 systems
 and
 silicon.
 Five
 full
 days
 of
 activities
 are
 planned.
New
 product
 introductions
 and
 application
 notes
 will
 be
 highlighted
 on
 Monday
 in
 the
 Exhibitor
Presentations,
 and
 more
 than
 250
 companies
 will
 exhibit
 the
 latest
 commercially
 available
products
 Monday
 through
 Wednesday.
 The
 central
 day,
 Wednesday,
 will
 be
 mainly
 devoted
 to
presentations
 on
 embedded
 system
 (ES)
 design,
 including
 a
 panel
 discussion
 among
 top
executives
 about
 how
th e
gr owing
 importance
 of
ES 
 will
 affect
 the
 EDA
 landscape.
Technical
 innovations
 from
 DA
r esearch
 and
 development
 and
 the
u se
 of
 DA
 in
 design
 of
 chips
 and
systems
 will
 be
 presented
 in
 five
 parallel
 sessions,
 Tuesday
 through
 Thursday,
 in
 the
 Technical
Program.
 The
 Technical
 Program
 features
 two
 keynote
 addresses,
 one
 on
 Tuesday
 morning
 by
 Dr.
Theo
 Claasen,
 Chief
 Technical
 Officer
 at
 Philips
 Semiconductor,
 and
 one
 on
 Thursday
 afternoon
by
 Prof.
 Hugo
D e
M an,
pr ofessor
a t
K atholieke
U niversiteit
Le uven
(B elgium)
a nd
r ecipient
 of
t he
1999
 Phil
 Kaufman
 Award.
Si x
 full-day
 tutorials
 will
be 
 offered
on 
 Friday.
The
 Technical
 Program
 consists
 of
 panel
 discussions,
 special
 sessions,
 and
 technical
 paper
sessions,
 some
 of
 which
 include
 embedded
 tutorials.
 The
 Design
 Tools
 track
 focuses
 on
 new
techniques
 for
 enhancing
 the
 performance
 and
 capabilities
 of
 EDA
 tools.
 The
 Design
 Methods
track
fo cuses
on 
th e
 results
a nd
in sights
g ained
b y
a pplying
ED A
t ools
to 
ac tual
s ystem
 designs.
This
 year
 DAC
 features
 an
ex panded
 set
 of
 sessions
 addressing
 design
 of
 embedded
 systems.
In
 addition
 to
t he
 ES
e xecutive
p anel,
n ine
o ther
p anel
d iscussions
c overing
t opics
t hat
r ange
f rom
dealing
 with
 timing
 closure
 to
 the
 future
 of
 design
 languages
 are
 also
 part
 of
 the
 Technical
 Program.
New to the Conference
2000
 is
 a
 year
 of
 records
 being
 set
 for
 DAC.
 At
 the
 conference
 this
 year
 you
 will
 have
 the
opportunity
 to
 choose
 from
 a
 record
 160
 papers,
 panels,
 tutorials
 and
 special
 sessions.
 When
in
 the
 DAC
 exhibition
 you
 will
 have
 the
 opportunity
 to
 visit
 with
 a
 record
 250
 EDA
 and
 silicon
vendors
 featured
 on
 the
 exhibit
 floor
 and
 in
 the
 demo
 suites.
New
 to
 the
 technical
 program
 is
 a
 special
 mini-track
 on
 embedded
 systems
 software.
 Software
for
 embedded
 systems
 will
 play
 an
 increasing
 role
 in
 the
 design
 of
 systems-on-a-chip
 (SOC).
Three
 parallel
 tracks
 of
 sessions
 will
 cover
 hardware
 and
 software
 aspects
 of
 embedded
systems,
 as
 well
 as
 their
 co-design,
 on
 Wednesday.
The
 Silicon
 Village:
 Where
 Designs
 Get
 Real
 is
 making
 its
 third
 appearance
 at
 DAC.
 DAC
 offers
 the
Silicon
 Village
 area
 on
 the
 exhibit
 floor
 to
 help
 address
 the
 interdependence
 between
 Silicon
 and
EDA
 vendors.
 Attendees
 have
 the
 opportunity
 to
 interact
 with
 both
 EDA
 and
 silicon
 vendors
concurrently
 and
 find
 solutions
 from
 design
 concept
 to
 working
 silicon.

n I n f o r m a t i o n
Exhibits
There
 will
 be
 over
 250
 exhibiting
 companies
 at
 the
 37th
 DAC.
 For
 a
 listing
 and
 other
information,
 see
 pages
 6-7.
 Children
 under
 the
 age
 of
 14
 will
 NOT
 be
 allowed
 in
 the
 exhibit
hall
 or
 demo
 suite
 area.
Silicon Village
DACnet-2000
Exhibit Information
The
 Design
 Automation
 Conference
 is
 continuing
 to
 feature
 Silicon
 Village
 in
acknowledgment
 of
 the
 trend
 of
 EDA
 companies,
 silicon
 vendors,
 and
 IP
 providers
collaborating
 to
 meet
 the
 challenges
 of
 electronic
 design.
 Silicon
 Village
 will
 facilitate
 the
interchange
 amongst
 these
 industries.
 Now
 attendees
 and
 customers
 will
 have
 one
 venue
 to
find
 the
 tools,
 methodologies,
 and
 silicon
 solutions
 they
 need.
 Visit
 the
 Silicon
 Village
 on
the
 exhibit
 floor
 during
 regular
 exhibit
 hours.
Free Monday Exhibit-Only Passes
The
 37th
 DAC
 is
 offering
 Free
 Monday
 Exhibit-Only
 Passes.
 These
 passes
 are
 good
 only
 on
Monday,
Ju ne
 5,
2 000,
 and
 are
o btainable
f rom
 DAC
 Exhibitors,
t he
 DAC
F ree
 Monday
 Hot
 Line:
toll-free
 1-800-321-4573,
 1-303-530-4333,
 or
 on
l ine
a t
 w
w
w
.
d
a
c
.
c
o
m
/
f
r
e
e
m
o
n
.
h
t
m
l.
Advance
 registration
 for
 the
 Free
 Monday
 Exhibit-Only
 Passes
 ends
 May
 18,
 2000.
 After
 May
 18,
2000,
F ree
M onday
E xhibit-Only
P asses,
w ill
b e
a vailable
A T-CONFERENCE
 ONLY,
 at
n o
c harge.
Exhibit-Only Admission
To
 enter
 the
 exhibits
 Monday,
 June
 5,
 2000,
 through
 Wednesday,
 June
 7,
 2000,
 purchase
an
 Exhibit-Only
 Pass
 for
 $40.00.
 To
 avoid
 long
 lines,
 register
 in
 advance
 by
 using
 the
registration
 form
 located
 on
 the
 inside
 back
 cover,
 or
 register
 on-line
 at
 www.dac.com.
Exhibitor Presentations
Exhibitor
 Presentations
 will
 be
 held
 on
 Monday,
 June
 5,
 2000,
 from
 9:00
 AM
 to
 6:00
 PM.
 The
Exhibitor
 Presentations
 will
 be
 20-minute
 time
 slots
 with
 six
 sessions
 running
 concurrently.
For
 more
 information
 see
 the
 abstracts
 and
 matrix
 for
 Exhibitor
 Presentations
 on
 pages
8-17.
 No
 badge
 needed.
The
 Design
 Automation
 Conference
 is
 pleased
 to
 provide
 conference
 attendees
 and
 exhibitors
the
 DACnet
 Mail
 and
 Information
 System.
 The
 DACnet
 system
 allows
 attendees
 direct
 internet
access
 during
 the
 duration
 of
 DAC.
 Once
 established,
 users
 can
 log-in
 to
 any
 of
 the
 DACnet
stations
 at
 the
 conference.
Each
 workstation
 will
 have
 a
 browser
 available
 for
 immediate
 www
 access,
 and
 telnet
 access.
If
 you
 would
 like
 to
 establish
 an
 email
 account
 at
 DAC,
 just
 follow
 the
 instructions
 on-site.
Pre-registration
 is
 not
 required
 or
 allowed
 this
 year.
 If
 you
 have
 any
 questions
 about
DACnet,
 email
 kevin@dac.com.
exhibitor
info
5

exhibitor
info
6
sv
sv
sv
sv
sv
sv
sv
sv
sv
Exhibitor Listing
The
 Design
 Automation
 Conference
 continues
 to
 combine
 its
 outstanding
 technical
 program
 with
exhibits
 featuring
 over
 230
 of
 the
 world’s
 top
 CAD/CAE
 companies.
 Exhibits
 are
 located
 in
 the
 South
Hall
 of
 the
 Los
 Angeles
 Convention
 Center.
 We
 are
 pleased
 to
 have
 the
 following
 exhibitors
 this
 year.
COMPANY NAME BOOTH # COMPANY NAME BOOTH #
0-IN
 DESIGN
 AUTOMATION ..........................4047
3
 DSP
 CORP. ..........................................SV39
ACE
 ASSOCIATED
 COMPILER
 EXPERTS
 BV............4706
ACTEL
 CORP. ..........................................3529
ADVANSIS ............................................4753
AGILENT
TECHNOLOGIES ..............................2553
ALBA
 CENTRE
 (THE) ....................................SV6
ALCATEL
 MICROELECTRONICS
 USA....................SV31
ALDEC,
 INC. ..........................................3009
ALTERA
 CORP. ........................................4001
ALTERNATIVE
 SYSTEM
 CONCEPTS,
 INC...............4721
ALTIUS
 SOLUTIONS,
 INC ............................4845
AMERICAN
 MICROSYSTEMS,
 INC. ....................SV21
ANSOFT
 CORP. ........................................3811
ANTRIM
 DESIGN
 SYSTEMS,
 INC. ....................4459
APLAC
 SOLUTIONS
 CORP. ............................3360
APPLIED
 SIMULATION
 TECHNOLOGY..................4441
APPNET,
 INC. ........................................4852
APTIX
 CORP...........................................4029
ARC
 CORES
 LTD. ......................................4039
ARCADIA
 DESIGN
 SYSTEMS,
 INC.....................4417
ARCHELON
 INC. ......................................4708
AREXSYS
 INC. ........................................3147
ARISTO
 TECHNOLOGY,
 INC. ..........................4545
ARM,
 INC. ............................................SV28
ARTISAN
 COMPONENTS,
 INC. ........................2929
ARTWORK
 CONVERSION
 SOFTWARE
 INC. ............4320
ATMOS
 CORP. ........................................4712
AUSTRIA
 MIKRO
 SYSTEME
 INTERNATIONAL
 AG........SV9
AUTOMATA
 DESIGN,
 INC. ............................2611
AVANT!
 CORP. ........................................3117
AXIS
 SYSTEMS ........................................4145
AXYS
 DESIGN
 AUTOMATION,
 INC. ..................3767
BARCELONA
 DESIGN ..................................4161
BILLIONS
 OF
 OPERATIONS
 PER
 SECOND
 (BOPS) ....SV17
BLUE
 PACIFIC
 COMPUTING,
 INC. ..................4607
BTA
 TECHNOLOGY,
 INC. ..............................4433
BYTEK
 DESIGNS,
 INC. ................................2415
C
 LEVEL
 DESIGN,
 INC.................................4819
CADABRA
 DESIGN
 AUTOMATION ....................3129
CADENCE
 DESIGN
 SYSTEMS,
 INC.....................3301
CADMOS
 DESIGN
 TECHNOLOGY,
 INC. ................4837
CAE
 PLUS,
 INC. ......................................3705
CAHNERS
 BUSINESS
 INFORMATION ..................3929
CARDTOOLS
 SYSTEMS..................................2307
CAST,
 INC. ..........................................4715
CCAES.COM............................................2637
CHIP
 EXPRESS
 CORP. ..................................SV1
CHRONOLOGY
 CORP. ..................................3517
CIRCUIT
 SEMANTICS,
 INC. ..........................4517
CMP ....................................................SV33
CMP
 MEDIA
 -
 MILLER
 FREEMAN ......................3017
CO-DESIGN
 AUTOMATION,
 INC. ....................3259
COMCAD
 GMBH
 ANALOG
 DESIGN
 SUPPORT ..........3267
COMPUTER
 GLOBAL,
 INC. ............................4544
CONCEPT
 ENGINEERING
 GMBH ......................3066
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CONVERGENCE
 DESIGN
 INC...........................4155
COWARE,
 INC. ........................................4745
CREOSYS
 INC. ........................................2757
CSELT
 SPA ............................................4653
CYNAPPS ..............................................3667
CYPRESS
SEMICONDUCTOR ..........................4253
D2W
 DESIGN-TO-WAFER
 SERVICES ..................4812
DENALI
 SOFTWARE,
 INC. ............................2617
DERIVATION
 SYSTEMS,
 INC. ........................4152
DESIGN
 &
 REUSE ......................................3153
DESIGNSOFT,
 INC. ..................................3461
DSM
 TECHNOLOGIES,
 INC. ..........................3362
DUALSOFT
 LLC ........................................2313
DYNALITH
 SYSTEMS,
 INC. ............................2453
EDA
 STANDARDS ......................................3711
EDACONNECT.COM ....................................3059
ELECTRONICS
WORKBENCH ..........................3547
ENGINEERING
 DATAXPRESS,
 INC. ..................4220
EONIC
 SYSTEMS
 INC. ................................4810
ESCALADE
 CORP.......................................4229
EXEMPLAR
 LOGIC,
 INC. ..............................3453
FARADAY
 TECHNOLOGY
 CORP. ........................3460
FINTRONIC
 USA,
 INC. ..............................2728
FLUENCE
 TECHNOLOGY ................................3653
FORESIGHT
 AT
 NU
 THENA
 SYSTEMS,
 INC. ..........4401
FREQUENCY
 TECHNOLOGY,
 INC. ......................3837
FRONTEC
 MICORELECTRONICS
 AB ....................SV23
FRONTIER
 DESIGN,
 INC. ............................2213
FTL
 SYSTEMS,
 INC. ..................................3347
GENESYS
 TESTWARE ..................................4546
GET2CHIP.COM,
 INC. ................................2019
GLOBAL
 UNICHIP
 CORP. ..............................SV35
GRIDWARE,
 INC. ....................................3363
HDAC,
 INC. ..........................................4818
HEWLETT-PACKARD
 CO. ..............................3617
IBM
 MICROELECTRONICS
 CORP. ....................SV25
IKOS
 SYSTEMS
 INC. ..................................3817
IMEC ..................................................3462
IMEC/EUROPRACTICE ................................SV32
IMODL,
 INC. ..........................................4061
INCENTIA
 DESIGN
 SYSTEMS,
 INC. ..................4561
INSILICON
 CORP. ....................................2734
INTEGRATED
 MEASUREMENT
 SYSTEMS ................3159
INTEGRATED
 SILICON
 SYSTEMS
 LTD. ................4447
INTELLITECH
 CORP. ..................................3941
INTERCEPT
 TECHNOLOGY
 INC. ......................3001
INTERNET
 BUSINESS
 SYSTEMS,
 INC. ................4814
INTERNETCAD.COM,
INC. ............................2713
INTERRA,
 INC. ......................................2537
INTERWEAVE
 TECH ....................................3966
INTIME
 SOFTWARE,
 INC. ............................2345
INTRINSIX
 CORP. ....................................3753
IOTA
 TECHNOLOGY
 INC. ..............................2861
IQXPERT ..............................................3341
KLUWER
 ACADEMIC
 PUBLISHERS ....................4222
LATTICE
 SEMICONDUCTOR
 CORP./
 VANTIS
 CORP. ..2529

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sv
sv
sv
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sv
LEGEND
 DESIGN
 TECHNOLOGY,
 INC. ................4329
LEVETATE
 DESIGN
 SYSTEMS,
 INC.....................4719
LEXRA,
 INC. ..........................................2562
LIBRARY
 TECHNOLOGIES,
 INC. ......................2613
LOGIC
 EXPRESS
 SYSTEMS
 INC. ......................4067
LOGICVISION,
 INC. ..................................4011
LSI
 LOGIC
 CORP. ....................................2544
MAGMA
 DESIGN
 AUTOMATION,
 INC. ................2329
MATHMATICAL
 SYSTEMS
 INC. ........................2867
MATRICUS
 INC. ......................................2732
MEMSCAP..............................................4829
MENTOR
 GRAPHICS
 CORP. ..........................3501
MICRO
 MAGIC,
 INC. ................................2401
MICROCOSM
 TECHNOLOGIES,
 INC. ..................2237
MIPS
 TECHNOLOGIES,
 INC. ..........................SV27
MITSUI
 &
 CO.,
 LTD. ..................................2767
MODEL
 TECHNOLOGY
 INC. ............................3353
MONTEREY
 DESIGN
 SYSTEMS ..........................3137
MORGAN
 KAUFMANN
 PUBLISHERS,
 INC. ............2635
MOSCAPE,
 INC. ......................................4645
MOSIS..................................................SV13
MOSYS,
 INC. ..........................................3061
MYCAD,
 INC. ........................................2641
NASSDA
 CORP. ........................................2407
NEC
 ELECTRONICS ....................................4539
NEO
 LINEAR,
 INC.....................................2661
NORDIC
 VLSI
 ASA ....................................SV14
NOVAS
 SOFTWARE,
 INC. ..............................4501
NUMERICAL
 TECHNOLOGIES,
 INC. ..................2512
NURLOGIC
 DESIGN,
 INC. ............................4053
OEA
 INTERNATIONAL,
 INC. ..........................4429
OPTEM
 ENGINEERING
 INC. ..........................4322
PADS
 SOFTWARE ......................................3211
PALMCHIP
 CORP. ....................................2113
PIVOTAL
TECHNOLOGIES ..............................SV22
PLATFORM
 COMPUTING
 CORP. ......................3447
PRENTICE
 HALL-PTR ..................................2629
PROLIFIC,
 INC. ......................................2314
PROSPER
 DESIGN
 SYSTEMS
 PTE
 LTD. ................2461
QTHINK................................................4445
QUICKLOGIC
 CORP. ....................................SV5
ROUTECH,
 INC. ......................................2207
RUBICAD
 CORP. ......................................4111
SAGANTEC ............................................4529
SAPPHIRE
 DESIGN
 AUTOMATION ....................3639
SENTE,
 INC. ..........................................3717
SICAN
 MICROELECTRONICS
 CORP. ..................3057
SIGDA/DAC
 UNIVERSITY
 BOOTH ....................2811
SILICON
 AUTOMATION
 SYSTEMS
 LTD. ................2339
SILICON
 CRAFT
 INC. ................................2966
SILICON
 FOREST
 RESEARCH,
 INC. ..................3441
SILICON
 GRAPHICS
 COMPUTER
 SYSTEMS
 INC. ......3553
SILICON
 INTEGRATION
 INITIATIVE,
 INC.
 (SI2) ..4019
SILICON
 METRICS
 CORP. ............................3759
SILICON
 PERSPECTIVE
 CORP.........................4553
SILICON
 VALLEY
 RESEARCH,
 INC.....................3329
SILICON
 VALUE........................................3367
SILICONX ..............................................SV10
SILVACO
INTERNATIONAL ............................2519
SIMPLEX
 SOLUTIONS,
 INC. ..........................2501
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Exhibitor Listing
SIMPOD,
 INC. ........................................2439
SIMUCAD,
 INC. ......................................4411
SIMULATION
 MAGIC,
 INC. ..........................4739
SIMUTECH,
 LLC ......................................2219
SIMUTEST,
 INC. ......................................2711
SLICEX,
 INC. ..........................................SV18
SNAKETECH
 CORP. ....................................3647
SONICS
 INC. ..........................................2961
SUMMUS
 DESIGN
 CO.,
 LTD. ..........................4711
SUN
 MICROSYSTEMS ..................................3317
SYCON
 DESIGN,
 INC. ................................4507
SYNAPTICAD
 INC. ....................................2315
SYNCHRONICITY,
INC. ..............................3537
SYNOPSYS
INTEROPERABILITY ......................4119
SYNOPSYS,
 INC. ......................................4201
SYNPLICITY,
 INC. ....................................2801
SYNTEST
 TECHNOLOGIES,
 INC. ......................2647
TANNER
 EDA ..........................................3111
TARGET
 COMPILER
 TECHNOLOGIES
 N.V. ............3160
TECH
 ONLINE ..........................................3661
TECHMATE
 INC. ......................................3158
TECHNICALLY
 SPEAKING,
 INC. ......................2631
TEMENTO
 SYSTEMS ....................................4453
TENSILICA,
 INC. ....................................3567
TERA
 SYSTEMS
 INC. ..................................4353
TERADYNE,
 INC. ......................................4822
TEXAS
 INSTRUMENTS
 INC.............................4639
THARAS
 SYSTEMS......................................2301
TRANSEDA,
 INC.......................................2729
TRANSLOGIC
 USA
 CORP...............................4540
TRANSMODELING,
 INC. ..............................4611
TRISCEND
 CORP. ......................................SV37
TSMC
 NORTH
 AMERICA ................................SV11
ULTIMA
 INTERCONNECT
 TECHNOLOGY ................3029
UNITED
 MICROELECTRONICS
 CORP.
 GROUP ........SV19
V
 DESIGN/UNIQUE
 SOFTWARE
 SERVICES,
 INC. ....4710
VALIDITY
 DESIGN
 AUTOMATION,
 INC. ..............2957
VALIOSYS
 SA ..........................................2561
VALOR
 COMPUTERIZED
 SYSTEMS......................3947
VAST
 SYSTEMS
 TECHNOLOGY
 CORP. ..................4361
VAUTOMATION,
 INC...................................SV15
VERIBEST,
 INC. ......................................3801
VERISITY
 DESIGN,
 INC...............................3829
VERITOOLS,
 INC. ....................................3701
VERPLEX
 SYSTEMS,
 INC. ..............................2319
VIEWLOGIC
 SYSTEMS
 &
 SUMMIT
 DESIGN ............3101
VIRAGE
 LOGIC
 CORP. ................................2229
VIRTUAL
 COMPONENT
 EXCHANGE ....................2662
VIRTUAL
 SILICON
 TECHNOLOGY,
 INC. ..............4337
VSI
 ALLIANCE ..........................................SV7
WESTERN
 DESIGN
 CENTER ..............................SV3
X-TEK
 CORP. ..........................................4405
XENTEC
 INC. ..........................................4153
XILINX,
 INC. ........................................3629
XPEDION
 DESIGN
 SYSTEMS,
 INC ....................2857
Y
 EXPLORATIONS,
 INC. ..............................3853
ZUKEN-REDAC,
 INC. ................................2601
exhibitor
info
7

T
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9:00
9:20
9:40
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2
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2:40
3:00
3:20
3:40
4:00
4:20
4:40
5:00
5:20
5:40
8
ROOM 403
AVANT! CORP.
SYNPLICITY, INC.
MAGMA D.A., INC.
SAGANTEC
EXEMPLAR
LOGIC, INC.
VERISITY
DESIGN, INC.
XILINX, INC.
CYPRESS
SEMICONDUCTOR
CADENCE DESIGN
SYSTEMS, INC.
ROOM 403
VAST SYSTEMS
TECHNOLOGY CORP.
ZUKEN-REDAC, INC.
Exhibitor Presentation Schedule
ROOM 404
DUALSOFT LLC
MICROCOSM
TECHNOLOGIES, INC.
0-IN DESIGN
AUTOMATION
ARCADIA DESIGN
SYSTEMS, INC.
VALIDITY DESIGN
AUTOMATION, INC.
A LT E R N ATIVE SYSTEM
CONCEPTS, INC.
GENESYS
TESTWARE
INSILICON CORP.
NEO LINEAR, INC.
ROOM 404
SONICS INC.
CONCEPT
ENGINEERING GMBH
ESCALADE CORP. FTL SYSTEMS, INC.
SYNOPSYS, INC.
MENTOR
GRAPHICS CORP.
TRANSEDA, INC.
HEWLETT-
PACKARD CO.
PADS SOFTWARE
MONTEREY DESIGN
SYSTEMS
SIMPLEX
SOLUTIONS, INC.
CHRONOLOGY
CORP
ALTERA CORP.
TEXAS
INSTRUMENTS INC.
LEGEND DESIGN
TECHNOLOGY, INC.
OPTEM
ENGINEERING INC.
ROOM 406
OEA I N T E R N AT I O N A L ,
INC.
CADMOS DESIGN
TECHNOLOGY, INC.
BOPS
ENGINEERING
DATAXPRESS, INC.
INCENTIA DESIGN
SYSTEMS, INC.
SICAN MICRO-
ELECTRONICS CORP.
ROOM 408A
APTIX CORP.
ARTISAN
COMPONENTS, INC.
DENALI
SOFTWARE, INC.
12:00
 –
 2:00
 LUNCH
 BREAK
ROOM 408B
VIEWLOGIC
SYSTEMS, INC.
These 20-minute presentations by DAC Exhibitors are intended to efficiently introduce you to new product and application information.
Badges are not required for admission to the Exhibitor Presentations.
ROOM 411
THARAS
SYSTEMS INC.
AXIS SYSTEMS NASSDA CORP.
MODEL
TECHNOLOGY INC.
SNAKETECH CORP. TENSILICA, INC.
VIRAGE
LOGIC CORP.
ULTIMA
INTERCONNECT
SIMUTEST, INC. IKOS SYSTEMS INC. RUBICAD CORP.
QTHINK
GROUP, INC.
PIVOTAL
TECHNOLOGIES
ROOM 406
SYNTEST
TECHNOLOGIES, INC.
BARCELONA
DESIGN
CADABRA DESIGN
AUTOMATION
ROOM 408A
QUICKLOGIC CORP.
CMP COWARE, INC.
BTA
TECHNOLOGY, INC.
CIRCUIT
SEMANTICS, INC.
INTERCEPT
TECHNOLOGY INC.
NURLOGIC
DESIGN, INC.
UMC GROUP CSELT SPA
PLATFORM
COMPUTING CORP.
CO-DESIGN
AUTOMATION, INC.
AREXSYS INC.
LOGICVISION, INC.
SENTE, INC.
PROLIFIC, INC.
VERPLEX
SYSTEMS, INC.
INTRINSIX CORP. TRISCEND CORP.
ANSOFT CORP. SIMUTECH, LLC
SILICON FOREST
RESEARCH, INC.
SILICON A U TO M AT I O N
SYSTEMS LTD.
ROOM 408B
TERA SYSTEMS INC.
AMERICAN MICRO-
SYSTEMS, INC.
ARISTO
TECHNOLOGY, INC.
AGILENT
TECHNOLOGIES
NUMERICAL
T E C H N O L O G I E S , INC.
COMCAD GMBH
ANALOG DESIGN
MYCAD, INC.
NORDIC VLSI ASA
ROOM 411
BLUE PACIFIC
COMPUTING, INC.
TARGET COMPILER
TECHNOLOGIES N.V.
HDAC, INC.
THE ALBA CENTRE
IMEC
CAE PLUS, INC. EDACONNECT.COM MOSIS
FINTRONIC
USA, INC.
SGI CAST, INC.
SIMPOD, INC.
SILICON CRAFT INC. SILICON VALUE
Y EXPLORATIONS,
INC.
SYCON DESIGN, INC.
SILICON VALLEY
RESEARCH, INC.
NOVAS
SOFTWARE, INC.
SLICEX, INC. IMS
AUSTRIA MIKRO
SYSTEME
SUMMUS DESIGN
CO., LTD.
XPEDION DESIGN
SYSTEMS, INC
ARC CORES LTD.
INTERRA, INC.
MATHMATICAL
SYSTEMS INC.
SIMUCAD, INC. SI2
SILICON VILLAGE PARTICIPANTS ARE SHADED IN GREY.
ALCATEL MICRO-
ELECTRONICS USA
DYNALITH
SYSTEMS, INC.
D2W DESIGN-TO-
WAFER SERVICES
ACE A S S O C I AT E D
COMPILER EXPERTS B V
ROUTECH, INC.
GLOBAL UNICHIP
CORP.

Exhibitor Presentation Abstracts
0-IN
 Design
 Automation 9:40
Learn
 how
 0-In’s
 white-box
 verification
 tools
 can
 help
 you
 zero-in
 on
 tough
 bugs
 -
without
 any
 design,
 testbench,
 or
 simulation
 changes.
ACE
 Associated
 Compiler
 Experts
 bv 5:00
Generating
 C
 compilers
 for
 flexible
 architectures
 using
 the
 CoSy
 compiler
 development
system.
Agilent
Technologies 3:00
Agilent
 EEsof
 EDA
 presents
 its
 Advanced
 Design
 System
 family
 of
 software
 products
 for
designing
 state-of-the-art
 wireless
 communication
 systems.
The
 Alba
 Centre 3:00
The
 Alba
 Centre
 is
 the
 hub
 of
 a
 Scottish
 initiative
 that
 is
 driving
 the
 future
 of
 electronic
design.
Alcatel
 Microelectronics
 USA 4:00
Alcatel
 Microelectronics
 offers
 mixed-signal
 systems-on-chip
 and
 specific
 interface
 application
 circuits,
 in
technologies
 as
 CMOS,
 BiCMOS,
 High-Voltage
 (HIBIMOSF,
 Intelegent
 Interface
 Technology)
 and
 BiCMOS R
F
.
Altera
 Corp. 5:40
Altera’s
s ystem-on-a-programmable-chip
( SOPC)
s olution
c ombines
 programmable
s ilicon,
s oftware,
and
 intellectual
 property
 to
 provide
 users
 with
 productivity
 advantages
 in
 system-level
 integration.
Alternative
 System
 Concepts,
 Inc. 10:40
Ask
 ASC
 about
 XML
 implementation
 of
 IP
 and
 SOC
 solutions
 including
 translation,
 rules
checking,
 test
 insertion
 and
 low
 power
 optimization.
American
 Microsystems,
 Inc.
 2:20
American
 Microsystems,
 Inc.
 offers
 the
 only
 ASIC
 solution
 for
 high-density
 Virtex
 and
Apex
 FPGAs
 with
 its
 targeted
 XLArray
 family.
Ansoft
 Corp. 10:40
Ansoft
 provides
 high
 performance
 solutions
 for
 IC
 packaging,
 high
 speed
 printed
 circuit
boards
 (PCBs),
 RFICs
 and
 EMI
 analysis.
Aptix
 Corp. 9:00
Aptix
 will
 provide
 a
 brief
 overview
 of
 its
 easy-to-use
 SoC
 emulation
 product
 line
 and
 its
activities
 at
 DAC
 including
 floor
 demonstrations
 of
 customer
 emulation
 environments.
Arcadia
 Design
 Systems,
 Inc. 10:00
Can't
 meet
 timing?
 Have
 an
 unroutable
 design?
 Use
 Mustang
 on
 datapath
 intensive
designs
 to
 reduce
 iterations
 and
 optimize
 throughput.
ARC
 Cores
 Ltd. 4:40
ARC
 Cores
 presents
 details
 of
 how
 the
 world's
 first
 32-bit
 user
 configurable
 microprocessor
remains
 unique
 in
 allowing
 designers
 to
 significantly
 reduce
 product
 development
 time.
Arexsys
 Inc. 2:40
Leader
 in
 System
 Design
 Automation
 delivers:
 ArchiMate
 for
 architecture
 exploration
(partitioning,
 synthesis,
t argeting);
 and
C osiMate
 a
 system
m odeling
 co-simulation
b ackplane.
Aristo
 Technology,
 Inc. 2:40
Aristo
 provides
 critical
 technology
 for
 automating
 block-based
 design
 --
 a
 methodology
which
 is
 transforming
 the
 silicon
 die
 into
 a
 full-scale
 system-on-chip.
Artisan
 Components,
 Inc. 9:20
Abstract
 not
 available.
e
x
h
i
b
i
t
o
r
p
r
e
s
e
n
t
a
t
i
o
n
s
9

e
x
h
i
b
i
t
o
r
p
r
e
s
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n
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t
i
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n
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10
Exhibitor Presentation Abstracts
Austria
 Mikro
 Systeme
 International
 AG 5:40
Austria
 Mikro
 Systeme
 International
 is
 a
 Design
 and
 Manufacture
 of
 Mixed
 mode,
 CMOS,
BiCMOS,
 and
 SiGe
 circuts
 for
 RF,
 Automotive,
 and
 high
 voltage
 applications.
Avant!
 Corp. 9:00
Avant!
 Corporation,
 the
 fastest
 growing
 EDA
 company
 in
 history,
 will
 announce
 its
 latest
technology
 breakthroughs
 and
 product
 achievements.
Axis
 Systems 9:20
Axis
 System
 brings
 design
 verification
 to
 the
 next
 level
 by
 introducing
 a
 breakthrough
 technology
to
 further
 extend
it s
v erification
a cceleration
 leadership.
B e
 there
li ve
f or
t he
a nnouncement.
Barcelona
 Design 11:20
Barcelona’s
 design
 automation
 engine
 allows
 analog
 and
 mixed-signal
 engineers
 to
create
 optimal
 designs
 in
 a
 fraction
 of
 the
 time
 it
 takes
 today.
Billions
 of
 Operations
 Per
 Second 9:40
BOPS,
 Inc.
 develops
 and
 licenses
 the
 highest-performance,
 scalable
 and
 reusable
 DSP
 cores
 and
world-class
 compiler
 and
 software
 tool
 products
 targeted
 for
 high-volume
 SOC
 based
 applications.
Blue
 Pacific
 Computing,
 Inc. 2:00
Blue
 Pacific
 Computing
 will
 demonstrate
 their
 BlueHDL
 simulation
 tools.
 BlueHDL
 supports
VHDL,
 Verilog
 and
 SystemC
 running
 under
 Linux,
 Solaris
 and
 Windows.
BTA
 Technology,
 Inc. 2:40
Accuracy
 is
 our
 claim
 to
 fame.
 Accurate,
 multi-million
 transistor
 circuit
 simulator.
Accurate
 SPICE
 modeling
 software
 for
 DC,
 AC,
 RF,
 Noise,
 Interconnect,
 and
 SOI
 devices.
Cadabra
 Design
 Automation 11:40
Cadabra's
 layout
c reation
 technology
p rovides
t he
 foundation
 for
 Library
 Factories
 which
help
 chip
 designers
 achieve
 higher
 performance
 designs
 while
 reducing
 development
 time.
Cadence
 Design
 Systems,
 Inc. 11:40
Cadence,
 the
 technology
 leader
 in
 design
 software
 and
 services,
 will
 present
 its
 latest
solutions
 in
 synthesis,
 place-and-route,
 verification,
 system-level
 and
 high-speed
 PCB
 design.
CadMOS
 Design
 Technology,
 Inc. 9:20
CadMOS
 will
 present
 on
 how
 to
 prevent
 noise
 wrecking
 havoc
 with
 your
 UDSM
 design's
productivity,
 quality
 and
 performance.
CAE
 Plus,
 Inc. 3:40
Design
 in
 HDL,
 verify
 in
 C!
 CAE
 Plus
 enables
 SOC
 designers
 to
 verify
 in
 fast,
 RTL-accurate
C
 while
 continuing
 to
 use
 existing
 HDL
 design
 methods
 and
 tools.
CAST,
 Inc. 4:20
Cost-effective
 IP
 and
 innovative
 design
 data
 management
 tools
 help
 designers
 replace
obsolete
 parts
 and
 integrate
 functions
 for
 SoC
 design.
Chronology
 Corp. 5:20
Testbench
 automation
 for
 all
 members
 of
 your
 design
 team,
 at
 all
 levels
 of
 the
 design.
Experience
 Chronology's
 latest
 QuickBench ® Verification
Suite.
Circuit
 Semantics,
 Inc. 3:00
The
 leading
 provider
 of
 timing
 and
 characterization
 solutions
 for
 high
 performance
 ICs,
multiple
 types
 of
 IP,
 and
 standard
 cells.
CMP 2:20
CMP
 is
 a
 manufacturing
 broker
 for
 ICs,
 MCMs,
 and
 MEMS,
 for
 prototyping
 and
 low
 volume
production.

Exhibitor Presentation Abstracts
Co-Design
 Automation,
 Inc. 4:40
For
 advanced
 simulation
 technology
 that
 combines
 the
 best
 of
 Verilog,
 C
 and
 SUPERLOG
for
 SoC
 designs,
 check
 out
 Co-Design
 Automation.
ComCAD
 GmbH 11:00
Need
 a
 tool
 that
 works
 out
 your
 analog
 circuits?
 Take
 Size!
 ComCAD
 ◆-
 inventing
 analog
synthesis.
Concept
 Engineering
 GmbH 2:20
Concept
 Engineering
 provides
 innovative
 schematic
 generation
 and
 viewing
 technology
for
 commercial
 EDA
 vendors,
 in-house
 CAD
 departments
 and
 IC
 and
 FPGA
 designers.
CoWare,
 Inc. 2:20
CoWare,
 the
 leading
 system-level
 design
 company,
 cuts
 SoC
 design
 time
 in
 half
 with
 a
proven
 hardware/software
 co-design
 methodology
 and
 tools.
CSELT
 SpA 4:00
CSELT
 introduces
 you
 to
 an
 effective
 methodology
 for
 designing
 ICT
 products
 based
 on
Intellectual
 Properties
 (VIP
 Library)
 and
 system
 emulation.
Cypress
Semiconductor 11:20
The
 best
 CPLDs
 in
 the
 World
 just
 got
 Better
 -
 Familiarize
 yourself
 with
 Cypress's
 Ultra37000,
Quantum38k,
 Delta39K
 and
 our
 new
 Warp
 Enterprise
 Edition
 CPLD
 development
 system.
D2W
 Design-to-Wafer
 Services 4:40
Introducing
 D2W,
 offering
 the
 fastest,
 most
 hassle-free
 way
 to
 move
 your
 design
 into
manufacturing,
 with
 precision,
 automated
 tapeout
 services.
Denali
 Software,
 Inc. 9:40
Memory
 subsystems
 are
 now
 a
 critical
 design
 bottleneck.
 Denali
 launches
 an
 integrated
solution
 for
 memory
 subsystems,
 from
 architecture
 to
 implementation.
DualSoft,
 LLC 9:00
ReviewVer
 and
 ReviewVHDL
 are
 Reuse-enabling
 tools
 for
 HDL
 designs.
 Developed
consistent,
 well-documented
 and
 "reuse-ready"
 designs
 with
 these
 tools!
Dynalith
 Systems,
 Inc. 4:20
Dynalith
 announces
 iSAVE,
 industry’s
 first
 toolkit
 for
 early
 C
 language
 model
 verification
of
 the
 planned
 ASIC
 in
 its
 hardware
 environment.
EDAConnect.com 3:40
EDAConnect.com,
t he
 Internet-based
E DA
c ompany,
p resents
t he
n ext
g eneration
 solution
f or
P CB
and
 Systems
 Design
 with
 all
 business
 transactions
 performed
 interactively
 using
 the
 World
 Wide
 Web.
Engineering
 DataXpress,
 Inc. 10:00
Equipped,
 Dedicated,
 and
 Xperienced
 in
 providing
 quality
 interoperability
 and
 data
integration
 product
 solutions
 for
 over
 15
 years!
Escalade
 Corp. 2:40
Escalade
 helps
 streamline
 RTL
 design
 and
 IP
 reuse.
 Come
 see
 our
 latest
 tool,
 Design
Extractor,
 and
 learn
 how
 to
 understand
 legacy
 designs
 dramatically
 faster.
Exemplar
 Logic,
 Inc. 10:20
Exemplar
 Logic
 is
 the
 leading
 provider
 of
 FPGA
 synthesis
 solutions.
 LeonardoSpectrum
 and
LeonardoInsight
 tools
 provide
 superior
 synthesis
 results.
Fintronic
 USA,
 Inc. 4:00
FinFarm:
 the
 Verilog
 simulation
 farm
 that
 enables
 one
 engineer
 to
 use
 hundreds
 of
workstations
 running
 Super
 FinSim,
 the
 best
 Verilog
 simulator.
e
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Exhibitor Presentation Abstracts
FTL
 Systems,
 Inc. 2:40
Capacity,
 Performance
 and
 Language
 Fidelity
 are
 at
 your
 Service
 with
 FTL
 System's
Auriga
 HDL
 compiler/simulator
 products.
Genesys
 Testware 11:00
Genesys
 Testware
 provides
 complete
 manufacturing
 test
 automation
 solutions
 to
 designers
 of
System
 on
 Chip,
 that
 improve
 designer
 productivity,
 improve
 product
 quality
 and
 reduce
 unit
 cost.
Global
 UniChip
 Corp. 5:40
UniChip
 speeds
 up
 your
 SoC
 design
 to
 market
 with
 IPs,
 design
 service,
 and
 turnkey
solutions.
Bu siness
mod els,
hig h
per formance
I Ps,
 and
DS M
des ign
flow
will 
b e
pre sented.
HDAC,
 Inc. 2:40
HDAC
 (www.hdac.com)
 presents
 Solidify,
 a
 new
 static
 functional
 verification
 tool
 that
"fundamentally
 changes
 the
 way
 designers
 do
 design
 and
 verification."
Hewlett-Packard
 Co. 4:00
Come
 see
 how
 the
 original
 company
 of
 inventors
 is
 reinventing
 EDA
 Design.
IKOS
 Systems
 Inc. 11:00
IKOS
 Systems
 is
 a
 technology
 leader
 in
 high-performance
 design
 verification
 solutions
delivering
 acceleration
 and
 emulation
 performance
 earlier
 in
 your
 design
 flow.
IMEC 3:20
Design
 for
 the
 iHome:
 C++-based
 object
 oriented
 design,
 low
 power
 memory
management,
 reconfigurable
 hardware
 for
 WLAN,
 MPEG-4
 multimedia,
 "smart"
 appliances.
Incentia
 Design
 Systems,
 Inc. 10:20
Incentia
 Design
 Systems
 provides
 a
 new
 class
 of
 design
 synthesis
 tools
 for
 VDSM
 SOC
designs.
inSilicon
 Corp. 11:20
inSilicon
 offers
 semiconductor
 IP
 cores
 (USB,
 VCI,
 Ethernet,
 IEEE
 1394,
 PCI-X,
 PCI,
 IrDA
and
 AGP)
 and
 software
 for
 SoC
 and
 embedded
 designs.
Integrated
 Measurement
 Systems,
 Inc. 5:20
Engineering
 validation
 resolves
 failures
 at
 first-silicon
 when
 the
 virtual
 electronic
 design
model
 is
 made
 into
 a
 real
 physical
 working
 prototype.
Intercept
 Technology
 Inc. 3:20
Intercept
 Technology
 presents
 the
 latest
 Pantheon/MoZaiX
 solutions
 for
 RF,
 signal
integrity,
 DFX,
 and
 library
 management
 for
 PCB/Hybrid/MCM
 design.
Interra,
 Inc. 5:00
Interra,
 Inc.,
 the
 technology
 leader
 for
 EDA
 building
 blocks,
 presents
 its
 latest
 highperformance
product
 offerings
 on
 functional
 design
 creation
 and
 verification.
Intrinsix
 Corp. 10:20
Find
 out
 how
 the
 largest
 independent
 ASIC
 and
 system
 design
 services
 company
 can
 help
you
 specify
 optimal
 strategies
 for
 system
 development
 and
 verification.
Legend
 Design
 Technology,
 Inc. 3:20
An
ad vanced
Mem ory
In stance
Ch aracterization
p rogram
( MemChar)
is
p resented.
 
Op erable
on
 Internet,
Me mChar’s
 benefits
a re
ac curacy,
pe rformance,
fle xibility,
an d
ea sy-to-u
s
e
.
LogicVision,
 Inc. 3:00
LogicVision
 unveils
 new
 paradigm
 of
 "Embedded

 Test"
 solutions
 from
 front-end
 design
through
 back-end
 manufacturing
 and
 ultimately
 in-field
 remote
 access
 and

 diagnostics.

Exhibitor Presentation Abstracts
Magma
 Design
 Automation,
 Inc. 9:40
Come
 see
 how
 Magma
 is
 melting
 logical
 and
 physical
 design
 with
 a
 single,
 unified
 RTL
 to
GDSII
 design
 system
 that
 eliminates
 iterations
 and
 guarantees
 timing.
Mathmatical
 Systems
 Inc. 5:20
THYME
 -a
 SPICE
 netlist
 reduction
 tool-
 enables
 you
 to
 analize
 a
 VLSI
 circuit
 impossible
until
 now.
Mentor
 Graphics
 Corp. 3:20
With
 Mentor
 Graphics
 high-performance
 tools,
 engineers
 can
 achieve
 designs
 that
 have
never
 been
 done
 before,
 turning
 extreme
 SoC
 and
 PCB
 system
 designs
 into
 real
 products.
Microcosm
 Technologies,
 Inc.
 9:20
Leading
 provider
 of
 software
 and
 engineering
 services
 for
 micro-electro-mechanical
 systems
 (MEMS)
development
f or
 automotive,
 telecommunications,
 bio-medical,
 industrial,
 and
 consumer
 systems.
Model
 Technology
 Inc. 9:40
Model
 Technology's
 ModelSim
 product
 line
 provides
 ASIC
 and
 FPGA
 designers
 with
 the
latest
 in
 HDL
 simulation
 technology
 regardless
 of
 the
 language.
Monterey
 Design
 Systems 4:40
Monterey
 Design
 Systems
 unveils
 innovative
 products
 and
 e-services
 as
 part
 of
 Dolphin,
 the
industry's
 only
c omplete
in tegrated
 physical
 design
 solution.
Mosis 3:40
MOSIS
 and
 partners
 present
 a
 complete
 design
 flow
 (digital,
 mixed-signal)
 for
prototyping
 production
 compatible
 designs
 at
 AMI,
 TSMC,
 etc.
MyCAD,
 Inc. 11:20
MyCAD
 provides
 complete
 solutions
 for
 IC
 design:
 IC
 Layout/Verification,
 VHDL,
Synthesis,
 FPGA
 Prototyper
 at
 affordable
 cost
 on
 PC
 platforms.
Nassda
 Corp. 9:20
Nassda’s
 HSIM
 performs
 full-chip
 circuit
 simulation
 and
 analysis
 for
 nanometer
 memory
and
 mixed-signal
 SOCs
 with
 SPICE
 accuracy
 and
 extremely
 high
 performance.
Neo
 Linear,
 Inc. 11:40
NeoCircuit
 and
 NeoCell
 automate
 custom
 analog
 cell
 synthesis
 and
 layout,
 while
capturing
 the
 design
 constraints
 necessary
 for
 mixed-signal
 IP
 reuse.
Nordic
 VLSI
 ASA 11:40
A
 highly
 skilled
 Fabless
 Foundry.

 Specialized
 in
 high
 speed
 A/D
 Converters
 and
 RF
transceivers
 for
 systems
 on
 chip
 integration.
Novas
 Software 5:00
Debussy ® Knowledge
 Based
 Debugging
 System--the
 complete,
 open
 debugging
 solution
for
 Verilog
 and
 VHDL
 designs--speeds
 IC
 and
 ASIC
 debugging.
Numerical
 Technologies,
 Inc. 3:20
See
 the
 Light!
 Numerical
 Technologies
 will
 present
 a
 solution
 that
 allows
 you
 to
 reliably
design
 and
 manufacture
 ICs
 with
 sub-0.2um
 features.
Nurlogic
 Design,
 inc. 3:40
NurLogic's
 complete
 set
 of
 Foundation
 IP
 includes
 process
 specific,
 silicon
 proven
Standard
 Cell
 Libraries,
 I/Os,
 Specialty
 I/Os,
 Memories,
 and
 Analog
 IP.
OEA
 International,
 Inc. 9:00
Providing
 design
 rule
 generation
 and
 high
 accuracy
 post-layout
 3-D
 field
 solutions
 for
chip
 level
 critical
 power,
 signal
 and
 clock
 nets.
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14
Exhibitor Presentation Abstracts
OptEM
 Engineering
 Inc. 3:40
OptEM
 presents
 interconnect
 analysis
 and
 device
 extraction
 tools
 for
 digital
 designers
concerned
 with
 inductive,
 frequency
 dependent
 and
 lossy
 transmission
 line
 effects.
PADS
 Software 4:20
HyperLynx,
 a
 division
 of
 PADS
 Software,
 supplies
 signal
 integrity
 solutions
 that
 will
quickly
 and
 accurately
 solve
 your
 SI,
 EMI
 and
 crosstalk
 issues.
Pivotal
Technologies 11:40
Pivotal
 Technologies
 provides
 deep
 sub-micron
 analog
 and
 mixed
 signal
 subsystems
 for
System-on-Chip
 Communications
 and
 Multimedia
 products.
Platform
 Computing
 Corp. 4:20
LSF
 Suite
 for
 Application
 Resouce
 Management,
 the
 industry-leading
 software
 solution
 that
delivers
 compelling
 business
 results
 by
 effectively
 managing
 enterprise
 computing
 workloads.
Prolific,
 Inc. 9:40
PROLIFIC's
 ProGenesis
 standard-cell
 layout
 tools

 produce
 custom-tailored
 libraries
 that
capture
 and
 reuse
 your
 design

 styles.
QThink 11:20
QThink
 IC
 Design
 Services.

 Find
 out
 why
 so
 many
 customers
 are
 coming
 to
 QThink
 for
 "pure
play"
 design
 services.
QuickLogic
 Corp. 2:00
QuickLogic’s
 new
 QuickDSP
 family
 of
 Embedded
 Standard
 Products
 combines
 the
 power
 of
DSP
 with
 the
 flexibility
 of
 programmable
 logic.
RouTech,
 Inc. 5:20
RouTech,
 Inc.
 has
 developed
 an
 advanced
 autorouter
 for
 PCB
 design,
 based
 on
breakthrough
 technology.

 Advantages
 are
 significant
 for
 high-speed
 designs.
RUBICAD
 Corp. 11:00
LADEE
 combines
 layout
 entry,
 compaction,
 extraction
 and
 verification
 functions
 to
address
 timing,
 cross-talk,
 power,
 and
 design-reuse
 problems
 in
 deep-submicron
 design.
Sagantec 10:00
Sagantec’s
 software
 ensures
 reuse
 and
 optimization
 of
 hard
 intellectual
 property––
designs
 represented
 as
 mask
 layouts
 ––
 to
 implement
 system
 on
 silicon.
Sente,
 Inc. 3:20
Sente,
 Inc.
 -
 leaders
 in
 RTL
 power
 analysis
 and
 reduction
 solutions
 -
 discusses
 issues
 and
trends
 in
 low
 power
 design
 methodologies
 for
 SOC
 designs.
SICAN
 Microelectronics
 Corp. 10:40
Do
 you
 want
 to
 shorten
 your
 design
 cycle,
 reduce
 risk
 and
 increase
 design
 performance
and
 complexity?
 Talk
 to
 Sican
 for
 IP
 and
 services!
Silicon
 Automation
 Systems
 Ltd. 11:40
SAS
p rovides
 design
 services
 in
 Design
 flows
 Optimization,
D esign
m ethodologies
O ptimization
and
C ustom
 tool
 development
 &
 integration,
 and
h ave
 developed
 various
E DA-IP
 blocks.
SiliconCraft
 Inc. 5:00
SiliconCraft
 introduces
 TimeCraft
 1.0,
 a
 fab-proven
 faster
 static
 timing

 analysis
solution
 for
 VDSM
 within
 3%
 of
 SPICE
 accuracy.
 (Come
 and
 let
 us

 show
 how
 it
 works.
 )
Silicon
 Forest
 Research,
 Inc. 11:20
Losing
 time
 because
 difficult
 bugs
 take
 days
 to
 track
 down?
 See
 how
 Assertion
Compiler
 speeds
 up
 RTL
 functional
 debugging
 by
 40%.

Exhibitor Presentation Abstracts
Silicon
 Graphics
 Computer
 Systems
 Inc. 4:20
Server
 Farm
 -
 hub
 of
 modern
 EDA
 solutions.
 Problem
 -
 rapidly
 evolving
 and
 expanding
design
 environment.
 Solution
 -
 Linux
 with
 SGI!
Silicon
 Integration
 Initiative,
 Inc. 5:40
Standards
 Specification
 Programs
 at
 Si2.
 Si2
 will
 discuss
 current
 status
 and
 future
direction
 of
 the
 ECIX,
 OLA/LEF,
 Design
 API,
 and
 SIPPs
 industry
 programs.
Silicon
 Valley
 Research,
 Inc. 4:40
Future
 of
 SVRI,
 and
 it’s
 advanced
 technology
 EDA
 tools,
 which
 provide
 dense,
 high
yielding,
 high
 performance
 chip
 designs,
 will
 be
 presented.
Silicon
 Value 5:00
A
 breakthrough
 full-custom
 design
 technology
 enables
 quick
 integration
 of
 complex
designs
 in
 the
 smallest-ever
 silicon
 areas
 in
 the
 ASIC
 industry.
Simplex
 Solutions,
 Inc. 5:00
Simplex
 presents
 Fire
 &
 Ice ® QX
 and
 VoltageStorm,
 solutions
 for
 UDSM
 verification
combining
 transistor-level
 accuracy
 with
 gate-level
 speed
 and
 ease-of-use.
Simpod,
 Inc. 4:40
Simpod’s
 patented
 hardware
 modeling
 technology
 interfaces
 to
 logic
 simulators
 and
software
 debuggers
 to
 speed
 design
 and
 verification
 of
 embedded
 systems.
Simucad,
 Inc. 5:40
SILOS
 III
 -
 FSM
 New
 capability
 allows
 user
 to
 graphically
 enter
 Finite
 State
 Machines
 and
view
 the
 state
 of
 each
 FSM
 during
 simulation.
Simutech,
 LLC 10:40
Simutech
 is
 focused
 on
 providing
 desktop
 IP
 and
 Internet
 based
 verification
 tools
 to
leading
 electronics
 systems,
 semiconductor,
 and
 IP
 companies.
Simutest,
 Inc. 11:00
Simutest
 presents
 an
 advanced
 Test
 Automation
 solution
 called
 Verifier.

 With
 Verifier
you
 can
 create
 &
 verify
 test
 programs
 offline
 and
 before
 silicon.
SliceX,
 Inc. 5:20
Analog
 IP
 provider,
 SliceX,
 will
 present
 a
 programmable
 phase-locked
 loop
 (PLL)
 for
 highspeed
clock
 synthesis.
Snaketech
 Corp. 10:00
Snaketech's
 substrate
 modeling
 and
 noise
 analysis
 software
 solves
 coupling
 problems
 in
RF,
 wireless,
 mixed-signal,
 and
 high-speed
 designs.
Sonics
 Inc. 2:00
Radically
 new
 SOC
 integration
 system
 that
 generates
 a
 highly
 configurable
 inter-core
communication
 network
 for
 complex
 and
 real-time
 data
 flows
Summus
 Design
 CO.,
 Ltd. 4:00
PowerEscort
 is
 the
 only
 solution
 of
 accurate
 hierarchical
 IR-drop
 and
 electromigration
analysis
 in
 multi-million
 gates
 SOC
 design
 within
 an
 hour.
Sycon
 Design,
 Inc. 5:40
Sycon
 presents
 a
 state-of-the-art
 automation
 tool-suite
 for
 high
 performance
 IC
physical
 design
 that
 produces
 results
 achieved
 only
 by
 manual
 design.
Synopsys,
 Inc. 3:00
Synopsys
 will
 showcase
 its
 technology-leading
 SoC
 design
 solution
 covering
 physical,
verification
 and
 implementation
 products
 and
 design
 flows.
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Exhibitor Presentation Abstracts
Synplicity,
 Inc. 9:20
Synplicity
 will
 showcase
 leading
 edge
 logic
 synthesis
 and

 verification
 products
 for
 FPGA
and
 ASIC

 designers.
SynTest
 Technologies,
 Inc. 2:00
The
 SynTest
 Exhibitor
 Presentation
 will
 describe
 existing
 and
 new
 products
 for
 DFT
 and
BIST
 applications
 for
 multi
 million
 gate
 SoC
 designs.
Target
 Compiler
 Technologies
 N.
 V. 2:20
Discover
 the
 latest
 extensions
 of
 Chess/Checkers,
 Target's
 retargetable
 compilation
environment.
 
 Find
 out
 how
 to
 design
 and
 program
 an
 application-specific
 DSP
 in
 only
 days
 of
 time.
Tensilica,
 Inc. 10:00
Xtensa
 is
 a
 configurable,
 extensible
 microprocessor
 architecture
 designed
 for
 high
volume,
 system-on-chip
 applications.
 A
 complete
 software
 development
 tool
 suite
 is
automatically
 configured
 with
 the
 processor.
Tera
 Systems
 Inc. 2:00
Discover
 how
 the
 TeraForm
 RTL
 design
 planner
 enables
 interactive
 front-end
 design,
 RTL
signoff,
 and
 back-end
 timing
 convergence
 for
 high-performance
 ASICs.
Texas
 Instruments
 Inc. 3:00
SLI
 -
 It's
 time,
 it's
 real
 and
 it's
 scary!

 The
 changing
 model
 of
 SLI
 and
 its
 impact
 on
 the
industry.
Tharas
 Systems
 Inc. 9:00
Want
 fast
 RTL
 simulation?
 Tharas
 Systems
 new
 acceleration
 product

 sets
 the
 standard
 for
ease
 of
 use,
 compile
 times
 and
 price/performance.
TransEDA,
 Inc. 3:40
Highlighting
 Verification
 Navigator,
 an
 integrated
 design
 verification
 solution
 for
 Verilog,
VHDL
 and
 mixed-language
 designs,
 and
 State
 Navigator,
 a
 finite
 state
 machine
 debug
 and
verification
environment.
Triscend
 Corp. 10:20
Triscend
is 
th e
le ader
in
C onfigurable
Sy stem-on-Chip--a
c ombination
of 
ind ustry-standard
microprocessors,
 embedded
 programmable
 logic,
 bus,
 memory,
 and
 other
 system
 features.
Ultima
 Interconnect
 Technology 10:40
Ultima
 provides
 focused
 design
 solutions
 for
 timing
 closure
 in
 0.25u
 and
 below
 designs
including
 coupling,
 IR-drop,
 clock
 skew
 and
 other
 interconnect
 effects.
United
 Microelectronics
 Corp.
 Group 4:00
UMC
 will
 be
 presenting
 ,
 "Taking
 advantage
 of
 world
 class
 foundry
 technology,
 IP
 and
services
 for
 your
 leading
 edge
 SOC
 designs."
Validity
 Design
 Automation,
 Inc. 10:20
Validity
 offers
 industry’s
 first
 truly
 scalable
 functional
 validation
 product
 suite
 that
automatically
 derives
 complex
 functional
 checks
 from
 the
 RTL
 and
 formally
 verifies
 them.
VaST
 Systems
 Technology
 Corp. 2:00
VaST’s
 systems
 engineering
 product
 CoMET
 is
 a
 specification,
 modelling
 and
 design
 environment
for
s ystems
 incorporating
 electronic
 hardware,
s oftware
a nd
 mechanical
 subsystems.
Verisity
 Design,
 Inc. 10:40
Functional
 verification
 automation
 to
 verify
 your
 most
 complex
 designs
 faster
 and
 more
efficiently
 than
 ever
 before.
 Verification
 in
 Motion.

Exhibitor Presentation Abstracts
Verplex
 Systems,
 Inc. 10:00
Verplex
 formal
 verification
 tools
 are
 superior
 in
 speed,
 capacity
 and
 usability.
 They
reliably
 handle
 the
 toughest
 full
 chip
 designs,
 RTL-netlist.
Viewlogic
 Systems
 &
 Summit
 Design 9:00
Innovative
 EDA
 tools
 and
 services
 for
 system
 level
 design,
 design
 capture,
 and
 board
design.
 Visualize
 it.
 Design
 it.
 Build
 it.
Virage
 Logic
 Corp. 10:20
Virage
 Logic
 will
 present
 its
 Embedded
 Memory
 Initiative
 for
 SoC
 designs
 with
 its
 broad
portfolio
 of
 embedded
 memory
 products.
Xilinx,
 Inc. 11:00
The
 Xilinx
 vision
 of
 Internet
 enabled
 software
 and
 upgradeable
 systems
 integrated
 with
ultra
 high
 density
 FPGAs
 and
 low
 power
 CPLDs
 will
 be
 presented
 by
 Rich
 Sevcik.
Xpedion
 Design
 Systems,
 Inc. 4:20
The
 Xpedion
 GoldenGate
 family
 delivers
 a
 new
 breed
 of
 RF/Microwave
 simulation
 and
modeling
 solutions
 for
 designing
 wireless
 communication
 circuits
 and
 systems.
Y
 Explorations,
 Inc. 5:20
YXI
 delivers
 tools
 for
 capturing,
 databasing,
 distributing
 and
 automatically
 synthesizing
interfaces
 between
 IPs
 into
 multiple
 alternative
 synthesizable
 RTL
 SoC
 netlists.
Zuken-Redac,
 Inc. 2:20
Design
 Innovation?
 ...Find
 out
 how
 to
 turn
 your
 ideas
 into
 real
 products
 with
 Zuken's
Technology-First
 solutions
 for
 electronic
 product
 design.
e
x
h
i
b
i
t
o
r
p
r
e
s
e
n
t
a
t
i
o
n
s
17

18
Workshop for Women in Design Automation
Strategies for Success - Sunday, June 4
This
 year’s
 workshop
 for
 women
 explores
 the
 topic
 of
 success.
 In
 our
 diverse
 world,
 each
 of
 us
defines
 personal
 success
 differently.
 You’ll
 hear
 from
 some
 of
 the
 industry’s
 most
 accomplished
women
 on
 how
 they
 define
 success
 and
 what
 they
 did
 to
 achieve
 it.
 In
 the
 afternoon
 workshop
 you’ll
identify
 what
 success
 means
 to
 you
 and
 learn
 to
 remove
 barriers
 to
 attaining
 your
 greatest
fulfillment.
 Join
 us
 on
 Sunday,
 June
 4th
 to
 identify
 your
 very
 own
 strategy
 for
 success.
WORKSHOP
 CHAIR: Karen
 Bartleson,
 Director
 of
 Interoperability,
 Synopsys,
 Inc.
ORGANIZERS: Kathryn
 Kranen -
 President
 and
 CEO,
 NVB
Pamela
 Parrish –
 Executive
 Director,
 EDA
 Consortium
Troy
 Wood –
 Marcom
 Program
 Manager,
 Synopsys,
 Inc.
STEERING
 COMMITTEE: Kathryn
 Kranen -
 President
 and
 CEO,
 NVB
Marie
 R.
 Pistilli –
 President,
 MP
 Associates,
 Inc.
Ellen
 Yoffa –
 DAC
 EC
 Representative
Schedule
8:00
 am ........Registration
 and
 Continental
 Breakfast
9:00
 am ........Welcome/Opening
Remarks – Karen
 Bartleson
9:15
 am ........Keynote
Larraine
 D.
 Segil,
 CEO,
 Lared
 Presentations
Larraine
 is
 highly
 recognized
 in
 the
 areas
 of
 strategic
 alliances,
global
 strategy,
 and
 competency.
 
 She'll
 reveal
 her
 definition
 of
success,
 how
 she
 achieved
 it,
 what
 obstacles
 she
 overcame,
 and
her
 future
 goals.
 Her
 stimulating
 portrayal,
 based
 on
 experience
as
 an
 entrepreneur,
 CEO,
 attorney,
 and
 international
 consultant,
will
in spire
yo u
to 
f ind
 your
 own
 avenue
o f
 success.
10:00
 am ......Break
10:20
 am ......Panel:
 The
 Contrasts
 of
 Success Moderator:
 Karen
 Bartleson
These
 accomplished
 panelists
 will
 convey
 their
 unique
 perspectives
 on
 success,
 presenting
 a
variety
 of
 descriptions
 of
 personal
 achievement.
 They
 will
 share
 their
 strategies
 and
 provide
insights
 that
w ill
 encourage
 audience
m embers
 to
 explore
 their
o wn
s uccess
 goals.
Susan
 Cain -
 Cain
 Communications Karla
 Reynolds -
 IBM
 Corp.
Nancy
 Nettleton -
 Sun
 Microsystems Jennifer
 Smith -
 Dain
 Rauscher
 Wessels
Judy
 Owen -
 SiliconX Carole
 Thurman -
 Mentor
 Graphics
 Corp.
12:00
 pm ......Lunch (provided)
 –
 A
 great
 opportunity
 to
 network.
1:00
 pm ........Interactive
Workshop: Defining
 Your
 Strategy
 for
 Success
Leader:
 Laurie
 Lippin -
 New
 Insights
 Consulting
What
 is
 your
 unique
 definition
 of
 success?
 Have
 you
 explored
 what
 success
 means
 to
 you
 and
 how
you
 can
 achieve
 it?
 Are
 you
 satisfied
 that
 you
 are
 successful
 in
 your
 own
 right?
 Using
 a
 fun,
interactive
 tool
 you
 will: -
 Define
 what
 success
 means
 to
 you
-
 Identify
 the
 obstacles
 to
 your
 success
-
 Determine
 how
 to
 achieve
 your
 personal
 success
 goals
2:20
 pm ........Break
2:40
 pm ........Interactive
Workshop - Defining
 Your
 Strategy
 for
 Success
 (Continued)
3:40
 pm ........Award
 Ceremony – Karen
 Bartleson
Join
 us
 as
 we
 honor
 the
 inaugural
 recipient
 of
 the
 Women
 in
 EDA
 Achievement
 Award
 for
contributions
 that
 advance
 women
 in
 the
 field
 of
 EDA
 technology.
4:00
 pm 
.
.
.
.Reception: Sponsored
 by
 the
 EDA
 Consortium

Workshop for VLSI Design Educators
Sunday, June 4
The
 Workshop
 for
 VLSI
 Design
 Educators
 is
 a
 new
 highlight
 of
 DAC.
 This
 program
 affords
 a
 unique
forum
 for
 VLSI
 educators,
 design
 tool
 vendors
 and
 textbook
 authors
 to
 interact,
 share
 their
thoughts
 and
 improve
 the
 instruction
 of
 VLSI
 Design
 courses.
 It
 will
 expose
 the
 educators
 to
 new
course
 material
 and
 design
 tools
 in
 order
 to
 help
 them
 prepare
 future
 VLSI
 design
 engineers
 to
better
 meet
 the
 challenges
 of
 recent
 changes
 in
 the
 design
 automation
 industry.
ORGANIZERS: Vijaykrishnan
Narayanan -

 Penn
 State
 Univ.
Mary
 Jane
 Irwin -
 Penn
 State
 Univ.
Steven
 P.
 Levitan -
 Univ.
 of
 Pittsburgh
Schedule
8:15am ........Breakfast
8:45am ........Welcome
Address: Vijaykrishnan
Narayanan
9:00am ........Jan
Rabaey -
 University
 of
 California,
 Berkeley,
 will
 speak
 on
 teaching
 a
VLSI
 Design
 course
 based
 on
 the
 "Digital
 Integrated
 Circuits:
 A
 Design
Perspective"
textbook.
9:30am ........Wayne
Wolf -
 Princeton
 University,
 will
 share
 his
 experience
 on
 teaching
VLSI
 design
 using
 the
 "Modern
 VLSI
 Design
 :
 Systems
 on
 Silicon"
 textbook.
10:00am ........Cherrice
Traver -
 Union
 College,
 will
 present
 a
 lecture
 demonstration
 on
using
 PC
 based
 VLSI
 design
 tools.
11:00am ........Lee
Travow -
 MicroMagic
 Inc.,
 will
 present
 a
 lecture
 demonstration
 using
UNIX/LINUX
 based
 VLSI
 design
 tools.
12:00 ........Lunch
1:00 ........Hands-on
Workshop. This
 will
 provide
 a
 hands-on-experience
 on
 using
 the
MicroMagic
 Design
 Toolset.
 Instructors
 who
 have
 used
 these
 tools
 at
 various
universities
 will
 assist
 with
 this
 session.
4:00pm ........Concluding
Remarks: Mary
 Jane
 Irwin
19

20
Interoperability Workshop
Sunday, June 4
Interoperability
 among
 EDA
 tools
 has
 been
 a
 topic
 of
 passionate
 discussion
 for
 a
 long
 time
 and
many
 standard
 file
 formats
 have
 been
 proposed
 to
 help.
 But
 the
 rapid
 advance
 in
 semiconductor
technology
 combined
 with
 the
 need
 for
 more
 predictable
 and
 productive
 automated
 design
methodologies
 are
 demanding
 a
 much
 tighter
 integration
 of
 new
 EDA
 tools.

 Many
 people
 believe
that
 for
 EDA
 to
 keep
 pace
 with
 semiconductor
 technology,
 new
 more
 modular
 applications
 will
need
 to
 operate
 on
 shared
 design
 data
 in
 memory.
 Several
 EDA
 companies
 have
 announced
 design
systems
 with
 suites
 of
 tools
 tightly
 integrated
 around
 their
 proprietary
 data
 models.

 But
 to
 be
able
 to
 assemble
 such
 systems
 with
 the
 best
 components
 from
 multiple
 suppliers,
 we
will
 need
 a
 standard
a pplication
 programming
 interface
f or
 data
 access
a nd
 control.
This
 Workshop
 invites
 representatives
 from
 the
 leading
 Semiconductor,
 System
and
 EDA
 companies
 to
 discuss
 the
 need
 for
 such
 a
 new
 design
 system
 architecture
and
 supporting
 standard
 data
 model
 API.

 It
 will
 also
 address
 the
 specific
changes
 needed
 to
 enable
 such
 a
 standard
 and
 formulate
 an
 initial
 action
 plan.
Schedule
1:00pm ........Lunch
CHAIR: John
 Darringer -

 EDA
 Strategy,
 IBM
 Corp.
1:00pm ........Welcome
 and
 Workshop
 Objectives : John
 Darringer
1:15pm ........Session
1 - Do
 we
n eed
 a
S tandard
 Data
M odel
 API?
W hat
a re
 the
R equirements?
2:15pm ........Break
Terry
 Blanchard -
 Mgr.
 VLSI
 Technology
 Center,
 Hewlett
 Packard
 Co.
Thomas
 Daniel -
 VP
 ASIC
 Technology,
 LSI
 Logic
Sumit
 Dasgupta -
 Mgr.
 Tools
 and
 Methodology,
 Motorola,
 Inc.
Jennifer
 Howland -
 Dir.
 EDA,
 IBM
 Corp.
Jan-Olof
 Kismalm -
 Dir.
 Microelectronics
 Coordination,
 Ericsson
Mark
 McDermott -
 Dir.
 Texas
 Development
 Center,
 Intel
 Corp.
2:30pm ........Session
2 -
 What
 is
 required
 to
 achieve
 a
 Standard
 API?
3:30pm ........Break
Bill
 Alexander -
 Corporate
 Product
 Management,
 Avant!
 Corp.
Dinesh
 Bettadapur -
 VP
 Business
 Development,
 Monterey
 Design
Raul
 Camposano -
 VP
 R&D,
 Synopsys,
 Inc.
Jim
 Hogan -
 Sr.
 VP
 IC
 Implementation,
 Cadence
 Design
 Systems,
 Inc.
Joe
 Hutt -
 VP
 R&D,
 Magma
 Design
 Automation
Kent
 Moffat -
 Group
 Mgr.
 Solutions
 Partnerships,
 Mentor
 Graphics
 Corp.
3:45pm ........Session
3 -
 What
 is
 the
 Action
 Plan
 for
 2000?
Panel
 Chair: Richard
 Goering -
 Editor
 EE
 Times
Panel
 members
 to
 be
 selected
 from
 workshop
 speakers
 and
 audience
4:45pm ........Wrap-up - John
 Darringer
5:00pm ........Adjourn

Student Design Contest
This
 year
 we
 have
 changed
 the
 format
 of
 our
 design
 contest.
 The
 new
 format
 is
 a
 blend
 of
 the
previous
 DAC
 University
 Design
 Contest
 and
 the
 Student
 VLSI
 Design
 Contest
 organized
 out
 of
 the
University
 of
 Utah
 and
 University
 of
 Michigan.
The
 purpose
 of
 the
 new
 Student
 Design
 Contest
 is
 to
 promote
 excellence
 in
 the
 design
 of
electronic
 systems
 by
 providing
 competition
 between
 graduate
 and
 undergraduate
 students
 at
universities
 and
 colleges.
 This
 year
 we
 received
 submissions
 in
 two
 categories:
 'Conceptual'
 and
'Operational.'
 Operational
 designs
 are
 those
 which
 have
 been
 implemented
 and
 tested.
 
 Conceptual
designs
ha ve
 not
 yet
 been
 fabricated
 and
 tested
 but
 must
 have
be en
 thoroughly
si mulated.
Students
 compete
 for
 cash
 prizes
 donated
 by
 a
 number
 of
 industrial
 sponsors
 and
 by
 DAC
 itself.
This
 year
 the
 total
 prize
 money
 is
 $19,500.
 Prizes
 will
 be
 awarded
 at
 a
 special
 luncheon
 during
 the
conference.
 Prize
 winners
 will
 be
 listed
 in
 the
 final
 program
 and
 have
 been
 invited
 to
 show
 their
work
 at
 the
 SIGDA/University
 Booth
 on
 the
 show
 floor.
 In
 addition,
 three
 of
 the
 submissions
 have
been
 included
 in
 this
 year's
 technical
 program
 (see
 pages
 33,
 40,
 47).
A
C
M
/
S
I
G
D
A Ph.D Forum
ACM/SIGDA
 will
 hold
 a
 semi-annual
 meeting
 after
 the
 cocktail
 party
 on
 Tuesday
 evening,
 June
 6,
from
 7:00PM
 to
 9:00PM.

 A
 light
 dinner
 will
 be
 served.

 The
 primary
 focus
 of
 the
 meeting
 will
 be
the
 third
 annual
 Ph.D.
 Forum.

 The
 meeting
 is
 open
 to
 all
 members
 of
 the
 DA
 community.
The
 Ph.D.
 Forum,
 hosted
 by
 SIGDA,
 aims
 to
 strengthen
 the
 ties
 between
 academic
 research
 and
industry.
 During
 the
 SIGDA
 meeting,
 students
 will
 use
 posters
 to
 discuss
 their
 Ph.D.
 thesis
 work
with
 interested
 attendees.

 This
 session
 will
 provide
 the
 students
 an
 opportunity
 to
 receive
feedback
 on
 their
 work.
 It
 also
 previews
 academic
 work-in-progress
 to
the
 DA
 community.
 For
 more
 information
 about
 the
 Forum,
 please
 visit
http://www.sigda.acm.org/Programs/PHDForum.
 SIGDA
 members
 and
 non-members
 are
 invited.
Birds-of-a-Feather (
B
O
F
) Meetings
DAC
 will
 provide
 conference
 rooms
 for
 informal
 groups
 to
 discuss
 items
 of
 common
 technical
interest.
 These
 very
 informal
 non-commercial
 meetings,
 held
 after
 hours,
 are
 referred
 to
 as
“Birds-of-a-Feather”.
 All
 BOF
 meetings
 are
 held
 at
 the
 Westin
 Bonaventure,
 Wednesday,
 June
 7,
6:00PM
 -
 7:30PM.
 DAC
 will
f acilitate
c ommon
 interest
gr oup
 meetings
to 
 discuss
D A
re lated
 topics.
To
 arrange
 a
 BOF
 meeting
 contact
 the
 DAC office
 at
 1-800-321-4573
 or
 sign
 up
 at the
 Information
Desk
 at-conference.
 A
 room
 will
 only
 be
 assigned
 if
 ten
 or
 more
 people
 sign
 up.
 A
 viewgraph
projector
 and
 screen
 will
 be
pr ovided
on 
 request.
 Check
 DACnet
 and
 the
Bi rds-of-a-Feather
 board
at
 the
 Information
 Desk.
21

22
Tuesday Keynote
First-Time-Right Si but to the Right Specification
Theo
 A.C.M.
 Claasen
Executive
 Vice
 President
Chief
 Technology
 Officer
Philips
Semiconductors
Eindhoven,
 The
 Netherlands
With
 the
 increasing
 complexity
 of
 today’s
 (and
 certainly
 tomorrow’s)
 integrated
 systems,
 the
real
 design
 challenge
 has
 shifted
 from
 making
 first-time-right
 silicon
 to
 making
 a
 first-timeright
specification
 and,
 of
 course,
 the
 associated
 chip
 that
 implements
 this
 specification
correctly.
 Many
 of
 today’s
 systems
 on
 a
 chip
 contain
 embedded
 CPU
 and
 /
 or
 DSP
 cores
 and
have
 a
 large
 amount
 of
 software
 that
 determines
 the
 function
 of
 the
 chip.
 To
 know
 that
 all
the
 system
 functions
 are
 specified
 and
 implemented
 correctly
 often
 requires
 hours
 of
exposure
 to
 real
 data
 in
 a
 real
 user
 environment.
 This
 can
 not,
 to
 any
 reasonable
approximation,
 be
 done
 by
 means
 of
 simulation.
 For
 that
 reason
 fine-tuning
 of
 the
 system
spec
 can
 usually
 only
 be
 done
 if
 an
 initial
 silicon-version
 of
 the
 system
 has
 become
 available.
It
 will
 be
 shown
 how
 the
 combination
 of
 Silicon
 Systems
 Platforms
 and
 the
 VLSI-Velocity
 Rapid
Silicon
 Prototyping
 can
 give
 a
 solution
 to
 this
 dilemma.
Dr.
 Theo
 Claasen
 assumed
 the
 function
 of
 Chief
 Technology
 Officer
 of
 Philips
 Semiconductors,
in
 1997
 after
 a
 long
 career
 in
 the
 Corporate
 Philips
 Research
 Labs.
 In
 this
 function
 he
 has
the
 responsibility
 for
 the
 shared
 technical
 resources
 of
 the
 division
 that
 develop
 (or
 acquire)
the
 full
 range
 of
 technologies
 needed
 in
 the
 business
 units
 (process
 technology,
 libraries,
CAD,
 IP
 cores,
 software
 and
 system
 architectures
 and
 applications).
 In
 this
 role
 he
 has
particularly
 promoted
 the
 concept
 of
 Silicon
 Systems
 Platforms,
 now
 available
 under
 the
Nexperia
 brand
 name.
 With
 the
 acquisition
 of
 VLSI
 by
 Philips
 Semiconductors
 Rapid
 Silicon
Prototyping
 has
 been
 added
 as
 a
 solution
 to
 the
 rapid
 design
 of
 Systems
 on
 Silicon.
 Dr.
Claasen
 is
 a
 Fellow
 of
 the
 IEEE
 for
 contributions
 to
 the
 theory
 of
 Digital
 Signal
Processing.

Thursday Keynote
System Design Challenges in the Post-PC Era
Hugo
 De
 Man
Professor
Katholieke
 Univ.
Leuven,
 Belgium
Progress
 of
 microelectronics,
 DSP,
 integrated
 sensors
 and
 RF
 CMOS
 causes
 a
 paradigm
shift
 in
 the
 ICT
 world
 referred
 to
 as
 the
 "post-PC"
 era
 when
 wearable
 computing
augments
 our
 consciousness,
 protects
 our
 health
 and
 globally
 connects
 people
 and
things.
 Designing
 such
 systems
 differs
 radically
 from
 designing
 CPU
 architectures.
 The
art
 will
 be
 to
 design
 a
 diversity
 of
 cheap,

 energy
 efficient,
 yet
 programmable
platforms
 that
 can
 be
 configured
 over
 the
 Internet
 and
 communicate
 with
 humans
through
 non-keyboard
 interfaces.
 It
 requires
 a
 grand
 convergence
 of
 previously
separated
 domains
 such
 as
 programmable/reconfigurable
 multi-processor
 architectures
with
 embedded
 software,
 broadband
 radio,
 MEMS
 and
 biosensor
 interfaces.
 We'll
discuss
 challenges
 to
 design
 technology
 and
 to
 the
 skills
 of
 future
 system
 engineers
 as
well
 as
 to
 their
 education.
Hugo
 De
 Man
 is
 professor
 in
 electrical
 engineering
 at
 the
 Katholieke
 Universiteit
 Leuven,
Belgium
 since
 1976.
 He
 was
 visiting
 associate
 professor
 at
 U.C.Berkeley
 in
 1975.
 His
early
 research
 was
 devoted
 to
 mixed-signal,
 switched
 capacitor
 and
 DSP
 simulation
tools.
 In
 1984
 he
 was
 one
 of
 the
 cofounders
 of
 IMEC,
 which,
 today,
 is
 the
 largest
independent
 semiconductor
 research
 institute
 in
 Europe
 with
 over
 800
 employees.
 From
1984-1995
 he
 was
 Vice-President
 of
 IMEC,
 responsible
 for
 research
 in
 design
 technology
for
 DSP
 and
 telecom
 applications.
 In
 1995
 he
 became
 a
 senior
 research
 fellow
 of
 IMEC,
working
 on
str ategies
 for
 education
and
res earch
 on
 design
 of
 future
 post-PC
sys tems.
His
 research
 at
 IMEC
 has
 lead
 to
 many
 novel
 tools
 and
 methods
 in
 the
 area
 of
 high
 level
synthesis,
 hardware-software
 codesign
 and
 C++
 based
 design.
 Many
 of
 these
 tools
 are
now
 commercialized
 by
 spin-off
 companies
 like
 Coware,
 Frontier
 Design
 and
 Target
Compilers.
His
 work
 and
tea ching
 also
re sulted
 in
 a
 cluster
 of
 DSP
 oriented
 companies
i n
Leuven
 now
 known
 as
 DSP
 Valley
 where
 more
 than
 1100
 DSP
 engineers
 work
 on
 design
tools
 and
 on
 telecom,
 networking
 and
 multimedia
 integrated
 system
 products.
 In
 1999
he
 received
 the
 Technical
 Achievement
 Award
 of
 the
 IEEE
 Signal
 Processing
 Society,
 The
Phil
 Kaufman
 Award
 of
 the
 EDA
 Consortium
 and
 the
 Golden
 Jubilee
 Medal
 of
 the
 IEEE
Circuits
 and
 Systems
 Society.
 
 Hugo
 De
 Man
 is
 an
 IEEE
 Fellow
 and
 a
 member
 of
 the
 Royal
Academy
 of
 Sciences
 in
 Belgium.
23

conference
at
 a
 glance
24
9:00
to
10:15
10:30
to
12:00
2:00
to
4:00
4:30
to
6:00
6:00
to
7:00
Tuesday, June 6
New
 Techniques
for
 Synthesis
and
 Mapping
General
 Session
 and
 Keynote
 Speaker
(no
 badge
 is
 required)


 Room: Concourse
 Hall
First-Time-Right
 Si
 but
 to
 the
 Right
 Specification
Theo
 Claasen -
 Chief
 Technical
 Officer
Philips
 Semiconductors,
 Eindhoven,
 The
 Netherlands
Opening
 Remarks
 •
 Awards
 •
 Keynote
 Address
Formal
Verification
BREAK
Room
 404AB Room
 408A Room
 406AB Room
 408B Room
 403
Session
 1 Session
 2 Session
 3 Session
 4
Analog
 and
 RF BDD-Based
Model
 Checking
LUNCH
 12:00
 -
 2:00
Session
 6 Session
 7 Session
 8 Session
 9 Session
 10
Algorithms
 for
RF
 Simulation
and
 Model
Reduction
Verification
 and
Debugging
Methodologies
Test
Generation
 and
Diagnosis
Test
 Issues
f or
D
e
e
p
-
S
u
b
m
i
c
r
o
n
S
y
s
t
e
m
-
o
n
-Chips
2
 Embedded
Tutorials
BREAK
Design
 Methods
for
 Emerging
Technologies
Interconnect
Modeling
Clock
 and
Po wer
Grid
 Analysis
for
 High
Performance
Designs
Exhibit
 Hours
 10:00AM – 6
:
0
0P
M /
 Demo
 Suite
 Hours
 8:00AM – 9
:
0
0P
M
Session
 5
Life
 at
 the
 End
of
 CMOS Scaling
(And
 Beyond)
P
a
n
e
l:
D esign
Closure:
H ope
or
H ype
Session
 11 Session
 12 Session
 13 Session
 14 Session
 15
Signal
 Integrity
P
a
n
e
l:
E DA
Meets
 .Com:
H ow
E-Services
wi ll
Change
t he
ED A
Business
M odel
DAC
 Cocktail
 Party
 at
 the
 Los
 Angeles
 Convention
 Center
6:00PM -
 7:00PM
 on
 the
 Galaxy
 Patio
All
 Design
M ethods
S essions
a re
 shaded
 blue,
 Embedded
 Systems
S essions
 are
s haded
 grey.

8:30
to
10:00
10:30
to
12:00
2:00
to
4:00
4:30
to
6:00
Timing
 Analysis
and
Verification
Logic/Physical
Co-Design
Wednesday, June 7
Room
 404AB Room
 408A Room
 406AB Room
 408B Room
 403
Session
 16 Session
 17 Session
 18 Session
 19 Session
 20
New
 Techniques
in
 Power
Estimation
 and
Performance
Improvement
Power
 Analysis
and
O ptimization
for
 Embedded
Software
BREAK
Plenary
 Panel
Embedded
 Systems
 CEO
 Panel:
Embedded
Compilation
Techniques
Embedded
 Systems
 Design
 in
 the
 New
 Millennium
Combined
Global
 Routing,
Buffering
 and
Wiresizing
Room:
 Concourse
 Hall
LUNCH
 12:00
 -
 2:00
Advances
 in
System
Modeling
 and
Synthesis
Designing
Systems
 on
 a
Chip
37th
 Dac
 Party 7:00PM -
 10:00PM at
 the
 Westin
 Bonaventure
P
a
n
e
l:
Fu ture
S
y
s
t
e
m
s
-
o
n
-
Chip:
S oftware
or
H ardware
D
e
s
i
g
n
?
Session
 21 Session
 22 Session
 23 Session
 24 Session
 25
P
a
n
e
l:
 The
Future
 of
System
D esign
L
a
n
g
u
a
g
e
s
Session
 26 Session
 27
BREAK
Session
 28 Session
 29 Session
 30
Mixed
 Signal
Design
 and
Analysis
Floorplanning
 &
Placement
System
 Level
Scheduling
Architectures
for
 Embedded
Systems
Exhibit
 Hours
 10:00AM – 6
:
0
0P
M /
 Demo
 Suite
 Hours
 8:00AM – 9
:
0
0P
M
Panel:
Embedded
Systems
Education
All
D esign
Me thods
 Sessions
a re
 shaded
 blue,
E mbedded
 Systems
S essions
 are
s haded
 grey.
conference
at
 a
 glance
25

conference
at
 a
 glance
26
8:30
to
10:00
10:30
to
12:00
2:00
to
4:00
4:30
to
6:00
Thursday, June 8
Room
 404AB Room
 408A Room
 406AB Room
 408B Room
 403
Session
 31 Session
 32 Session
 33 Session
 34 Session
 35
Interconnect
Analysis
Intellectual
Property
Protection
 &
Re-use
High
 Level
Synthesis
 for
DSPs:
 Data
Intensive
Applications
Correctness
Issues
 in
 High
Level
 Synthesis
Embedded
Tutorial:
MOSFET
Modeling
 and
Circuit
 Design:
Re-Establishing
 a
Lost
 Connection
BREAK
SoC
 Test
Methodologies
and
 Defect
Modelling
Reconfigurable
Computing
Systems
Embedded
Tutorial:Bridging
the
 Gap
 Between
Full
 Custom
 and
ASIC
 Design
Panel:
Survival
Strategies
 for
Mixed-Signal
Systems-On-
Chip
Session
 36 Session
 37 Session
 38 Session
 39 Session
 40
Layout
Optimization
Decision
Procedures
 for
CAD
 Problems
New
F rameworks
for
 the
E DA
 Field
P
a
n
e
l:
 Web-Based
Frameworks
 to
Enable
 CAD
 R&D
High
Performance
Microprocessor
Design
Panel:
Case
Studies:
 Chip
Design
 on
 the
Bleeding
 Edge
Session
 41 Session
 42 Session
 43 Session
 44 Session
 45
Large-Scale
Parasitic
Analysis
KEYNOTE

 1:00
 -
 1:45

 (Lunch
 Not
 Included)

 Room: Concourse
 Hall
System
 Design
 Challenges
 in
 the
 Post-PC
 Era
Hugo
 De
 Man - Professor,
 Katholieke
 Univ.,
 Leuven,
 Belgium
Advances
 in
High
 Level
Synthesis
BREAK
Session
 46 Session
 47 Session
 48 Session
 49
Fault
Simulation
 and
Extraction
 of
Low-Level
Effects
Low
 Power
Design
Techniques
 and
Estimation
Demo
 Suite
 Hours
 8:00AM – 5
:
0
0P
M
Panel:
When
Bad
 Things
Happen
 to
 Good
Chips
Session
 50
Panel:
Emerging
Companies:
Acquiring
 Minds
Want
 to
 Know
All
D esign
Me thods
 Sessions
a re
 shaded
b lue,
E mbedded
 Systems
S essions
a re
s haded
 grey.

Opening Session - Tuesday, June 6
Opening Remarks
Giovanni
 DeMicheli -
 General
 Chair,
 37th
 DAC
Awards presented by:
STEVEN
 P.
 LEVITAN MICHAEL
 LIGHTNER
ACM/SIGDA REPRESENTATIVE IEEE/CAS
REPRESENTATIVE
ASCEE Undergraduate Scholarships
Opening keynote address
Theo
 Classen
Chief
 Technical
 Officer
Philips
Semiconductor
Awards/Scholarships
Scholarships
 will
 be
 awarded
 to
 four
 high
 school
 students
 who
 will
 be
 pursuing
 a
 degree
 in
Electrical
 Engineering
 or
 Computer
 Science
 from
 under-represented
 minorities.
Graduate Scholarships
Scholarships
 will
 be
 awarded
 to
 four
 graduate
 students
 to
 support
 research
 in
 Design
Automation.
Student Design Contest Award
Award
 will
 be
 presented
 to
 the
 school
 sponsoring
 the
 best
 entry
 to
 the
 contest.
Best Paper Awards
Best
 Paper
 Awards
 will
 be
 given
 in
 the
 following
 areas:
1.
 Design
 Synthesis,
 Test
 and
 Validation
2.
 Analog/RF/Electrical
 Modeling
 and
 Simulation
3.
 Design
 Methodology
 (2)
4.
 Embedded
 Systems
Individual Awards
2000
 IEEE Fellows
ACM/SIGDA
 Outstanding
 Ph.D
 Dissertation
 Award
 in
 Electrical
 Design
 Automation
ACM/SIGDA
 Distinguished
 Service
 Award
27

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All
 speakers
 are
denoted
 in
 Bold
28
S
 -
 denotes
short
 paper
Tuesday, June 6
Session 1
ROOM:
 404AB
ANALOG
 AND
 RF
CHAIR: Joel
 R.
 Phillips -
 Cadence
 Design
 Systems,
Inc.
 San
 Jose,
 CA
ORGANIZERS: Hidetoshi
 Onodera,
 Joel
 Phillips
This session surveys progress in synthesis,
symbolic analysis, and statistical analysis of analog
circuits.
1.1 A
 Case
 Study
 of
 Synthesis
 for
Industrial
 Scale
 Analog
 IP:

 Redesign
 of
 the
Equalizer/Filter
 Frontend
 for
 an
 ADSL
 Codec
Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard
Carley - Carnegie Mellon Univ., Pittsburgh, PA
James R. Hellums - Texas Instruments, Dallas, TX
1.2S Optimal
 RF
 Design
 Using
 Smart
Evolutionary
Hardware
Peter Vancorenland, Carl Deranter, Michiel Steyaert -
Katholieke Univ., Leuven, Belgium
1.3S Cyclone:
 Automated
 Design
 and
 Layout
of
 RF
 LC-Oscillators
Carl De Ranter, Bram De Muer, Geert van der Plas, Peter
Vancorenland - Katholieke Univ., Leuven, Belgium
Michiel Steyaert, Georges Gielen, Willy Sansen - Katholieke
Univ., Leuven, Belgium
1.4S An
 Asymptotically
 Constant,
 Linearly
Bounded
 Methodology
 for
 the
 Statistical
Simulation
 of
 Analog
 Circuits
 Including
Component
 Mismatch
 Effects
Carlo Guardiani, Sharad Saxena, Patrick McNamara, Philip
Schumaker, Dale Coder- PDF Solutions, San Jose, CA
1.5S Multi-Terminal
 Determinant
 Decision
Diagram:
 A
 New
 Approach
 to
Symbolic/Numeric
 Analysis
 of
 Large
 Analog
Integrated
 Circuits
Tao Pi, C.-J. Richard Shi - Univ. of Washington, Seattle, WA
Session 2
ROOM:
 408A
BDD-BASED
 MODEL
 CHECKING
CHAIR: Andreas
 Kuehlmann -
 IBM
 Corp.,
 Yorktown
Heights,
 NY
ORGANIZERS: Limor
 Fix,
 Timothy
 Kam
This session presents three novel approaches to
increase the capacity of BDD-based model
checking. The first paper investigates the transitionfunction-based
and transition-relation-based
methods to compute the image during state
traversal and describes a new approach to combine
both. The second paper presents the application of
user-provided hints to guide the state traversal for
CTL model checking. The following presentation
describes a technique to optimize the model
checking process by dynamically excluding
irrelevant parts of the design from it. The last paper
presents an alternative heuristic to prioritize the
state traversal in order to boost its capacity.
2.1 To
 Split
 or
 to
 Conjoin:
 The
 Question
 in
Image
 Computation
In-Ho Moon - Univ. of Colorado, Boulder, CO
James Kukula - Synopsys, Inc., Beaverton, OR
Kavita Ravi - Cadence Design Systems, Inc., New Providence, NJ
Fabio Somenzi - Univ. of Colorado, Boulder, CO
2.2 Symbolic
 Guided
 Search
 for
 CTL
Model
 Checking
Roderick Bloem - Univ. of Colorado, Boulder, CO
Kavita Ravi - Cadence Design Systems, Inc., New Providence, NJ
Fabio Somenzi - Univ. of Colorado, Boulder, CO
2.3S Lazy
 Symbolic
 Model
 Checking
Jin Yang - Intel Corp., Hillsboro, OR
Andreas Tiemeyer - Intel Corp., Swindon, UK
2.4S Distance
 Driven
 Finite
 State
 Machine
Traversal
Andreas Hett, Christoph Scholl, Bernd Becker - Univ. of
Freiburg, Freiburg, Germany
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 3
ROOM:
 406AB
TEST
 GENERATION
 AND
DIAGNOSIS
CHAIR: Robert
 Aitken -
 Hewlett-
Packard
 Co.,
 Palo
 Alto,
 CA
ORGANIZER: Tim
 Cheng
This session includes test generation
and diagnosis techniques for a variety of
fault models and circuits described at
different levels of abstraction. The first
paper deals with RTL test generation.
The second paper presents a BIST
method for FPGAs. The third paper
describes a diagnosis technique for
scan-based BIST. The fourth paper
introduces an enhanced delay fault
model and a diagnosis technique for it.
3.1 Automatic
 Test
 Pattern
Generation
 for
 Functional
 RTL
Circuits
 Using
 Assignment
Decision
 Diagrams
Indradeep Ghosh, Masahiro Fujita - Fujitsu
Labs. of America, Sunnyvale, CA
3.2 Interconnect
 Testing
 in
Cluster-Based
 FPGA
 Architectures
Ian G. Harris, Russell Tessier - Univ. of
Massachusetts, Amherst, MA
3.3S Improved
 Fault
 Diagnosis
 in
Scan-Based
 Bist
 via
 Superposition
Ismet Bayraktaroglu, Alex Orailoglu - Univ. of
California at San Diego, La Jolla, CA
3.4S On
 Diagnosis
 of
 Pattern-
Dependent
 Delay
 Faults
Irith Pomeranz, Sudhakar M. Reddy - Univ. of
Iowa, Iowa City, IA
Session 4
ROOM:
 408B
INTERCONNECT
 MODELING
Tuesday, June 6
CHAIR: Nick
P. 
v an
d er
Me ijs -
Del ft
Univ.
o f
Te ch.,
Del ft,
T he
N
e
t
h
e
r
l
a
n
d
s
ORGANIZERS: Ralph
 H.J.M.
 Otten,
Anantha
Chandrakashan
Fast and accurate analysis of
interconnect is more and more important
for performance estimation of deep
submicron circuits. Inductance,
conveniently neglected in the past,
cannot be ignored anymore. The first
paper addresses that point. The second
paper presents a wealth of practical data
on this issue. The two final papers are
more general in nature: eff i c i e n t
techniques in model reduction and a
reevaluation for the so-called miller
effect on interconnect capacitance.
4.1 On-Chip
 Inductance
 Modeling
and
 Analysis
Kaushik Gala, Vladimir Zolotov, Rajendran V.
Panda, Brian Young, David Blaauw - Motorola,
Inc. Austin, TX
4.2 A
 Practical
 Approach
 to
 Parasitic
Extraction
f or
 Design
 of
 Multimillion-
Transistor
 Integrated
 Circuits
Eileen Yo u, Lakshminarasimh Varadadesikan -
Sun Microsystems, Inc., Palo Alto, CA
John Macdonald - Mentor Graphics Corp.,
Wilsonville, OR
Weize Xie - Hewlett-Packard Co., Palo Alto, CA
4.3S A
R ank-One
U pdate
M ethod
 for
Efficient
P rocessing
o f
I nterconnect
Parasitics
 in
 Timing
 Analysis
Jacob K. White - Massachusetts Instittute of
Technology, Cambridge, MA
4.4S Revisiting
 the
 Switch
 Factor
Based
 Analysis
 Methodology
 for
Coupled
 RC
 Interconnects
Sudhakar Muddu, Egino Sarto - SGI, Mountain
View, CA
Session 5
ROOM:
 403
LIFE
 AT
 THE
 END
 OF
CMOS
 SCALING
 (AND
BEYOND)
CHAIR: Rob
 A.
 Rutenbar
 -
 Carnegie
Mellon
 Univ.,
 Pittsburgh,
 PA
ORGANIZER: Rob
 A.
 Rutenbar
It is clear by now that CMOS scaling
cannot continue forever, and that we will
soon require a radical technology
change. And yet, exceedingly small
MOS devices are being created
t o d a y, devices about a hundred
atoms wide. Will we really be able to
scale this far down? What are the
obstacles to making such aggressively
scaled devices usable as circuits? And
what might come after CMOS? Our
invited speakers will fearlessly speculate
on these problems.
5.1 INVITED
 PAPER: CMOS
Transistor
 Scaling
 Limit
Chenming Hu - Univ. of California, Berkeley, CA
5.2 INVITED
 PAPER: Circuits
 and
Interconnect
 in
 Aggressively
Scaled
 MOS
Mark Horowitz - Stanford Univ., Stanford, CA
5.3 INVITED
 PAPER: Single
Electron
 Switches
 and
 Memory:
Devices,
 Technology
 and
Design
 Issues
Steve Chou - Princeton Univ., Princeton, NJ
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All
 speakers
 are
denoted
 in
 Bold
30
S
 -
 denotes
short
 paper
Tuesday, June 6
Session 6
ROOM:
 404AB
NEW
 TECHNIQUES
 FOR
SYNTHESIS
 AND
 MAPPING
C
H
A
I
R
: Leon
S tok -
I BM
C orp.,
Y orktown
H eights,
N Y
ORGANIZERS: Jason
 Cong,
Malgorzata
Marek-Sadowska
This session presents progress in synthesis and
technology mapping, including combined mapping
with gate-decomposition considering area-delay
trade-off, BDD-based logic synthesis, fine-grained
arithmetic optimization in data path synthesis, XORbased
decomposition, and watermarking of
synthesis solutions.
6.1 Area
 Control
 and
 Search
 Space
Limitations
 for
 Technology
 Mapping
Dirk-Jan Jongeneel - Delft Univ. of Tech., Delft, The
Netherlands
Robert K. Brayton - Univ. of California, Berkeley, CA
Ralph H.J.M. Otten - Delft Univ. of Tech., Delft, The Netherlands
Yosinori Watanabe - Cadence European Labs., Roma, Italy
6.2 BDS:
 A
 BDD-Based
 Logic
 Optimization
System
Congguang Yang, Maciej Ciesielski - Univ. of Massachusetts,
Amherst, MA
Vigyan Singhal - Cadence Berkeley Labs., Berkeley, CA
6.3 A
 Fine-Grained
 Arithmetic
Optimization
 for
 High-Performance/Low-
Power
 Data
 Path
 Synthesis
Junhyung Um, Taewhan Kim - Korea Advanced Institute of
Science, Taejon, Korea
C.L. Liu - National Tsing Hua Univ., Hsinchu, Taiwan ROC
6.4S Optimal
 Low
 Power
 XOR
 Decomposition
Hai Zhou - Synopsys, Inc, Mountain View, CA
D. F. Wong - Univ. of Texas, Austin, TX
6.5S Watermarking
 while
 Preserving
 the
Critical
 Path
Seapahn Meguerdichian, Miodrag Potkonjak - Univ. of
California, Los Angeles, CA
Session 7
ROOM:
 408A
FORMAL
 VERIFICATION
CHAIR: Limor
 Fix -
 Intel
 Semiconductors
 Ltd.,
Haifa,
 Israel
ORGANIZERS: Timothy
 Kam,
 Andreas
 Kuehlmann
Formal verification is scaling up in many
dimensions. From the application point of view, it is
scaling up from RT L verification to microarchitecture
and software verification. From the
technology point of view, it is scaling up from BDDbased
algorithms to ATPG and constraint solving
techniques.
7.1 Formal
 Verification
 of
 Superscalar
Microprocessors
 with
 Multicycle
 Functional
Units,
 Exceptions,
 and
 Branch
 Prediction
Miroslav N. Velev, Randal E. Bryant - Carnegie Mellon Univ.,
Pittsburgh, PA
7.2 Assertion
 Checking
 by
 Combined
 Word-
Level
 ATPG
 and
 Modular
 Arithmetic
Constraint-Solving
Techniques
Ric Chung-Yang Huang, Kwang-Ting (Tim) Cheng - Univ. of
California, Santa Barbara, CA
7.3 Reliable
 Verification
 Using
 Symbolic
Simulation
 with
 Scalar
 Values
Chris Wilson, David L. Dill - Stanford Univ., Stanford, CA
7.4 Automatic
 Formal
 Verification
 of
 DSP
Software
David W. Currie - Mentor Graphics Corp., Billerica, MA
Alan J. Hu - Univ. of British Columbia, Vancouver, BC, Canada
Sreeranga P. Rajan, Masahiro Fujita - Fujitsu Labs. of America,
Sunnyvale, CA
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 8
ROOM:
 406AB
TEST
 ISSUES
 FOR
DEEP-SUBMICRON
SYSTEM-ON-CHIPS
CHAIR: Janusz
 Rajski -
 Mentor
Graphics
 Corp.,
 Wilsonville,
 OR
ORGANIZERS: K.T.
 Cheng,
 Anand
Raghunathan
A major challenge in realizing core-based
system-on-chip is in adopting and designing-in
adequate test and diagnosis strategies. T h i s
embedded tutorial focuses on the current
industrial practices in designing SOC test. It
discusses the challenges in testing deeply
embedded cores supplied by diverse providers,
often using different hardware description level
and mixed technologies, and describes the
state-of-the-art practices that address these
challenges, such as system level test re-use
and integrating test for complex system-onchips.
In addition, this tutorial covers the current
standardization efforts for embedded core test
interface mechanisms.
8.1 Embedded
 Tutorial: Systemon-Chip:
How
 will
 it
 Impact
Your
 Design
Yervant Zorian - LogicVision, Inc., San Jose, CA
Erik Jan Marinissen - Philips Research Labs.,
Eindhoven, The Netherlands
The use of deep submicron process
technologies presents several new challenges
in the area of manufacturing test. While a
significant body of work has been devoted to
identifying and investigating design challenges
in nanometer technologies, the impact on test
strategies and methodologies is still not well
u n d e r s t o o d .
This embedded tutorial will highlight the
challenges to current test methodologies
arising from technology driven trends, and will
present an overview of emerging techniques
that address deep submicron test challenges.
8.2 Embedded
 Tutorial:
 Test
Challenges
 for
 Deep
 Sub-Micron
Technologies
Kwang -Ting (Tim) Cheng - Univ. of California,
Santa Barbara, CA
Sujit Dey - Univ. of California, San Diego, CA
Mike Rodgers - Intel Corp., Santa Clara, CA
Kaushik Roy - Purdue Univ., West Lafayette, IN
Tuesday, June 6
Session 9
ROOM:
 408B
CLOCK
 AND
 POWER
 GRID
A
N
A
L
Y
S
I
S FOR
 HIGH
PERFORMANCE
 DESIGNS
CHAIR: Vivek
 Tiwari -
 Intel
 Corp.,
 Santa
Clara,
 CA
ORGANIZERS: Ingrid
 Verbauwhede,
Mojy
 Chian
Higher level of integration of modern chips have
significantly increased the size and complexity of the
power and clocking networks. The first paper in this
session focuses on hierarchical analysis of power
networks. The second paper demonstrates an
e fficient reduction method. The third paper presents
a novel approach for fast vector compression for IRdrop
analysis. The final two papers analyze the
impact of process variation on clock skew.
9.1 Hierarchical
 Analysis
 of
 Power
Distribution
Networks
Min Zhao - Univ. of Minnesota, Minneapolis, MN
Rajendran V. Panda - Motorola, Inc., Austin, TX
Sachin S. Sapatnekar - Univ. of Minnesota,
Minneapolis, MN
Tim Edwards, Rajat Chaudhry, David Blaauw -
Motorola, Inc., Austin, TX
9.2 Fast
 Power
 Grid
 Simulation
Sani R. Nassif - IBM Austin Research Lab., Austin, TX
Joseph N. Kozhaya - Univ. of Illinois, Urbana, IL
9.3 Current
 Signature
Compression
 for
 IR-Drop
 Analysis
Rajat Chaudhry, David Blaauw, Rajendran V.
Panda, Tim Edward s - Motorola, Inc., Austin, TX
9.4S Impact
 of
 Interconnect
Variations
 on
 the
 Clock
 Skew
 of
 a
Gigahertz
Microprocessor
Ying Liu - Carnegie Mellon Univ., Pittsburgh, PA
Sani R. Nassif - IBM Austin Research Lab., Austin, TX
Lawrence T. Pileggi, Andrzej J. Strojwas - Carnegie
Mellon Univ., Pittsburgh, PA
9.5S A
 Methodology
 for
 Modeling
the
 Effects
 of
 Systematic
 Within-
Die
 Interconnect
 and
 Device
Variation
 on
 Circuit
 Performance
Vikas Mehrotra, Shiou Lin Sam, Duane Boning,
Anantha Chandrakasan - Massachusetts Institute of
Te c h n o l o g y, Cambridge, MA
Rakesh Va l l i s h a y e e - PDF Solutions, San Jose, CA
Sani R. Nassif - IBM Austin Research Lab., Austin, TX
Session 10
ROOM:
 403
PANEL:
 DESIGN
CLOSURE:
 HOPE
 OR
HYPE?
CHAIR: Kurt
 Keutzer
 -
 University
 of
California,
 Berkeley,
 CA
ORGANIZERS: Andrew
 Kahng,
 Gloria
Nicols,
 Vik
 Kulkarni
It’s been one year since Richard Goering
told us that the EDA RTL-to-GDSII world
was about to change. What have we
learned? Who’s winning, and who’s
not? This panel, consisting of the
leading large and upcoming players in
this space, will deliver concrete data to
d i fferentiate leading approaches to
achieving design closure. Does the solution
lie in raw speed and RTL optimization, with
the synthesis-place-route back end just a
commodity? Does the solution lie in new
metrics for design convergence, and
symmetric multiprocessing platforms for
efficiency? Does the solution lie in a holistic,
unified architecture of data model and
tools? Or does the solution lie in extensions
and unifications of existing productionproven
logic, timing, and layout optimization
technologies? A hard-hitting panel session
will reveal the answers!
PANELISTS:
Raul
 Camposano -
 Synopsys,
 Inc.,
Mountain
 View,
 CA
Jacob
 Greidinger -
 Aristo
Technology,
 Cupertino,
 CA
Patrick
 Groeneveld -
 Magma
 Design
Automation,
 Cupertino,
C A
Michael
 Jackson
 -
 Avant!
 Corp.,
Fremont,
 CA
Larry
 Pileggi
 -
 Monterey
 Design
Systems,
 Sunnyvale,
 CA
Lou
 Scheffer -
 Cadence
 Design
Systems,
 Inc.,
 San
 Jose,
 CA
Martin
 Walker -
 Frequency
Technology,
 Santa
 Clara,
 CA
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short
 paper
Tuesday, June 6
Session 11
ROOM:
 404AB
ALGORITHMS
 FOR
 RF
SIMULATION
 AND
 MODEL
REDUCTION
CHAIR: Alan
 Mantooth -
 Univ.
 of
 Arkansas,
Fayetteville,
 AR
ORGANIZERS: Hidetoshi
 Onodera,
 Alan
 Mantooth
A multi-interval Chebyshev method is described that
discretizes the circuit equations by dividing the
simulation domain into intervals and represents the
solution using Chebyshev polynomials. This method
is applied to nonlinear RF circuits. The remaining
two papers involve model reduction. The first paper
is on weakly nonlinear systems, which is a
generalization of popular linear techniques. The
second paper describes a novel driving point model
for on-chip interconnect including inductance.
11.1 A
 Multi-Interval
 Chebyshev
 Collocation
Method
 for
 Efficient
 High-Accuracy
 RF
Circuit
 Simulation
Baolin Yang, Joel R. Phillips - Cadence Design Systems, Inc.
San Jose, CA
11.2 Projection
 Frameworks
 for
 Model
Reduction
 of
 Weakly
 Nonlinear
 Systems
Joel R. Phillips - Cadence Design Systems Inc., San Jose, CA
11.3 A
 Realizable
 Driving
 Point
 Model
 for
On-Chip
 Interconnect
 with
 Inductance
Chandramouli Kashyap, Byron Krauter - IBM Corp., Austin, TX
Session 12
ROOM:
 408A
VERIFICATION
 AND
DEBUGGING
METHODOLOGIES
CHAIR: Ivo
 Bolsens -
 IMEC,
 Leuven,
 Belgium
ORGANIZER: Ivo
 Bolsens
The first two papers present case studies on the
application of formal verification techniques to an
on-chip bus arbiter core and iterative circuits in
microprocessors. The last paper talks about a
technique to support incremental FPGA b a s e d
emulation.
12.1 Verification
 of
 an
 IBM
 Coreconnect
Processor
 Local
 Bus
 Arbiter
 Core
Amit Goel - Carnegie Mellon Univ., Pittsburgh, PA
William Lee - IBM Microelectronics, Research Triangle Park, NC
12.2 Formal
 Verification
 of
 Iterative
Algorithms
 in
 Microprocessors
Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine
Kohatsu, Carl-Johan H. Seger - Intel Corp., Hillsboro, OR
12.3 Efficient
 Error
 Detection,
 Localization,
and
 Correction
 for
 FPGA-Based
 Debugging
John Lach, William H. Mangione-Smith, Miodrag Potkonjak -
Univ. of California, Los Angeles, CA
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 13
ROOM:
 406AB
DESIGN
 METHODS
 FOR
EMERGING
TECHNOLOGIES
CHAIR: Ingrid
 Verbauwhede -
 Univ.
 of
California,
 Los
 Angeles,
 CA
ORGANIZERS: Tadahiro
 Kuroda,
Telle
 Whitney
The future IC will include very different
technologies. This session includes
papers that suggest some of them.
The first paper describes design
implementation and performance
evaluation of 3-D IC’s. The second
paper gives a strategy to design and
model the optical interconnects. T h e
third paper describes the design of a
quantum DOT based microprocessor.
13.1 Multiple
 SI
 Layer
 ICs:
Motivation,
Performance
Analysis,
 and
 Design
 Implications
Shukri Souri, Kaustav Banerjee - Stanford Univ.,
Stanford, CA
Amit Mehrotra - Univ. of Illinois, Urbana, IL
Krishna C. Saraswat - Stanford Univ., Stanford, CA
13.2 High-Level
 Model
 for
 a
 WDMA
Passive
 Optical
 Interconnection
Scheme
 for
 a
 Reconfigurable
Multiprocessor
System
Vince Boros - Univ. of Queensland, St Lucia,
Australia
13.3 DESIGN CONTEST: A
 Design
 of
and
 Design
 Tools
 for
 a
 Novel
Quantum
 Dot
 Based
 Microprocessor
Peter Kogge, Michael Kontz, Michael Niemier -
Univ. of Notre Dame, Notre Dame, IN
Session 14
ROOM:
 408B
SIGNAL
 INTEGRITY
Tuesday, June 6
CHAIR: Luis
 Miguel
 Silveira -
INESC/IST,
 Lisboa,
 Portugal
ORGANIZERS: Joel
 Phillips,
 Lou
Scheffer
Controlling noise on signals is of critical
importance in deep submicron chips.
The first paper describes a tool and flow
for noise analysis and control. T h e
second and third papers describes the
extensions needed for SOI and dynamic
logic. The fourth paper contains a new
approach to reduced models intended to
make multiport analysis faster without
sacrificing too much accuracy.
14.1 Clarinet:
 A
 Noise
 Analysis
Tool
 and
 Methodology
 for
 Deep-
Submicron
 Design
Shoba Alwar, Aurobindo Dasgupta, Amir
Grinshpon, Rafi Levy, Chanhee Oh, Boaz O r s h a v,
Vladimir Zolotov - Motorola, Austin, TX
14.2S Static
 Noise
 Analysis
 for
Digital
 Integrated
 Circuits
 in
Partially-Depleted
Silicon-on-
Insulator
Technology
Kenneth L. Shepard, Dae-Jin Kim - Columbia
Univ., New York, NY
14.3S Dynamic
 Noise
 Immunity
in
 Precharge-Evaluate
 Circuits
Dinesh Somasekhar - Intel Corp., Hillsboro, OR
Seung Hoon Choi, Kaushik Roy - Purdue Univ.,
West Lafayette, IN
Yibin Ye, Vivek De - Intel Corp., Hillsboro, OR
14.4 Extended
 Krylov
 Subspace
Method
 for
 Reduced
 Order
Analysis
 of
 Linear
 Circuits
 with
Multiple
 Sources
Tuyen V. Nguyen - IBM Austin Research Lab.,
Austin, TX
Janet M.L. Wa n g - Univ. of California, Berkeley, CA
Session 15
ROOM:
 403
PANEL:
 EDA
MEETS
 .COM:
 HOW
E-SERVICES
 WILL
CHANGE
 THE
 EDA
BUSINESS
 MODEL
CHAIR: Jennifer
 Smith
 -
 Dain
 Rauscher
Wessels,
 San
 Francisco,
 CA
ORGANIZERS: Tom
 Quan,
 Andrew
 Kahng
The skyrocketing complexities of SOC
design have led to such design
bottlenecks as iterations, poor scaling
of tools, and inadequate computational
power of desktop workstations and servers.
At the same time, many organizations face
long capital budgeting cycles for new
hardware and software, and increased total
cost of ownership (software, maintenance,
integration, training, etc.) for their design
c a p a b i l i t y. This panel addresses the "dot
.com" phenomenon and its associated
technology and infrastructure -- e-services -which
offer the promise of new design
capabilities for chip designers and new
business models for EDA companies. Issues
include (1) for EDA, how will e-services
transform sales channels, the push to
interoperability, or how customer needs are
addressed? (2) for ASIC vendors, will eservices
change how end users design, and
how vendors deploy their services? (3) for eservices
providers and investors, what's real,
what's the market, and how does this affect
valuations and business strategy?
PANELISTS:
Jacques
 Benkoski
 -
 Monterey
 Design
Systems,
 Sunnyvale,
 CA
David
 Dick -
 Fujitsu
 Microelectronics,
San
 Jose,
 CA
Adriaan
 Ligtenberg -
 Cadence
 Design
Systems,
 Inc.,
 San
 Jose,
 CA
Mike
 Schuh -
 Foundation
 Capital,
 Palo
Alto,
 CA
Greg
 Spirakis -
 Intel
 Corp.,
 Santa
Clara,
 CA
Bruce
 Toal -
 Hewlett-Packard
 Co.,
Richardson,
 TX
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 speakers
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34
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 denotes
short
 paper
Wednesday, June 7
Session 16
ROOM:
 404AB
TIMING
 ANALYSIS
 AND
VERIFICATION
CHAIR:
Hidetoshi
 Onodera -
 Kyoto
 Univ.,
 Kyoto,
Japan
ORGANIZERS: Srinivas
 Devadas,
 Hidetoshi
 Onodera
The first paper shows a symbolic simulation method
for transister-level simulation. The second paper
presents a novel dynamic delay model to take into
account capacitive coupling, while the next paper
takes into account coupling effects during timing
analysis. The last paper presents an algorithm to
remove false paths in a timing graph model.
16.1 Symbolic
 Timing
 Simulation
 Using
Cluster
 Scheduling
Clayton B. McDonald, Randal E. Bryant - Carnegie Mellon
Univ., Pittsburgh, PA
16.2 Critical
 Path
 Analysis
 Using
 a
Dynamically
 Bounded
 Delay
 Model
Soha Hassoun - Tufts Univ., Medford, MA
16.3S Taco:
 Timing
 Analysis
 with
 Coupling
Ravishankar Arunachalam - Carnegie Mellon Univ.,
Pittsburgh, PA
Karthik Rajagopal - Intel Corp., Santa Clara, CA
Lawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA
16.4S Removing
 User-Specified
 False
Paths
 from
 Timing
 Graphs
Rajendran V. Panda, David Blaauw - Motorola, Inc., Austin, TX
Session 17
ROOM:
 408A
LOGIC/PHYSICAL
CO-DESIGN
CHAIR: Massoud
 Pedram -
 Univ.
 of
 Southern
California,
 Los
 Angeles,
 CA
ORGANIZERS: Jason
 Cong,
Margaret
Marrek-Sadowska
This session presents novel techniques that link
logical and physical designs. The first paper
presents and efficient technique for performancedriven
circuit partitioning with retiming to minimize
global interconnect delays. The second paper
proposes an interesting concept called the crosstalk
immunity set in the logic domain which can help
noise-avoidance layout. The third paper explores
the use of functional symmetry in post-layout
optimization. The last paper presents a fast
incremental FPGA mapping algorithm which
supports an efficient iterative design methodology.
17.1 Performance-Driven
 Multi-Level
 and
Multi-Way
 Partitioning
 with
 Retiming
Jason Cong, Sung Kyu Lim - Univ. of California, Los Angeles, CA
Chang Wu - Aplus Design Technologies, Inc., Los Angeles, CA
17.2 High
 Performance
 Domino
 Logic
Synthesis
 with
 Noise
 Constraints
Ki-Wook Kim, Sung-Mo Kang - Univ. of Illinois, Urbana, IL
Unni K. Narayanan - Intel Corp., Santa Clara, CA
17.3S Fast
 Post-Placement
 Rewiring
 Using
Easily
 Detectable
 Functional
 Symmetries
Chih-Wei (Jim) Chang - Univ. of California, Santa Barbara, CA
Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
Peter R. Suaris - Mentor Graphics Corp., Wilsonville, OR
M a l g o rzata Mare k - S a d o w s k a - Univ. of California, Santa Barbara, CA
17.4S Depth
 Optimal
 Incremental
 Mapping
for
 Field
 Programmable
 Gate
 Arrays
Jason Cong - Univ. of California, Los Angeles, CA
Hui Huang - Stanford Univ., Stanford, CA
*
 Please
 be
 advised
t hat
 the
 two
Ke ynotes
 and
 some
 of
t he
T echnical
S essions
 will
b e
video
t aped
 during
 the
c onference.
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 18
ROOM:
 406AB
POWER
 ANALYSIS
 AND
OPTIMIZATION
 FOR
EMBEDDED
 SOFTWARE
CHAIR: Luca
 Benini -
 Univ.
 of
 Bologna,
Bologna,
 Italy
ORGANIZERS: John
 Glossner,
Luciano
 Lavagno
This session deals with several levels at
which the problem of software power
consumption can be handled. The first
paper discusses how bus and memory
activity can be minimized by compressing
the code. The next paper discusses how
part of the data cache can be hardwired
and optimized for power. The next two
papers deal with compiler optimizations.
Finally the impact of the real-time operating
system is discussed, considering
communication and scheduling primitives.
18.1 Code
 Compression
 for
 Low
Power
 Embedded
 System
 Design
Haris Lekatsas - Princeton Univ., Princeton, NJ
Joerg Henkel - NEC USA, C&C Research Labs.,
Princeton, NJ
Wayne Wolf - Princeton Univ., Princeton, NJ
18.2S Synthesis
 of
 Application-
Specific
 Memories
 for
 Power
Optimization
in 
 Embedded
S ystems
Luca Benini - Univ. of Bologna, Bologna, Italy
A l b e rto Macii, Enrico Macii, Massimo Poncino -
Politecnico di Torino, Torino, Italy
18.3S Influence
 of
 Compiler
Optimizations
 on
 System
 Power
Mahmut Kandemir, Vijaykrishnan Narayanan,
Mary Jane Irwin, Wu Ye - Penn State Univ.,
University Park, PA
18.4S Power
 Minimization
Derived
 from
 Architectural-Usage
of
 VLIW
 Processors
Catherine H. Gebotys - Univ. of Waterloo,
Waterloo, ON, Canada
18.5S Power
 Analysis
 of
Embedded
 Operating
 Systems
Ganesh Lakshminarayana - NEC USA, C&C
Research Labs., Princeton, NJ
Session 19
ROOM:
 408B
EMBEDDED
COMPILATION
TECHNIQUES
Wednesday, June 7
CHAIR: John
 Glossner -
 IBM
 Corp.,
Yorktown
 Heights,
 NY
ORGANIZERS: Kees
 Vissers,
 Luciano
Lavagno
This session explores compilation
techniques for embedded systems.
Memory latency is an important issue. A
compiler that reorders code to hide
memory latency for DSP and multimedia
applications is discussed. The second
paper shows how to compile a language
with concurrency and timing constraints
into fast sequential code. Two shorter
papers discuss minimizing memory
bandwidth in telecom applications and
using compilers to predict the
performance of a program as an aid for
h a n d - o p t i m i z a t i o n .
19.1 Memory
 Aware
 Compilation
through
 Accurate
 Timing
Extraction
Peter Grun, Nikil D. Dutt, Alexandru Nicolau -
Univ. of California, Irvine, CA
19.2 Compiling
 Esterel
 into
Sequential
 Code
Stephen A. Edwards - Synopsys, Inc.,
Mountain View, CA
19.3S Interactive
 Algorithms
 for
Minimizing
 Memory
 Bandwidth
 in
High
 Throughput
 Telecom
 and
Multimedia
Omnes Thierry - IMEC VZW - Desics, Leuven,
Belgium
19.4S Predicting
Performance
Potential
 of
 Modern
 DSPs
Naji S. Ghazal, A. Richard Newton, Jan M.
Rabaey - Univ. of California, Berkeley, CA
Session 20
Room:
 ROOM:
 403
PANEL:
 FUTURE
SYSTEMS-ON-CHIP:
SOFTWARE
 OR
HARDWARE
 DESIGN?
CHAIR: Brian
 DiPert -
 EDN,
Sacramento,
 CA
ORGANIZERS: Shishpal
 Rawat,
Sylvia
 Tam
Advances in device technology have led to
an era where entire systems can be
implemented on a single component,
commonly referred to as system-onchip.
With shrinking product life cycles
placing severe time to market demands on
manufacturers, coupled with their need to
quickly change a product's feature set to
address evolving customer requirements,
programmability will emerge as a cornerstone
for all chips implemented in the future.
The Internet, communications, consumer
electronics, and computing markets are first
to take advantage of system-on-chip
t e c h n o l o g y. What are the benefits of
programmability to these and other markets
and are there potential pitfalls? What
architectures and programmability (or
reconfigurability) are going to be the likely
winners and at what cost? Are these
architectures likely to converge or diverge?
The panelists will debate the merits of their
existing approaches and how they are likely
to be shaped in the future.
PANELISTS:
Barry
 Britton
 -
 Lucent
 Technologies,
Allentown,
 PA
Bob
 Broderson
 -
 Univ.
 of
 California,
Berkeley,
 CA
Bob
Co lwell -
I ntel
Co rp.,
Hi llsboro,
 OR
Bill
 Harris
 -
 Cisco
 Systems,
 Research
Triangle
 Park,
 NC
Chris
 Rowen
- 
T ensilica,
 Santa
C lara,
 C
A
Danesh
 Tavana -Triscend,
 Mountain
View,
 CA
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short
 paper
Wednesday, June 7
Plenary Panel
ROOM:
 Concourse
 Hall
PANEL:
 EMBEDDED
 SYSTEMS
 DESIGN
 IN
 THE
 NEW
 MILLENNIUM
CHAIR:
 A.
 Richard
 Newton,
 Univ.
 of
 California,
 Berkeley,
 CA
ORGANIZER: Randolph
 E.
 Harr
As
 we
 turn
 the
 corner
 into
 the
 new
 century,
 design
 is
 increasingly
 focused
 on
 single
 integrated
circuit
 implementations
 of
 complete
 systems.

 Similar
 to
 alchemy
 in
 the
 middle
 ages,
 the
 design
of
 a
 complex
 system
 onto
 an
 IC
 is
 an
 art
 and
 possibly
 an
 illusion
 understood
 by
 a
 very
 few.

 It
is
 a
 complex
 search
 for
 an
 optimal
 answer
 which
 requires
 understanding
 the
 application,
 the
system
 domain,
 digital
 function
 and
 control,
 and
 the
 fundamentals
 of
 circuits
 and
 IC
fabrication
 technology.
 Due
 to
 the
 complexity
 of
 standards
 and
 processing,
 no
 one
 company
understands
 or
 owns
 all
 of
 the
 needed
 technologies.
This
 plenary
 panel
 draws
 on
 leaders
 from
 companies
 that
 are
 successfully
 addressing
 embedded
system
 design
 problems
 in
 the
 new
 millennium.
 The
 panelists
 will
 discuss
 what
 they

 perceive
 as
the
 biggest
 problems
 today
 and
 down
 the
 road,
 and
 outline
 solutions
 they
 will
 have
 a
 part
 in
bringing
 about.
They
 will
 collectively
 address
 the
 challenges
 of
 authoring
 and
 integrating
 major
 components
such
 as
 microprocessors,
 memory,
 custom
 digital
 logic
 and
 software
 into
 a
 single
 design.
Questions
 that
 arise
 in
 the
 design
 of
 complex
 embedded
 systems
 are:
1)
 How
 does
 one
r efine
 an
app lication
pr oblem
 to
 a
 solution
 in
t he
 face
of 
I C
t echnology
limitations?
 
Ar e
 there
t hat
ma ny
t all,
 thin
 designers
or 
ar e
t hey
 not
r eally
t he
 norm
 needed?
2)
 Are
 the
 issues
 the
 same
 old
 DSM
 issues
 as
 for
 custom
 design:
 problems
 induced
 by
 the
physics
 of
 the
 sub-micron
 structures
 as
 well
 as
 problems
 induced
 by
 the
 shear
 enormity
of
 the
 millions
 of
 components?
3)
 How
 does
 one
 trade-off
 the
 power
 savings
 and
 performance
 gains
 of
 custom
 hardware
with
 the
 flexibility
 and
 reusability
 of
 programmable
 solutions?
4)
 What
 about
 balancing
 the
 increasing
 mixed
 functions
 of
 embedded
 DSP
 with
 analog
 and
user
 interfaces?
5)
 Are
 shrinking
 time
 to
 market
 and
 market
 lifetime
 windows
 forcing
 everything
 to
 a
reusable
 architectural
 platform?
6)
 Can
 anything
 be
 learned
 from
 board
 /
 subsystem
 design
 techniques
 and
 carried
 down
 to
Embedded
 System
 on
 a
 Chip
 design?
7)
 How
 do
 we
 achieve
 and
 exploit
 the
 most
 transistors?

 Think
 of
 the
 problem
 as
 inherently
parallel
 and
 figure
 out
 ways
 to
 synchronize
 where
 needed?

 Or
 treat
 it
 as
 a
 traditional
software,
 sequential
 specification
 and
 look
 for
 ways
 to
 parallelize
 to
 tasks?
The
group
 
 will
compar e
 the
chall enges
t hey
have
f aced
in
implement ing
embedded
 systems
as
well
as
 the
 solutions
t hat
 have
 come
 to
 fruition
 thus
 far.
 They
 will
c onsider
 whether
 embedded
 systemon-a-chip
is
 the
 dawn
 of
 a
 new
 industry,
 the
 natural
 progression
 of
 the
 existing
 semiconductor
integrated
 circuit
 market,
 or
 the
 seemingly
 unreachable
 goal
 of
 turning
lead
 into
 gold.
PANEL
 MEMBERS:
Tudor
 Brown -
 ARM,
 LOCATION
Sönke
 Mehrgardt -
 Infineon
 Technologies,
 Munich,
 Germany
Walden
C .
Rh ines -
M entor
Gr aphics
Cor p.,
W ilsonville,
OR
Henry
 Samueli -
 Broadcom,
 Irvine,
 CA
Geoff
 Tate -
 Rambus,
 LOCATION

Biographies
Wednesday, June 7
Tudor
 Brown
Tudor
 Brown
 graduated
 in
 Electrical
 Sciences
 from
Cambridge
 University
 in
 1989.
 His
 early
 career
 included
industrial
 control,
 Ethernet
 and
 graphics
 controllers;
bringing
 together
 analog
 electronics
 and
 computer
engineering.
 He
 has
 been
 dedicated
 to
 ARM
developments
 since
 1984,
 leading
 several
 CPU
 and
system
 designs
 in
 that
 time.
 He
 has
 managed
 the
development
 team
 since
 1991
 and
 been
 CTO
 since
 1997.
Sönke
 Mehrgardt
Dr.
 Sönke
 Mehrgardt
 was
 elected
 to
 the
 Management
Board
 of
 Infineon
 Technologies
 in
 April
 1999.
 He
 is
Chief
 Technology
 Officer
 and
 Executive
 Vice
 President.
Previously
 he
 held
 the
 position
 President
 Signal
Processing
 and
 Control
 and
 before
 that
 President
 of
Consumer
 Electronics
 ICs
 in
 Siemens
 Semiconductor
Group.
Aft er
being
t en
 years
w ith
IT T-Semiconductor,
Dr.
 Mehrgardt
 
 joined
 Siemens
 in
 1993.
 He
 holds
 a
 MA
in
 Physics
 and
 an
 Ph.D.
 in
 Natural
 Science
 from
 the
University
 of
 Goettingen
 and
 where
 he
 was
 Assistant
Professor
 at
 the
 university
for
nine
years .
Richard
 Newton
Richard
 Newton
 has
 been
 actively
 involved
 as
 a
researcher
 and
 teacher
 in
 the
 areas
 of
 design
technology,
 electronic
 system
 architecture,
 and
integrated
 circuit
 design
 since
 1979.
 In
 addition
 to
his
 academic
 role,
 Professor
 Newton
 has
 helped
 to
found
 a
 number
 of
 design
 technology
 companies,
including
 SDA
 Systems
 (now
 Cadence
 Design
 Systems),
PIE
 Design
 Systems,
 Simplex
 Solutions,
 and
 Synopsys,
where
 he
 rejoined
 the
 Board
 of
 Directors
 in
 1994.
Since
 1988,
 he
 has
 acted
 as
 a
 Venture
 Partner
 with
the
 Mayfield
Fund, 
a
 high-technology
v enture
capi tal
partnership,
 where
 he
 has
 contributed
 to
 both
 the
evaluation
 and
 early-stage
 development
 of
 over
 a
dozen
 new
 companies
 and
 is
 presently
 a
 Member
 of
 the
Board
 of
 Directors
 of
 two
 of
 them.
 Professor
 Newton
is
 a
 member
 of
 the
 Microsoft
 Research
 Laboratories
Technical
 Advisory
Board
 and
is 
 a
Fel low
 of
 the
 IEEE.
Walden
 C.
 Rhines
Walden
 C.
 Rhines
 is
 President
 and
 Chief
 Executive
Officer
 of
 Mentor
 Graphics.

 He
 joined
 Mentor
 in
 1993
from
 Texas
 Instruments
 (TI)
 where
 he
 was
 most
recently
 Executive
 Vice
 President
 in
 charge
 of
 TI's
semiconductor
 business.

 During
 twenty-one
 years
 at
TI,
 he
 managed
 all
 parts
 of
 their
 semiconductor
 and
computer
 systems
 businesses
 and
 was
 responsible
 for
development
 of
 key
 products
 such
 as
 TI's
 TMS
 320
family
 of
 digital
 signal
 processors
 and
 speech
synthesis
 components
 for
 Speak
 'N
 Spell.


 He
 is
currently
 Vice
 Chairman
 of
 the
 Electronic
 Design
Automation
 Consortium
 and
 a
 board
 member
 of
 Lewis
and
 Clark
 College,
 the
 Oregon
 Independent
 College
Foundation,
 SEMI/Sematech
 and
 the
 Oregon
Symphony.
 He
 received
 a
 BSE
 degree
 from
 the
University
 of
 Michigan,
 an
 MS
 and
 PhD
 from
 Stanford
University,
 an
 MBA
 from
 Southern
 Methodist
University
 and
 an
 Honorary
 Doctor
 of
 Technology
degree
 from
 Nottingham
 Trent
 University.
Henry
 Samueli
Dr.
 Henry
 Samueli
 co-founded
 Broadcom
 Corporation
in
 1991.
 As
 Co-Chairman
 and
 Chief
 Technical
 Officer
of
 the
 company,
 he
 is
 responsible
 for
 all
 research
 and
development
 activities.
 Broadcom
 is
 a
 leading
supplier
 of
 integrated
 circuits
 enabling

 broadband
communications
 to
 and
 throughout
 the
 home
 and
business.
 
 Dr.
 Samueli
 also
 co-founded
 PairGain
Technologies
 in
 1988
 and
 served
 as
 Chief
 Scientist
 of
the
 company
 until
 1994.
 From
 1985-1995
 he
 was
 a
Professor
 in
 the
 Electrical
 Engineering
 Department
 at
UCLA
 where
 he
 supervised
 advanced
 research
programs
 in
 broadband
 communications
 circuits.

 He
has
 published
 over
 100
 papers
 on
 the
 subject.
 From
1980-1985,
 he
 held
 various
 engineering
 management
positions
 in
 the
 Electronics
 and
 Technology
 Division
of
 TRW,
 Inc.
 Dr.Samueli
 is
 on
 the
 Board
 of
 Trustees
of
 the
 UCI
 Foundation
 and
 he
 is
 a
 member
 of
 the
 UCI
Chief
 Executive
 Roundtable.

 He
 is
 also
 a
 member
 of
the
 Board
 of
 Directors
 of
 the
 Orange
 County
Performing
 Arts
 Center

 and
 Project
 Tomorrow,
 a
 nonprofit
organization
 supporting
 K-12
 math
 and
science
 education.

 Dr.
 Samueli
 received
 a
 B.S.,
 M.S.
and
 Ph.D.
 in
 Electrical
 Engineering
 from
 UCLA
 in
 1975,
1976,
 and
 1980,
 respectively.
Geoff
 Tate
Geoff
 Tate
 has
 been
 CEO
 of
 Rambus
 Inc.
 since
 May
1990;
 and
 is
 a
 Member
 of
 the
 Board
 of
 Rambus
 Inc.
From
 1979
 to
 1990,
 Geoff
 was
 at
 Advanced
 Micro
Devices
 in
 various
 positions:
 his
 last
 position
 was
Senior
 Vice
 President
 of
 the
 Microprocessor
 &
 Logic
Group.

 Geoff
 received
 a
 Bachelors
 in
 Computer
Science
 from
 University
 of
 Alberta
 in
 1974;
 and
 an
MBA
 from
 Harvard
 University
 in
 1976.
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S
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short
 paper
Wednesday, June 6
Session 21
ROOM:
 404AB
NEW
 TECHNIQUES
 IN
 POWER
ESTIMATION
 AND
PERFORMANCE
IMPROVEMENT
CHAIR: Vivek
 Tiwari -
 Intel
 Corp.,
 Santa
 Clara,
 CA
ORGANIZERS: Luciano
 Lavagno,
 Timothy
 Kam
The first three papers present new techniques in
power estimation. The fourth paper proposes
pipelined FSMs. The last paper discusses analysis
and optimization techniques to improve
performance of system design.
21.1 The
 Design
 and
 Use
 of
 Simplepower:
 A
Cycle-Accurate
 Energy
 Estimation
 Tool
Wu Ye, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary
Jane Irwin - Penn State Univ., University Park, PA
21.2 An
 Instruction-Level
 Functionality-
Based
 Energy
 Estimation
 Model
 for
 32-bits
Microprocessors
Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella
Sciuto - Politecnico di Milano, Milano, Italy
21.3S Dynamic
 Power
 Management
 of
Complex
 Systems
 Using
 Generalized
Stochastic
 Petri
 Nets
Qinru Qiu, Qing Wu, Massoud Pedram - Univ. of Southern
California, Los Angeles, CA
21.4S Wave-Steering
O ne-Hot
 Encoded
F SMs
Luca Macchiarulo, Malgorzata Marek-Sadowska - Univ. of
California, Santa Barbara, CA
21.5 Performance
 Analysis
 and
Optimization
 of
 Latency
 Insensitive
Systems
Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli - Univ. of
California, Berkeley, CA
Session 22
ROOM:
 408A
COMBINED
 GLOBAL
 ROUTING,
BUFFERING
 AND
 WIRESIZING
CHAIR: Patrick
 Groeneveld -
 Magma
 Design
Automation,
 Inc.,
 Cupertino,
 CA
ORGANIZERS: Lou
 Scheffer,
 Patrick
 Groeneveld
This session deals with routing long wires during
top-level routing on the chip. To optimize delay,
buffers must be inserted. A problem is that these
buffers cannot be placed as arbitrary locations, but
only in specific areas. The papers provide various
solutions to this problem. The last paper deals with
combined routing and wiresizing.
22.1 A
 Fast
 Algorithm
 for
 Context-Aware
Buffer
 Insertion
John Lillis, Ashok Jagannathan, Sung-Woo Hur - Univ. of
Illinois, Chicago, IL
22.2 Maze
 Routing
 with
 Buffer
 Insertion
and
 Wiresizing
Minghorng Lai, D.F. Wong - Univ. of Texas, Austin, TX
22.3 Routing
 Tree
 Construction
 with
 Fixed
Buffer
 Insertion
Jason Cong, Xin Yuan - Univ. of California, Los Angeles, CA
22.4 A
 Current
 Driven
 Routing
 and
Verification
 Methodology
 for
 Analog
Applications
Thorsten Adler - Infineon Technologies AG, Munich, Germany
Lars Hedrich, Hiltrud Brocke, Erich Barke - Univ. of Hanover,
Hanover, Germany
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 23
Room:
 ROOM:
 406AB
ADVANCES
 IN
S YSTEM
MODELING
A ND
 SYNTHESIS
CHAIR: Rajesh
 K.
 Gupta -
 Univ.
 of
California,
 Irvine,
 CA
ORGANIZERS: Randolph
 Harr,
Donatella
 Sciuto
The session presents different approaches to
system level modeling, synthesis, and optimization.
The first deals with a new base model of
representation for system designs, while the
second considers system-level modeling from the
embedded OS perspective. The next two papers
introduce different aspects of the Espirit/OMI Cosy
Project. The fifth paper shows a task scheduling
algorithm based on Peri Nets, while the last one
considers partitioned cache to improve the
performance of embedded applications.
23.1 A
C odesign
 Virtual
M achine
f or
Hierarchical,
B alanced
 Hardware/
Software
S ystem
M odeling
Joann Paul, Simon Peffers, Donald E. Thomas -
Carnegie Mellon Univ., Pittsburgh, PA
23.2 An
 Operating
 System
Approach
 to
 System
 Level
 Design
Dirk Desmet, Diederik Verkest, Hugo De Man -
IMEC, Leuven, Belgium
23.3S YAPI:
 Application
 Modeling
for
 Signal
 Processing
 Systems
E rwin de Kock, Gerben Essink, Wim Smits, Pieter van
der Wolf, Jean-Yves Brunel, Wido Kru i j t z e r, Paul Lieverse -
Philips Research Labs., Eindhoven, The Netherlands
Kees A. Vi s s e r s - Univ. of California, Berkeley, CA
23.4S Cosy
 Communication
 IP’s
J e a n - Yves Bru n e l, Wido Kru i j t z e r, Arjan Kenter -
Philips Research Labs., Eindhoven, The Netherlands
Frederic Petrot - Univ. Pierre et Marie Curie
L a u rent Pasquier - Philips Research Labs., Paris, France
Erwin de Kock, Wim Swits - Philips Research
Labs., Eindhoven, The Netherlands
23.5S Synthesis
 and
 Optimization
of
C oordination
 Controllers
 for
Distributed
 Embedded
S ystems
Gaetano Borriello - Univ. of Washington, Seattle, WA
23.6S
 Application-Specific
M emory
Management
f or
E mbedded
S ystems
Using
S oftware-Controlled
C aches
Derek Chiou, Prabhat Jain, Srinivas Devadas,
L a rry Rudolph - Massachusetts Institute of Te c h n o l o g y,
Cambridge, MA
Session 24
Wednesday, June 7
ROOM:
 408B
DESIGNING
 SYSTEMS
ON
 A
 CHIP
CHAIR: Randolph
 E.
 Harr -
 Synopsys,
Inc.,
 Mountain
 View,
 CA
ORGANIZERS: Kurt
 Keutzer,
 Asawaree
Kalavade
This session begins with a tutorial
overview of tools and methodologies being
put in place at IBM to support a corebased
approach to the design of systemson-a-chip.
Topics covered will include
interconnect and communication, core
implementation, interface synthesis, and
verification. The remaining two papers will
go into detail on methodologies for
design verification and manufacture
test respectively.
24.1 EMBEDDED
 TUTORIAL:
Designing
Systems-on-a-chip
Using
 Cores
Reinaldo Bergamaschi - IBM Corp., Yorktown
Heights, NY
William Lee - IBM Microelectronics, Research
Triangle Park, NC
24.2 Verification
 of
 Configurable
Processor
 Cores
Marines Puig-Medina, Gulbin Ezer, Pavlos
Konas - Tensilica, Santa Clara, CA
24.3 Design
 of
 System-on-a-Chip
Test
 Access
 Architectures
 under
Place-and-Route
 and
 Power
Constraints
Krishnendu Chakrabarty - Duke Univ.,
Durham, NC
Session 25
ROOM:
 403
PANEL:
 THE
 FUTURE
 OF
SYSTEM
 DESIGN
LANGUAGES
CHAIR: Richard
 Goering
 -
 EE
 Times,
Felton,
 CA
ORGANIZERS: Nanette
 Collins,
 Clifford
 E.
Cummings,
 Richard
 Goering
Verilog HDL was a breakthrough for the
hardware design community in 1986. Over
the years, the methodology based on the
Verilog HDL has been extended with
utilities and enhancements. With 0.25and
0.18- processes enabling a system to
be packed onto a single integrated circuit
(IC), design problems have surfaced that no
one could have predicted 13 years ago. As a
result, several new design language
proposals have been introduced since the
last Design Automation Conference (DAC),
all claiming to aid system-on-chip (SOC)
design. Several claim to improve the
d e s i g n e r’s ability to efficiently create,
implement, and verify SOC designs from
architectural specification through functional
implementation. The panel, comprised of
experienced designers and representatives
of organizations submitting design language
proposals, will debate the various proposals
and will try to identify what future trend will
accelerate system design.
PANELISTS:
Clifford
 E.
 Cummings -
 Sunburst
Design,
 Beaverton,
 OR
Simon
 Davidmann -
 Co-Design
Automation,
 San
 Jose,
 CA
Joachim
 Kunkel -
 Synopsys,
 Inc.,
Mountain
 View,
 C
A
Oz
 Levia
 -
 Improv,
 Santa
 Clara,
 CA
John
 Sanguinetti -
 CynApps,
 Santa
Clara,
 CA
Steven
 E.
 Schulz -
 Texas
 Instruments,
Dallas,
 TX
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short
 paper
Wednesday, June 6
Session 26
ROOM:
 404AB
MIXED
 SIGNAL
 DESIGN
 AND
ANALYSIS
CHAIR: Mojy
 C.
 Chian -
 Conexant
 Systems
 Inc.,
Newport
 Beach,
 CA
ORGANIZERS: Ingrid
 Verbauwhede,
 David
 Blaauw
With the explosion of the telecommunication market,
there is an over increasing trend to integrate more
functionality on one single chip. The papers in this
session demonstrate enabling technologies in
support of this trend. The first paper presents an
efficient simulation techniques for digital telecom
transceivers. The second paper demonstrates a
cell-based techniques for substrate and power
supply noise analysis. The third paper reports on the
design methodology and trade-offs for the
implementation of a 14-bit D/A Converter.
26.1 A
 Methodology
 for
 Efficient
 High-Level
Dataflow
 Simulation
 of
 Mixed-Signal
 Front-
Ends
 of
 Digital
 Telecom
 Transceivers
Gerd Vandersteen, Piet Wambacq - IMEC, Leuven, Belgium
Yves Rolain - VUB, Brussels, Belgium
Petr Dobrovolny, Stephane Donnay, Marc Engels, Ivo Bolsens -
IMEC, Leuven, Belgium
26.2 High-Level
 Simulation
 of
 Substrate
Noise
 Generation
 Including
 Power
 Supply
Noise
 Coupling
Marc van Heijningen, Mustafa Badaroglu, Stephane Donnay,
Marc Engels, Ivo Bolsens - IMEC, Leuven, Belgium
26.3 DESIGN CONTEST: Systematic
 Design
of
 a
 14-bit
 150-MS/S
 CMOS
 Current-Steering
D/A
 Converter
Geert Van der Plas, Jan Vandenbussche, Walter Daems, Anne
Van Den Bosch, Georges Gielen, Michiel Steyaert, Willy Sansen -
Katholieke Univ., Leuven, Belgium
Session 27
ROOM:
 408A
FLOORPLANNING
 &
 PLACEMENT
CHAIR: Louis
 Scheffer -
 Cadence
 Design
 Systems,
Inc.,
 San
 Jose,
 CA
ORGANIZERS: Patrick
 Groeneveld,
 Lou
 Scheffer
Two critical tasks in chip design are the construction
of an appropriate floorplan and the detailed
placement of each component. This session starts
with a new data structure for floorplanning, followed
by a new technique for enforcing symmetry
constraints and a new aspect ratio optimization. The
last two papers implement detailed placement by
partitioning, while trying to control both timing and
routing congestion.
27.1 B*-Trees:
 A
 New
 Representation
 for
Non-Slicing
 Floorplans
 with
 Hard/Pre-
Placed/Soft
 Modules
Yun-Chih Chang, Su-Wei Wu - National Chiao Tung Univ.,
Hsinchu, Taiwan, ROC
Ya o - Wen Chang - National Chiao Tung Univ., Hsinchu, Taiwan ROC
27.2S Block
 Placement
 with
 Symmetry
Constraints
 Based
 on
 the
 O-Tree
 Non-Slicing
Representation
Yingxin Pang - Univ. of California at San Diego, La Jolla, CA
Florin Balasa, Koen Lampaert - Conexant Systems, Inc.,
Newport Beach, CA
Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
27.3S Floorplan
 Sizing
 by
 Linear
Programming
Approximation
Pinhong Chen, Ernest S. Kuh - Univ. of California, Berkeley, CA
27.4S Timing-Driven
 Placement
 Based
 on
Partitioning
 with
 Dynamic
 Cut-Net
 Control
Shihg-Liang Ou, Massoud Pedram - Univ. of Southern
California, Los Angeles, CA
27.5S Can
 Recursive
 Bisection
 Alone
Produce
 Routable
 Placements?
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov - Univ.
of California, Los Angeles, CA
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 28
ROOM:
 406AB
SYSTEM
 LEVEL
SCHEDULING
CHAIR: Erwin
de 
Koc k -
Phi lips
Res earch
Labs.,
 Eindhoven,
 The
 Netherlands
ORGANIZERS: Kees
V issers,
 John
G lossner
An important part of system software is
the task-scheduling approach. In this
session the subject of finding priorities
under real-time constraints is addressed,
in the context of a real-time operating
system. Furthermore a novel technique
for addressing the scheduling problems
at this level will be presented. Also an
approach is presented that indicates
where reductions should be made in
execution times of tasks.
28.1 Task
 Scheduling
 with
 RT
Constraints
Marco di Natale - Universita’ Degli Studi di
Pisa, Pisa, Italy
Alberto L. Sangiovanni-Vincentelli - Univ. of
California, Berkeley, CA
Felice Balarin - Cadence Berkeley Labs., Berkeley, CA
28.2 Task
 Generation
 and
Compile-Time
 Scheduling
 for
 Mixed
Data-Control
 Embedded
 Software
Jordi Cortadella - Univ. Politecnica de Catalunya,
Barcelona, Spain
Alex Kondratyev - Univ. of Aizu, Fukushima, Japan
Luciano Lavagno - Univ. di Udine, Udine, Italy
M a rc Massot - Univ. de Girona, Girona, Spain
Sandra Moral - Univ. Politecnica de Cataluny,
Barcelona, Spain
Claudio Passerone - Politecnico di Torino,
Torino, Italy
Yosinori Watanabe - Cadence European Labs.,
Roma, Italy
Alberto L. Sangiovanni-Vincentelli - Univ. of
California, Berkeley, CA
28.3 Schedulability-Driven
Performance
 Analysis
 of
 Multiple
Mode
E mbedded
R eal-Time
S ystems
Youngsoo Shin, Daehong Kim - Seoul National
Univ., Seoul, Korea
Session 29
Wednesday, June 6
ROOM:
 408B
ARCHITECTURES
 FOR
EMBEDDED
 SYSTEMS
CHAIR: Kees
 A.
 Vissers -
 Univ.
 of
California,
 Berkeley,
 CA
ORGANIZERS: Donatella
 Scuito,
Rajesh
 Gupta
Selection of an appropriate architecture
is an important design decision for
embedded systems. Papers in this
session address architectural choices
and organization of embedded systems
using reconfigurable hardware. Last
paper proposes a new technique for
design of communication functions for
embedded systems on a chip.
29.1 System
 Design
 of
 Active
Basestations
 Based
 on
Dynamically
Reconfigurable
Hardware
Athanassios Boulis, Mani B. Srivastava - Univ.
of California, Los Angeles, CA
29.2 Hardware-Software
Co-
Design
 of
 Embedded
Reconfigurable
Architectures
Yanbing Li - Synopsys, Inc., Mountain View, CA
Tim Callahan - Univ. of California, Berkeley, CA
Ervan Darnell - Silicon Spice, Mountain Vi e w, CA
Randolph E. Harr, Uday Kurkure, Jon Stockwood -
Synopsys, Inc., Mountain View, CA
29.3 Communication
Architecture
Tuners:
 A
 Methodology
 for
 the
Design
 of
 High
 Performance
Communication
 Architectures
 for
System-on-Chips
Kanishka Lahiri - Univ. of California at San
Diego, La Jolla, CA
Anand Raghunathan, Lakshminarayana Ganesh -
NEC USA, C&C Research Labs, Princeton, NJ
Sujit Dey - Univ. of California at San Diego, La
Jolla, CA
Session 30
ROOM:
 403
PANEL:
 EMBEDDED
SYSTEMS
 EDUCATION
CHAIR: Alberto
 L.
 Sangiovanni-
Vincentelli -
 Univ.
 of
California,
 Berkeley,
 CA
ORGANIZERS: Sharad
M alik,
J an
R abaey,
Asawaree
 Kalavade
The design and design automation of
embedded systems is rapidly emerging as a
research area in its own right. It draws from
several traditional areas of study such
as system specification, modeling and
analysis; computer architecture and
microarchitecture, as well as compilers and
operating systems. However, the embedded
domain adds some interesting twists in terms
of tighter problem constraints that demand a
fresh look at even these traditional areas. In
addition, there are several emerging EDA
areas such as design reuse and integration of
systems on a chip that are critical to the study
of embedded systems. All these aspects are
not typically covered by computer engineering
and EDA curricula. This panel addresses the
challenges associated with the educational
issues in embedded systems design and
design automation. The panelists will examine
issues in including embedded systems in
university curricula, as well as in setting up
research programs that are crucial for the
education of graduate students.
The panel of distinguished members have all
grappled with these issues and will share their
experiences in setting up various programs,
as well as point out changes we should be
looking at for the future.
PANELISTS:
Edward
 Lee
 -
 Univ.
 of
 California,
Berkeley,
 CA
Phil
 Koopman
 -
 Carnegie
 Mellon
 Univ.,
Pittsburgh,
 PA
Alberto
 L.
 Sangiovanni-Vincentelli -
Univ.
 of
 California,
 Berkeley,
 CA
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 speakers
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 denotes
short
 paper
Thursday, June 8
Session 31
ROOM:
 404AB
INTERCONNECT
ANALYSIS
CHAIR: David
 D.
 Ling -
 IBM
 Corp.,
 Yorktown
Heights,
 NY
ORGANIZERS: Joel
 Phillips,
 Alan
 Mantooth
This session features efficient methods for modeling
interconnnect. The first two papers discuss new
model reduction approaches, the third, closed-form
models for coupling noise, and the fourth, compact
discretizations for capacitance extraction.
31.1 Passive
 Model
 Order
 Reduction
Algorithm
 Based
 on
 Chebyshev
 Expansion
 of
Impulse
 Response
 of
 Interconnect
Networks
Janet Meiling Wang - Univ. of California, Berkeley, CA
31.2 Passive
 Model
 Order
 Reduction
 of
Multiport
 Distributed
 Interconnects
Emad Gad, Anestis Dounavis, Michel Nakhla, Ramachandra
Achar - Carleton Univ., Ottawa, ON, Canada
31.3S Predicting
 Coupled
 Noise
 in
 RC
Circuits
 by
 Matching
 1,
 2,
 and
 3
 Moments
Bernard N. Sheehan - Mentor Graphics Corp., St. Paul, MN
31.4S Singularity-Treated
Quadrature-
Evaluated
 Method
 of
 Moments
 Solver
 for
3-D
 Capacitance
 Extraction
Jinsong Zhao - Cadence Design Systems, Inc., San Jose, CA
Session 32
ROOM:
 408A
HIGH
 LEVEL
 SYNTHESIS
 FOR
DSPs: DATA
 INTENSIVE
APPLICATIONS
CHAIR: Nikil
D .
 Dutt -
U niv.
o f
Ca lifornia,
I rvine,
C A
ORGANIZERS: Rajesh
 K.
 Gupta,
 Kazutoshi
Wakabayashi
Papers in this session address synthesis and
optimization techniques for DSP and memory
intensive applications. The first and the last papers
address memory organization to minimize latency
and bandwidth effects. The second paper proposes
an improvement over latency bounding techniques
for DFGs. The third paper in this session looks at
interface generation from data flow graphs.
32.1 Optimal
 Two
 Level
 Partitioning
 and
Loop
 Scheduling
 for
 Hiding
 Memory
 Latency
for
 DSP
 Applications
Zhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha -
Univ. of Notre Dame, Notre Dame, IN
32.2 On
 Lower
 Bounds
 for
 Scheduling
Problems
 in
 High-Level
 Synthesis
M. Narasimhan, J. Ramanujam - Louisiana State Univ.,
Baton Rouge, LA
32.3S Efficient
 Building
 Block
 Based
 RTL-
HDL
 Code
 Generation
 from
 Synchronous
Data-Flow
 Graphs
Jens Horstmannshoff, Heinrich Meyr- Integrated Signal
Processing System, RWTH Aachen, Germany
32.4S High-Level
 Memory
 Mapping
Exploration
 for
 Dynamically
 Allocated
 Data
Structures
Peeter Ellervee - KTH, Kista, Sweden
Miguel Miranda, Francky Catthoor - IMEC, Leuven, Belgium
Ahmed Hemani - KTH, Kista, Sweden
*
 Please
 be
 advised
t hat
 the
 two
Ke ynotes
 and
 some
 of
t he
T echnical
S essions
 will
b e
video
t aped
 during
 the
c onference.
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 33
ROOM:
 406AB
EMBEDDED
 TUTORIAL:
MOSFET
 MODELING
 AND
CIRCUIT
 DESIGN:
RE-ESTABLISHING
 A
LOST
 CONNECTION
CHAIR:
 Brian
 Mulvaney -
 Motorola,
Inc.,
 Austin,
 TX
ORGANIZER: Daniel
 Foty
Amid the blizzard of design-automation
technologies, the analytical MOSFET m o d e l s
(and their associated model parameter sets)
receive scant attention from the design
c o m m u n i t y. However, these models and
parameter sets are fundamental to the design
process, since they represent the critical
"communication link" between a design group
and its wafer foundry.
The first part of this tutorial will examine the
present "infrastructure" of MOS modeling for
circuit simulation, with particular emphasis on
how history has played a role at least as large
as that of engineering. The viewpoint will be
that of a circuit design "consumer" of MOS
models who must make the best possible use
of a badly flawed infrastructure. In recent
years, the entire structure of MOS models has
been evolving into continually more
complicated and empirical forms, opening up a
"reality gap" between a model's mathematical
structure and circuit design usage.
The second part of this tutorial will
demonstrate the connection between
M O S F E T modeling and a modern approach to
designing analog and digital integrated circuits.
A methodology is presented is which permits
M O S F E T sizing for optimal bandwidth, optimal
dc matching, balanced compromises in
bandwidth and dc matching, and other
combinations of circuit performance. T h e
methodology permits operation anywhere in
the continuum of MOSFET operation through
weak, moderate, and strong inversion. T h e
methodology is particularly compatible with the
EKV MOSFET model, as will be shown.
PRESENTERS:
David
B inkley
 -
 Concorde
 Microsystems,
Knoxville,
 TN
Daniel
 Foty
 -
 Gilgamesh
 Associates,
Fletcher,
 VT
Session 34
ROOM:
 408B
RECONFIGURABLE
COMPUTING
 SYSTEMS
Thursday, June 8
CHAIR: Telle
 Whitney - Malleable
Technologies,
 San
 Jose,
 CA
ORGANIZERS: Telle
 Whitney,
 Ingrid
Verbauwhede
Reconfigurable computing systems
provide a platform for a vast array of
attractive applications. The session
opens with a novel FPGA d e s i g n
environment. The second paper
proposes a metric for FPGA placement
and routing. The session closes with a
case study of a reconfigurable system.
34.1 Using
General-Purpose
Programming
 Languages
 for
 FPGA
Design
Brad Hutchings, Brent Nelson - Brigham Young
Univ., Provo, UT
34.2 An
Architecture-Driven
Metric
 for
 Simultaneous
Placement
 and
 Global
 Routing
 for
FPGAs
Yao-Wen Chang, Yu-Tsang Chang - National
Chiao Tung Univ., Hsinchu, Taiwan ROC
34.3 Morphosys:
 Case
 Study
 of
 a
Reconfigurable
 Computing
 System
Targeting
 Multimedia
 Applications
Hartej Singh, Guangming Lu, Ming-Hau Lee, Fadi
J. Kurdahi, Nader Bagherzadeh - Univ. of
California, Irvine, CA
Eliseu Filho - Federal Univ. of Rio de Janei, Rio de
Janeiro, Brazil
Rafael Maestre - Univ. Complutense, Madrid, Spain
Session 35
ROOM:
 403
PANEL:
 SURVIVAL
STRATEGIES
 FOR
MIXED-SIGNAL
SYSTEMS-ON-CHIP
CHAIR: Stephen
 Ohr,
 EE
 Times,
New
 York,
 NY
ORGANIZERS: Rob
 A.
 Rutenbar,
Georges
 Gielen
More and more large ASICs require analog
subsystems to interface to the real
world--to wireless and wired networks,
to sensors and transducers in
embedded applications, to electrically
complex high-speed interconnect. This is a
major problem, since these analog
subsystems break almost every assumption
we know and love about digital systems. Wi t h
respect to today's logic-centric CAD flows,
analog blocks fit poorly and abstract badly.
What is happening to help mixed-signal SoC
designers in this difficult area? And what can
we hope for here? Analog synthesis? Mixedsignal
IP? Practical reuse methodologies? Or
will we continue to design analog the oldfashioned
way – one transistor, one polygon
at a time? Our panelists offer a mix of widely
d i ffering viewpoints on this important question.
PANELISTS:
Henry
 Chang -
 Cadence
 Design
Systems,
 Inc.,
 San
 Jose,
 CA
Georges
 Gielen
 -
 Katholieke
 Univ.
Leuven,
 Leuven
 Belgium
Rudolf
 Koch -
 Infineon
 Technologies
AG,
 Munich,
 Germany
Roy
 McGuffin -
 Antrim
 Design
 Systems,
Scotts
 Valley,
 CA
K.
 C.
 Murphy -
 Pivotal
 Technologies,
Pasadena,
 CA
Rob
A .
Ru tenbar
- 
Ca rnegie
M ellon
Univ.,
P ittsburgh,
 PA
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Thursday, June 6
Session 36
ROOM:
 404AB
INTELLECTUAL
PROPERTY
PROTECTION
 &
 RE-USE
CHAIR: Kenji
 Yoshida -
 Toshiba
 Corp.,
 Kawasaki,
Japan
ORGANIZERS: Anantha
 Chandrakasan,
 Mojy
 Chian
This session addresses issues in IP protection and
reuse methodologies for the modern SoC
environments. The first two papers discuss forensic
engineering and finger printing techniques based on
graph theory approaches. The final two papers
present HW/SW IP protection and reuse
methodologies for web-based designs.
36.1 Forensic
 Engineering
 Techniques
 for
VLSI
 CAD
 Tools
David T. Liu, Jennifer L. Wong, Darko Kirovski,
Miodrag Potkonjak - Univ. of California, Los Angeles, CA
36.2 Fingerprinting
 IPs
 Using
 Constraint-
Addition:
 Approach
 and
 Graph
 Coloring
Case
 Study
Gang Qu, Miodrag Potkonjak - Univ. of California, Los Angeles, CA
36.3S Hardware/Software
 IP
 Protection
Marcello Dalpasso - Univ. of Padova, Padova, Italy
Alessandro Bogliolo - Univ. of Ferrara, Ferrara, Italy
Luca Benini - Univ. of Bologna, Bologna, Italy
36.4S A
 Web-CAD
 Methodology
 for
 IP-Core
Analysis
 and
 Simulation
Alessandro Fin, Franco Fummi - Univ. di Verona, Verona, Italy
Session 37
ROOM:
 408A
CORRECTNESS
 ISSUES
 IN
HIGH
 LEVEL
 SYNTHESIS
CHAIR: Kwang-Ting
 (Tim)
 Cheng -
 Univ.
 of
California,
 Santa
 Barbara,
 CA
ORGANIZERS: Kazutoshi
 Wakabayashi,
Rajesh
 K.
 Gupta
With the diffusion of high-level tools into practical
designs, designers continue to face problems such
as how to ensure that a high-level synthesis tool
generates a correct structure after it applies various
transformations, and to ensure the testability of the
synthesized design. This session explores answers
to these questions.
37.1 Optimizing
 Sequential
 Verification
 by
Retiming
Transformations
Gianpiero Cabodi, Stefano Quer - Politecnico di Torino,
Torino, Italy
Fabio Somenzi - Univ. of Colorado, Boulder, CO
37.2 Efficient
 Methods
 for
 Embedded
System
 Design
 Space
 Exploration
Harry Hsieh - Univ. of California, Berkeley, CA
Felice Balarin - Cadence Berkeley Labs., Berkeley, CA
Luciano Lavagno - Cadence Design Systems, Inc., Berkeley, CA
A l b e rto L. Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA
37.3 Synthesis-for-Testability
of
Controller-Datapath
 Pairs
 that
 Use
Gated
 Clocks
Mehrdad Nourani - Univ. of Texas, Richardson, TX
Joan E. Carletta - Univ. of Akron, Akron, OH
Christos A. Papachristou - Case Western Reserve Univ.,
Cleveland, OH
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 38
ROOM:
 406AB
SOC
 TEST
METHODOLOGIES
 AND
DEFECT
 MODELLING
CHAIR: Anand
 Raghunathan -
 NEC
 USA,
C&C
 Research
 Labs.,
 Princeton,
 NJ
ORGANIZERS: Anand
 Ragunathan,
Kenji
 Yoshida
The first two papers present HW and
SW based self test techniques.
targetting respectively crosstalk and
stuck-at faults in System-on-Chip
design. The last paper explains the
application of fuzzy logic to model
defects using a resistive fault model.
38.1 Self-Test
 Methodology
 for
At-Speed
 Test
 of
 Crosstalk
 in
 Chip
Interconnects
Xiaoliang Bai, Sujit Dey - Univ. of California at
San Diego, La Jolla, CA
Janusz Rajski - Mentor Graphics Corp.,
Wilsonville, OR
38.2 Embedded
 Hardware
 and
Software
Self-Testing
Methodologies
 for
 Processor
 Cores
Li Chen, Sujit Dey, Pablo Sanchez, Ying Chen -
Univ. of California at San Diego, La Jolla, CA
38.3 Modeling
 and
 Simulation
 of
Real
 Defects
 Using
 Fuzzy
 Logic
Mehrdad Nourani, Amir Attarha - Univ. of Texas,
Richardson, TX
Caro Lucas - The Univ. of Tehran, Tehran, Iran
Session 39
Thursday, June 6
ROOM:
 408B
EMBEDDED
 TUTORIAL:
BRIDGING
 THE
 GAP
BETWEEN
 FULL
 CUSTOM
AND
 ASIC
 DESIGN
CHAIR: Bryan
 D.
 Ackland -
 Bell
 Labs.
 -
Lucent
 Technologies,
H olmdel,
N J
ORGANIZER: Kurt
 Keutzer
Custom designs manufactured in .25
micron processes have routinely exceeded
speeds of 600 MHz. where ASIC designs
in the same processes may only achieve
150 MHz. The first aim of this embedded
tutorial is to identify precisely what factors
are responsible for the gap between A S I C
and custom performance. Initial studies
indicate that key factors are: preferential
processing, use of dynamic logic families,
better circuit design, elimination of
guardbanding, and generally better
attention to design at the RTL, gate, and
transistor levels. Each of the participants
will evaluate these aspects and quantify
the contribution of each aspect. Keutzer’s
talk will focus on determining the extent to
which new tools and methodologies can
close the performance gap between A S I C
and custom. Dally’s talk will focus on
looking at new custom design techniques,
that promise to continue to keep custom
design performance well ahead of that
attainable by ASIC techniques. Finally the
two presentations will be critiqued and
reviewed by a small panel of designers and
CAD tool developers.
3
9
.
1 Closing
t he
G ap
b etween
 ASIC
and
C ustom:
 An
 ASIC P
e
r
s
p
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c
t
i
v
e
Kurt Keutzer - Univ. of California, Berkeley, CA
39.2 Closing
t he
G ap
b etween
 ASIC
and
C ustom:
 A
 Custom P
e
r
s
p
e
c
t
i
v
e
William J. Daly - Stanford Univ., Stanford, CA
39.3 Comments
 on
 Closing
 the
Gap
 between
 ASIC
 and
 Custom
Michael Keating - Synopsys, Inc., Mountain
View, CA
Udi Kra - Silicon Value, Jerusalem, Israel
Earl Killian - Tensilica, Santa Clara, CA
Martin Lefebvre - Cadabra Technologies,
Santa Clara, CA
Session 40
ROOM:
 403
PANEL:
 CASE
 STUDIES:
CHIP
 DESIGN
 ON
 THE
BLEEDING
 EDGE
CHAIR: John
 M.
 Cohn
 -
 IBM,
 Essex
Junction,
 VT
ORGANIZER: Rob
A .
 Rutenbar
Often, the most interesting tools,
methodologies, and insights come from
designs that push hard on the "leading edge"
of technology -- what the survivors
commonly call the "bleeding edge" of
design. In this session, we collect three
such on-the-edge designs, each done in
a different style, each aimed at a very diff e r e n t
market, each with its own unique set of
challenges and solutions. The session off e r s
case studies from an enormous FPGA, a
maximally high-end PC graphics engine, and
a huge system-on-a-chip for a cellular
handset. Design leads from each design
team will share some technical strategies,
some success stories, and some horror
stories in a set of introductory talks. A s h o r t
panel session at the end will allow the
audience to ask questions of all the speakers.
PANELISTS:
Luis
 Aldaz
 -
 Philips
 Semiconductors,
San
 Jose,
 CA
Chris
 Malachowsky
 -
 NVIDIA,
 Santa
Clara,
 CA
Steve
 Young -
 Xilinx,
 San
 Jose,
 CA
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Session 41
ROOM:
 404AB
LAYOUT
 OPTIMIZATION
CHAIR: Ralph
 H.J.M.
 Otten -
 Delft
 Univ.
 of
 Tech.,
Delft,
 The
 Netherlands
ORGANIZERS: Telle
 Whitney,
 Miodrag
 Potkonjak
Layout needs to be optimized to a wide variety of
objectives these days. This session presents a
sample of three widely different aspects: from device
sizing, module generation to density equalizing.
Especially the last topic, needed to enable effective
chemical-mechanical polishing, is new and
challenging issue in layout design.
41.1 Minflotransit:
 Min-Cost
 Flow
 Based
Transistor
 Sizing
 Tool
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi -
Univ. of Minnesota, Minneapolis, MN
41.2 Convex
 Delay
 Models
 for
 Transistor
Sizing
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar -
Univ. of Minnesota, Minneapolis, MN
41.3 A
 Macro-Driven
 Circuit
 Design
Methodology
 for
 Custom
 High
 Performance
Datapaths
Mahadevamurty Nemani, Vivek Tiwari - Intel Corp., Santa
Clara, CA
41.4S Model-Based
 Dummy
 Feature
Placement
 for
 Oxide
 Chemical-Mechanical
Polishing
Manufacturability
Ruiqi Tian, D. F. Wong - Univ. of Texas, Austin, TX
Robert Boone - Motorola Inc., Austin, TX
41.5S Practical
 Iterated
 Methods
 for
Layout
 Density
 Control
Yu Chen, A n d rew B. Kahng - Univ. of California, Los Angeles, CA
Alexander Zelikovsky - Georgia State Univ., Atlanta, GA
Session 42
ROOM:
 408A
DECISION
 PROCEDURES
 FOR
CAD
 PROBLEMS
CHAIR: Eugene
 Goldberg -
 Cadence
 Design
Systems,
 Inc.,
 Berkeley,
 CA
ORGANIZERS: Limor
 Fix,
 Kurt
 Keutzer
Boolean functions manipulation and boolean
satisfiability are fundamental underlying technology
in many EDA applications. A tutorial on SAT
algorithms will be presented and new variable order
and partition algorithms for BDDs will be described.
42.1 EMBEDDED
 TUTORIAL: Boolean
Satisfiability
 Models
 and
 Algorithms
 for
 EDA
Joao P. Marques Silva - Technical Univ. of Lisbon,
Lisboa, Portugal
Karem Sakallah - Univ. of Michigan, Ann Arbor, MI
42.2 Analysis
 of
 Composition,
 and
 How
 to
Obtain
 Smaller
 Canonical
 Graphs
Jawahar Jain, Dinos Moundanos - Fujitsu Labs. of America,
Sunnyvale, CA
Kartik Mohanram - Univ. of Texas, Austin, TX
Yuan Lu - Carnegie Mellon Univ., Pittsburgh, PA
42.3 Efficient
 Variable
 Ordering
 Using
Abstraction
 Based
 Sampling
 Techniques
Yuan Lu - Carnegie Mellon Univ., Pittsburgh, PA
Jawahar Jain - Fujitsu Labs. of America, Inc., Sunnyvale, CA
All
 Design
 Methods
S essions
 are
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 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 43
ROOM:
 406AB
NEW
 FRAMEWORKS
FOR
 THE
 EDA
 FIELD
CHAIR: Olivier
 R.
 Coudert -
 Monterey
Design
S ystems
I nc.,
S unnyvale,
C A
ORGANIZERS: Sharad
 Malik,
Srinivas
 Devadas
As design technology and the EDA field as a
whole mature, new frameworks for
roadmapping, measuring, and reusing the
leading edge of progress must be put in place.
This session presents four types of such
frameworks. First, a framework for an extensible,
open-source living technology roadmap is
presented. Next is a framework for composing
modular components for system simulation.
Third is a framework for instrumenting and
measuring (then improving) the design process
itself. The session closes with a panel of three
perspectives on how the web will be enabling to
R&D processes throughout EDA.
43.1 GTX:
 The
 Marco
 GSRC
Technology
 Extrapolation
 System
Andrew Caldwell, Andrew B. Kahng, Farinaz
Koushanfar, Hua Lu, Igor L. Markov, Michael R.
Oliver, D. Stroobandt - Univ. of California, Los
Angeles, CA
43.2S A
 System
 Simulation
Framework
Peter van den Hamer, Wim van der Linden,
Peter Bingley, Nico Schellingerhout - P h i l i p s
R e s e a rch Labs., Eindhoven, The Netherlands
43.3S Metrics:
 A
 System
Architecture
 for
 Design
 Process
Optimization
Andrew B. Kahng, Stefanus Mantik - Univ. of
California, Los Angeles, CA
PANEL:
 WEB-BASED
FRAMEWORKS
 TO
ENABLE
 CAD
 R&D
PANEL
 MEMBERs:
Igor L. Markov - Univ. of California, Los Angeles, CA
Arno Wagner - Univ. of Trier, Trier, Germany
Session 44
ROOM:
 408B
HIGH
 PERFORMANCE
MICROPROCESSOR
DESIGN
Thursday, June 8
CHAIR: David
 Blaauw -
 Motorola,
 Inc.,
Austin,
 TX
ORGANIZERS: Anantha
Chandrakasan,
Ralph
 Otten
This session presents design methodologies and
verification techniques for Gigahertz microprocessors.
The methodologies address a range of problems from
low-level timing verification and clock distribution to
Cache coherence protocols and multiprocessor design
verification. The use of “timing closure” by design is high
lighted. The various approaches are verified on large
commercial processors. The session also includes the
design of high performance using GaAs technology.
44.1 Timing
 Closure
 by
 Design,
 a
High
 Frequency
 Microprocessor
Design
 Methodology
Stephen Posluszny, Naoaki Aoki, Dave
Boerstler, Paula Coulman, Sang Dhong, Brian
Flachs, Peter Hofstee, Nobuo Kojima, O h s a n g
Kwon, Kyung Tek Lee - IBM Corp., Austin, TX
Dave Meltzer - IBM C o r p ., Yorktown, NY
Kevin Nowka, Jaehong Park, Jim Peter - IBM
C o r p ., Austin, TX
Joel Silberman - IBM C o r p ., Yorktown, NY
Osamu Takahashi, Paul Villarubia - IBM Corp.,
Austin, TX
44.2 Multiprocessing
Design
Verification
M ethodology
 for
 Motorola
MPC74xx
 PowerPC Microprocessor
Jen-Tien Yen, Qichao Richard Yin - Motorola
Inc., Austin, TX
44.3 A
 Methodology
 for
 Formal
Design
 of
 Hardware
 Control
 with
Application
 to
 Cache
 Coherence
Protocols
Cindy Eisner - IBM Haifa Research Lab., Haifa, Israel
Russ Hoover, Wayne Nation, Kyle L. Nelson - IBM
Corp., Rochester, MN
Irit Shitsevalov - IBM Haifa Research Lab., Haifa, Israel
Ken Valk - IBM Rochester Server Group,
Rochester, MN
44.4 DESIGN CONTEST:
CGAAS
PowerPC
 FXU
Richard B. Brown, Alan Drake - Univ. of
Michigan, Ann Arbor, MI
Session 45
ROOM:
 403
PANEL:
 WHEN
 BAD
THINGS
 HAPPEN
 TO
GOOD
 CHIPS
CHAIR: Nagaraj
 NS -
 Texas
Instruments,
 Dallas,
 TX
ORGANIZERS: Nagaraj
 NS,
S hishpal
 Rawat
45.1 EMBEDDED
 TUTORIAL: Yield
and
 Reliability
 Challenges
 in
Designing
 "Good"
 Chips
Andrzej
 Strojwas -
 Carnegie
Mellon
 Univ.,
 Pittsburgh,
 PA
Design of reliable chips with high yield is an
extremely challenging task in UDSM
technologies. Time to market pressures,
which often limit the necessary verification
before tape-out, typically are manifested as
ramp-to-production problems on "good"
designs either in the manufacturing process or
in the field. Burn-in process, a reactive
measure to ship reliable chips, is not eff e c t i v e
for high volume designs. Another cause for
concern is hidden failures that go undetected
due to incompleteness of test vectors.
This session begins with a tutorial that
examines a number of "bad things that can
happen to good chips" both during
manufacturing and in the field. The concept
of "design marginality" which can significantly
affect manufacturing yield, the proximity to
the "cliffs" in chip operation, and test escapes
that could cause failures in the field are
discussed. Then the panel, from different
perspectives on yield and reliability
challenges, will describe their own real-world
experiences, and discuss how these
challenges could be addressed in the
manufacturing process, design, and EDA.
PANELISTS:
Ray
 Hokinson -
 Compaq
 Computer
Corp.,
 Shrewsbury,
 MA
Sung-Mo
 Kang -
 Univ.
 of
 Illinois,
Urbana,
 IL
Wonjae
 Kang
 -
 Intel
 Corp.,
 Santa
Clara,
 CA
David
 Overhauser -
 Simplex
 Solutions,
Santa
 Clara,
 CA
Suni
 Nassif -
 IBM
 Corp.,
 Austin,
 TX
Tak
 Young -
 Monterey
 Design,
Mountain
 View,
 CA
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Thursday, June 8
Session 46
ROOM:
 404AB
LARGE-SCALE
PARASITIC
ANALYSIS
CHAIR:
 Alan
 Mantooth -
 Univ.
 of
 Arkansas,
Fayetteville,
 AR
ORGANIZER: Alan
 Mantooth
Methods and algorithms are presented in this
session that address large-scale parasitic analysis.
The first paper describes a method for improving the
speed of extraction and matrix sparsification for
substrate coupling. The second paper describes a
new method for capacitance calculation that
involves integrated equation formalation but that
uses charge distributions that decouple charge
variation from conductor geometry. The last paper
combines frequency and time domain techniques to
achieve performance improvements in simulation of
thermal networks.
46.1 Fast
 Methods
 for
 Extraction
 and
Sparsification
 of
 Substrate
 Coupling
Joseph D. Kanapka - Massachusetts Institute of Technology,
Cambridge, MA
Joel R. Phillips - Cadence Design Systems, Inc., San Jose, CA
Jacob K. White - Massachusetts Instittute of Te c h n o l o g y, Cambridge, MA
46.2 Large
 Scale
 Capacitance
 Calculation
Sharad Kapur, David E. Long - Bell Labs. - Lucent
Technologies, Murray Hill, NJ
46.3 Fast
 Temperature
 Calculation
 for
Transient
 Electrothermal
 Simulation
 by
Mixed
 Frequency/Time
 Domain
 Thermal
Model
 Reduction
Ching-Han Tsai, Sung-Mo (Steve) Kang - Univ. of Illinois,
Urbana, IL
Session 47
ROOM:
 408A
ADVANCES
 IN
 HIGH
 LEVEL
SYNTHESIS
CHAIR:
Kazutoshi
 Wakabayashi -
 NEC
 Corp.,
Kawasaki,
 Japan
ORGANIZERS: Rajesh
 K.
 Gupta,
 Kazutoshi
Wakabayashi
This session focuses on architectural synthesis and
optimization issues. The first paper presents a
simultaneous behavioral synthesis and physical
design flow for DFGs. The second paper proposes a
new approach for describing multi-way
synchronization protocols using a graphical
formalism. The third paper discusses optimization of
carry-save-adder representation by retiming.
47.1 Unifying
 Behavioral
 Synthesis
 and
Physical
 Design
Bill Dougherty, Donald E. Thomas - Carnegie Mellon Univ.,
Pittsburgh, PA
47.2 Hardware
 Implementation
 of
Communication
 Protocols
 Modeled
 by
Concurrent
 EFSMs
 with
 Multi-Way
Synchronization
Hisaaki Katagiri - Osaka Univ., Toyonaka, Japan
Keiichi Yasumoto - Shiga University, Hikone, Japan
Akira Kitajima - Osaka Univ., Osaka, Japan
Teruo Higashino, Kenichi Taniguchi - Osaka Univ.,
Toyonaka, Japan
47.3 Joint
 Module
 Selection
 and
 Retiming
with
 Carry-Save
 Representation
Zhan Yu - Univ. of California, Los Angeles, CA
Kei-Yong Khoo - Synopsys, Inc., Mountain View, CA
Alan N. Willson Jr. - Univ. of California, Los Angeles, CA
All
 Design
 Methods
S essions
 are
s haded
 blue,
 Embedded
S ystems
 Sessions
 are
 shaded
g rey.

Session 48
ROOM:
 406AB
FAULT
 SIMULATION
AND
 EXTRACTION
 OF
LOW-LEVEL
 EFFECTS
CHAIR:
 Thomas
 W.
 Williams -
 Synopsys,
Inc,
 Boulder,
 CO
ORGANIZERS: Tim
 Cheng,
Irith
 Pomeranz
This session features fault simulation
and extraction techniques for digital and
analog circuits taking into account lowlevel
effects. The first paper presents
fault simulation and test development
techniques for analog circuitry. T h e
second paper describes an environment
for mixed switch/RTL fault simulation.
The third paper introduces a
comprehensive fault representation
mechanism and a fault simulation
procedure for it. The fourth paper
presents an efficient extraction method
for bridging faults.
48.1 Closing
 the
 Gap
 Between
Analog
 and
 Digital
 Testing
Khaled Saab, Naim Ben Hamida, Bozena
K a m i n s k a - Fluence Technology Inc., Beaverton, OR
48.2 A
 Switch
 Level
 Fault
Simulation
Environment
Venkatram Krishnaswamy, Jeremy Casas,
Thomas Tetzlaff - Intel Corp., Hillsboro, OR
48.3S Universal
 Fault
 Simulation
Using
 Tuple
 Faults
Kumar Dwarakanath, Shawn Blanton -
Carnegie Mellon Univ., Pittsburgh, PA
48.4S An
 Efficient
 Algorithm
 to
Extract
 Two-Node
 Bridges
Sreejit Chakravarty, Sujit Thomas Zachariah,
Carl D. Roth - Intel Corp., Santa Clara, CA
Session 49
ROOM:
 408B
LOW
 POWER
 DESIGN
TECHNIQUES
 AND
ESTIMATION
Thursday, June 8
CHAIR: Tadahiro
 Kuroda -
 Toshiba
Corp.,
 Kawasaki,
 Japan
ORGANIZERS: David
 Blaauw,
Vivek
 Tiwari
The first paper describes a control
generated clocking scheme to save
power in datapath registers and clock
drivers of sequential circuits. T h e
second paper discuses bus encoding to
reduce dynamic and static power in I/O
for memory systems.The third paper
proposes a dynamic voltage scaling
scheme and a method to modify existing
application programs for real-time multimedia
applications. The last paper
presents a functional-level power
estimation methodology for predicting
power dissipation of embedded software
at compilation time.
49.1 Power
 Minimization
 Using
Control
 Generated
 Clocks
Srikanth Rao Muro o r, Soumitra Kumar Nandy -
Indian Institute of Science, Bangalore, India
49.2 Bus
 Encoding
 for
 Low-Power
High-Performance
Memory
Systems
Naehyuck Chang, Kwanho Kim, Heonshik Shin,
Jinsung Cho - Seoul National Univ., Seoul, Korea
49.3S Run-Time
 Dynamic
 Voltage
Scaling
 with
 Software
 Feedback
Loop
f or
L ow-Power
V LSI
P
r
o
c
e
s
s
o
r
s
Seongsoo Lee, Takayasu Sakurai - Univ. of
Tokyo, Tokyo, Japan
49.4S Function-Level
Power
Estimation
 Methodology
 for
Microprocessors
Gang Qu - Univ. of California, Los Angeles, CA
Naoyuki Kawabe, Kimiyoshi Usami - Toshiba
Corp., Kawasaki, Japan
Session 50
ROOM:
 403
PANEL:
 EMERGING
 EDA
COMPANIES:
ACQUIRING
 MINDS
WANT
 TO
 KNOW
CHAIR: Dan
 Schweikert -
 Sun
Microsystems,
 Palo
 Alto,
 CA
ORGANIZER: Mike
 Murray
The EDA industry is entering its third decade
with more software suppliers than ever before,
automating smaller and smaller pieces of
the design flow. The question invariably is
whether an emerging EDA company can
remain independent and grow large enough to
rival the big EDA players. In fact, executives
managing newcomer EDA players know what it
takes to be a publicly traded company. T h e y
understand first and foremost about technology
and the ensuing design methodology challenge.
Customer support is crucial to the equation, as is
the imperative to have better software and better
integration of tool suites within a design flow.
Executives managing these emerging and much
talked about companies are colorful and
seasoned EDA veterans. They have a healthy
mix of senior-level experience, business
acumen and vision –– much like the big EDA
players –– and the intimate knowledge of the
work in the trenches which appeals to real
designers. They are pushing the envelope of
company strategy by introducing clever and
innovative ideas related to new business
models, pricing and technologies that are
currently being implemented or are working.
The panel will offer a lively and spirited debate
on the correct strategy for success.
PANELISTS:
Lorne
 Cooper
 -
 Sente,
 Inc.,
Chelmsford,
 MA
Subbu
 Gannesan
 -
 Tharas
 Systems,
Santa
 Clara,
 CA
Moshe
 Gavrielov -
 Verisity,
 Mountain
View,
 CA
Rajeev
 Madhavan
 -
 Magma
 Design
Automation,
 Cupertino,
 CA
Judy
 Owen
 -
 SiliconX,
 San
 Jose,
 CA
Y.C.(Buno)
 Pati
 -
 Numerical
Technologies,
 Inc.,
 San
 Jose,
 CA
t
e
c
h
n
i
c
a
l
p
r
o
g
r
a
m
49

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Tutorial 1 - Friday, June 9
Tutorials
 will
 be
 held
 at
 the
 Los
 Angeles
 Convention
 Center
 in
 the
 Second
 Level
 meeting
rooms.
8:00
 AM
 -
Tu torial
 Registration
 Opens
 (Second
 Level) 12:00
 Noon
- 
L unch
8:30
 AM
 -
 Continental
 Breakfast
 5:00
 PM
 -
 Tutorials
 End
9:00
 AM
 -
 Tutorials
 Begin
THE
 QUEST
 FOR
 SYNTHESIS
 AND
 LAYOUT
 TIMING
 CLOSURE
Organizers: Jason
 Cong -
 Univ.
 of
 California,
 Los
 Angeles,
 CA
Patrick
 Groeneveld -
 Magma
 Design
 Automation,
 Inc.,
 Cupertino,
 CA
Presenters:
Jason
 Cong -
 University
 of
 California,
 Los
 Angeles,
 CA
Olivier
 Coudert -
 Monterey
 Design
 Systems,
 Inc.,
 Sunnyvale,
 CA
Anthony
 Drumm -
 IBM
 Corp.,
 Rochester,
 MN
Patrick
 Groeneveld
 -
 Magma
 Design
 Automation,
 Cupertino,
 CA
Audience: Logic
 designers,
 layout
 designers
 and
 CAD
 engineers
 would
 benefit
 from
 understanding
new
 algorithm
 and
 tool
 capabilities
 for
 achieving
 timing
 closure
 between
 synthesis
 and
 layout.
This
 tutorial
 will
 also
 help
 design
 project
 managers
 and
 academic
 researchers
 in
 understanding
 the
state-of-art
t he
s olutions
fo r
ti ming
c losure
a nd
 future
 research
 directions.
D
e
s
c
r
i
p
t
i
o
n:
 Getting
 timing
 closure
 between
 synthesis
 and
 layout
 has
 become
 the
 biggest
challenge
 in
 deep
 submicron
 chip
 design.
 The
 increasing
 significance
 of
 interconnect
 delay
 is
forcing
 a
 complete
 re-assessment
 of
 the
 traditional
 division
 between
 the
 logical
 design
 and
physical
 design
 steps.
 How
 can
 we
 bond
lo gic
 synthesis
 with
 placement
 and
 routing
 such
 that
 the
resulting
 chip
 will
 meet
 the
 original
 circuit
 timing
 specifications?
 This
 tutorial
 will
 provide
 the
latest
 answers
 to
 this
 question.
 An
 in-depth
 technical
 overview
 of
 all
 techniques
 for
 timing
 closure
will
 be
 discussed:
 new
 synthesis
 techniques,
 wire
 buffering
 for
 optimum
 speed,
 timing
 analysis
 and
clocking
 strategies,
 signal
 integrity,
 etc.
 Also,
 the
 technical
 core
 of
 a
 number
 of
 new
 design
systems
 will
 be
 presented,
 each
 operating
 in
 fundamentally
 different
 ways.
 The
 audience
 will
 be
offered
a 
s trong
i nsight
i n
 the
 fundamental
t echnical
p roblems
 and
 their
s olutions.
The
 first
 section
 will
 provide
 an
 in-depth
 review
 of
 the
 existing
 techniques
 that
 have
 been
successfully
 used
 today
 in
 designing
 high-performance
 chips.
 This
 covers
 the
 full
 "bag
 of
tricks"
 for
 timing
 correction,
 including
 buffering
 and
 manipulating
 wire
 load
 models.
 Timing
analysis
 and
 clocking
 methodologies
 will
 also
 be
 reviewed.
 The
 second
 part
 presents
 the
 new
'gain-based
 synthesis'
 method
 that
 is
 based
 on
 the
 theory
 of
 logical
 effort.
 This
 method
essentially
 fixes
 the
 gate
 delays
 before
 physical
 design,
 rather
 than
 the
 gate
 sizes.
 The
presentation
 will
 describe
 how
 delay
 can
 be
 kept
 constant
 during
 placement
 and
 routing
 and,
with
 that,
 how
 the
 timing
 closure
 problem
 can
 be
 solved.
 Various
 practical
 details
 of
 this
method
 that
 emerged
 during
 commercial
 application
 will
 also
 be
 discussed.
 The
 third
 part
introduces
 a
 new
 design
 closure
 method.
 It
 is
 based
 on
 simultaneous
 optimization
 and
 model
refinement.
 The
 placement,
 synthesis,
 timing,
 and
 routing
 engines
 suitable
 for
 this
 'spiraling
convergence'
 technique
 will
 be
 presented,
 together
 with
 the
 framework
 that
 enables
 their
interaction.
 The
 fourth
 section
 presents
 the
 latest
 approaches
 to
 global
 interconnect
 planning
and
 optimization
 at
 the
 chip-level.
 Buffer
 block
 planning
 and
 wire
 width
 planning
 can
 maximize
the
 speed
 of
 the
 long
 wires
 crossing
 the
 chip.
 New
 methods
 to
 automate
 this
 process
 with
 be
presented,
 together
 with
 more
 advanced
 methods
 for
 interconnect-centric
 designs,
 including
floorplanning
 with
 interconnect
 planning,
 combining
 partitioning
 with
 retiming,
 etc.

Tutorial 2 - Friday, June 9
STATIC
 TIMING
 ANALYSIS
 AND
 OPTIMIZATION
 FOR
 HIGH-PERFORMANCE
DIGITAL
 DESIGN
 SUCCESS
Organizers: Tim
 Burks
 -
 Magma
 Design
 Automation,
 Inc.,
 Cupertino,
 CA
David
 Blaauw
 -
 Motorola,
 Inc.,
 Austin,
 TX
Presenters:
Tim
 Burks -
 Magma
 Design
 Automation,
 Inc.,
 Cupertino,
 CA
Jacob
 Avidan -
 AmmoCore
 Technology
 Inc.,
 San
 Jose,
 CA
Chandu
 Visweswariah
 -
 IBM
 Corp.,
 Yorktown
 Heights,
 NY
Peter
 Beerel
 -
 Univ.
 of
 Southern
 California,
 Los
 Angeles,
 CA
Audience:
 This
 tutorial
 is
 intended
 for
 anyone
 with
 an
 interest
 in
 static
 timing
 analysis
techniques
 for
 verification
 and
 optimization,
 including
 system
 and
 circuit
 designers,
 CAD
engineers,
 design
 project
 managers,
 and
 researchers.
D
e
s
c
r
i
p
t
i
o
n:
 Too
 important
 to
 entrust
 to
 tools,
 but
 too
 difficult
 to
 attempt
 without
 them...
specifying
 and
 achieving
 timing
 goals
 has
 become
 a
 central
 part
 of
 the
 design
 process.

 As
timing-driven
 methodologies
 come
 online,
 it
 is
 critical
 to
 pay
 close
 attention
 to
 timing
 from
 the
beginning
 of
 the
 design
 flow.

 When
 combined
 with
 formal
 verification,
 static
 timing
 analysis
methods
 can
 verify
 the
 correct
 operation
 of
 a
 design
 more
 thoroughly
 than
 billions
 of
simulation
 cycles.

 However,
 many
 pitfalls
 and
 traps
 await
 the
 unwary
 user.

 Successful
 use
 of
static
 timing
 analysis
 requires
 a
 combination
 of
 design
 discipline,
 well-understood
 modeling
assumptions,
 and
 carefully
 chosen
 algorithms.
The
 first
 section
 of
 this
 tutorial
 will
 cover
 the
 basic
 models
 and
 algorithms
 of
 static
 timing
analysis.
 
 Topics
 will
 include
 the
 static
 analysis
 assumption,
 graph
 models
 of
 circuit
 timing,
arrival
 and
 required
 time
 calculation,
 path-tracing
 algorithms,
 multifrequency
 clocks,
 timing
models
 for
 latches
 and
 dynamic
 logic,
 algorithms
 for
 handling
 false
 and
 multicycle
 paths,
 and
algorithms
 for
 fast
 incremental
 timing
 analysis.
 
 Special
 attention
 will
 be
 given
 to
 the
 problem
of
 verifying
th at
 a
 design
 has
 been
 properly
co nstrained.
The
 second
 section
 will
 describe
 delay
 calculation
 methods
 in
 detail.
 Beginning
 with
 gate-level
 delay
models,
 the
 models
 used
 in
 current
 tools
 will
 be
 described,
 including
 table
 lookup
 models,
 operating
condition
 scaling,
 and
 the
 characterization
 process.
 
 The
 Delay
 Calculation
 Language
 (DCL)
 standard
will
 be
 presented
 and
 an
 overview
 of
 effective
 capacitance
 and
 wire
 delay
 calculation
 algorithms
 will
be
g iven.
 
A 
 discussion
o f
 limitations
 of
g ate-level
 models
 will
l ead
t o
a 
p resentation
o f
 transistorlevel
modeling
 techniques
 including
 partitioning,
 fast
 timing
 simulation,
 generation
 of
 worst-case
delays
a nd
d elay
c alculation
f or
s pecial
c ircuits
i ncluding
d omino
a nd
d ifferential
l ogic.
The
 third
 section
wi ll
 be
de voted
 to
 optimizing
 circuits
ba sed
 on
st atic
 timing
 analysis,
 implying
optimal
 sizing
 of
 gates
 and
 wires.
 Heuristic
 and
 formal
 methods
 will
 be
 compared
 and
 contrasted,
with
a n
e mphasis
on 
 the
la tter.
 
 The
co mponents
of 
a
s tate-of-the-art
s tatic
o ptimization
to ol
include
 fast
 simulation,
 time-domain
 sensitivity
 analysis,
 innovative
 problem
 formulation
 with
the
 help
 of
 a
 static
 timing
 analyzer
 and
 a
 nonlinear
 optimization
 package;
 each
 of
 these
components
 will
be 
 discussed.
 
 Limitations
an d
 methodology
 implications
wi ll
 also
 be
 addressed.
Finally,
 several
 advanced
 timing
 analysis
 topics
 will
 be
 presented.Some
 simple
 techniques
 from
asynchronous
 analysis
 will
 be
 discussed
t hat
 can
 be
u sed
 to
 verify
 system-level
 performance
 and
to
 derive
 the
 necessary
 conditions
 for
 correct
 operation
 of
 dynamic
 circuits.
 The
 effects
 of
 noise
and
 process
 variation
on 
 timing
 analysis
wi ll
 also
 be
 briefly
 discussed.
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51

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Tutorial 3 - Friday, June 9
SYSTEM
 LEVEL
 DESIGN
 WITH
 EMBEDDED
 PLATFORMS
Organizers: Kees
 Vissers
 -
 Philips
 Research
 Labs.,
 Briarcliff
 Manor,
 NY
Bart
 Kienhuis -
 Univ.
 of
 California,
 Berkeley,
 CA
Presenters:
Alberto
 L.
 Sangiovanni
 Vincentelli -
 Univ.
 of
 California,
 Berkeley,
 CA
Bart
 Kienhuis -
 Univ.
 of
 California,
 Berkeley,
 CA
Jan
 Rabaey -
 Univ.
 of
 California,
 Berkeley,
 CA
Kees
 Vissers -
 Philips
 Research
 Labs.,
 Briarcliff
 Manor,
 NY
Diederik
 Verkest -
 IMEC,
 Leuven,
 Belgium
Audience:
 This
 tutorial
 is
 intended
 for
 system
 design
 professionals,
 EDA
 professionals
 and
people
 involved
 in
 embedded
 systems.
D
e
s
c
r
i
p
t
i
o
n:
 The
 increasing
 complexity
 of
 systems
 on
 silicon
 makes
 them
 more
 costly
 to
manufacture
 and
de sign.
 
H owever,
 for
 these
sy stem
to 
b e
su ccessful
in 
t he
m arket,
th e
d esign
time,
 and
 therefore
 time
 to
 market,
 should
 shrink.
 Over
 the
 years
 we
 have
 seen
 the
 trend
 in
design
 from
 the
 transistor
 level
 to
 the
 gate
 level,
 then
 to
 the
 register
 transfer
 level,
 and
recently
 to
 the
 behavioral
 level
 in
 VHDL
 and
 Verilog.
 
 However,
 while
 Moore's
 Law
 holds,
 future
designs
 will
 have
 to
 start
 at
 even
 higher
 levels
 of
 abstraction
 in
 order
 to
 keep
 the
 design
 time
sufficiently
 short.
In
 this
 tutorial
 we
 introduce
 a
 separation
 between
 architecture
 and
 functions
 or
 applications,
followed
 by
 mapping
 the
 application
 onto
 the
 architectures
 of
 the
 embedded
 platforms.
 In
 the
morning
 session,
 we
 discuss
 trends
 in
 embedded
 systems
 and
 give
 a
 definition
 of
 platforms.
 
 We
elaborate
 on
 the
 impact
 of
 platform
 thinking
 on
 embedded
 systems
 and
 highlight
 the
 importance
 of
separation
 of
 computation
 and
 communication
 in
 embedded
 systems.
 We
 present
 the
 y-chart
methodology
 for
 designing
 systems
 using
 embedded
 platforms.
 
 In
 this
 methodology,
 sets
 of
applications
 are
 mapped
 onto
 architectures
 at
 several
 levels
 of
 abstraction.
 We
 show
 several
 models
of
 computation
 that
 play
 an
 important
 role
 in
 the
 y-chart
 methodology.
 
 We
 explain
t hese
 models,
including
 models
 for
 control
 and
 data
 flow.
 
 We
 demonstrate
 that
 the
 computation
 and
communication
 characteristics
 in
 the
 Picoradio
 research
 at
 UC
 Berkeley
 define
 the
 exploration
 space
for
n ovel
i mplementations.
W e
a lso
i llustrate
t he
n eed
f or
a nd
r ole
o f
a dvanced
s ystem
l evel
t ools.
In
 the
 afternoon
 session,
 we
 look
 at
 two
 industrial
 design
 cases
 for
 multimedia
 systems.
 In
 the
first
 design
 case,
 we
 focus
o n
 the
d esign
 and
 exploration
 of
 multimedia
 functions
 for
 a
 real-time
high-performance
 platform
 that
 consists
 of
 a
 MIPS
 core,
 a
 VLIW
 core,
 and
 several
 coprocessors.
We
 look
 at
t he
m odeling
 of
 video
 applications
 and
 at
t he
m odeling
 of
 architectures.
 We
 show
h ow
we
 map
 Kahn
 Process
 Networks
 to
 VLIW
 cores
 and
 dedicated
 coprocessors,
 and
 we
 quantify
 and
illustrate
 system
 trade-offs
 in
 terms
 of
h ardware,
 software
a nd
 communication
 costs.
T he
 design
of
 the
 data
 transfer
 mechanism
 and
 data
 storage
 organization
 in
 these
 multimedia
 applications
is
 extremely
 important
 and
 has
 a
 large
 impact
 on
 system
 performance
 and
 total
 power
consumption.
 Using
 compiler
 technology,
 we
 show
 the
 exploration
 of
 several
 memory
organizations.
 
W e
 present
 quantitative
re sults
f or
a 
 multimedia
ap plication.

Tutorial 4 - Friday, June 9
SIGNAL
 INTEGRITY
 IN
 DEEP
 SUBMICRON
 DESIGNS
Organizer: Chung-Kuan
 Cheng -
 Univ.
 of
 California,
 San
 Diego,
 CA
Presenters:
Tak
 Young -
 Monterey
 Design
 Systems
 Inc.,
 Sunnyvale,
 CA
Shen
 Lin -
 Hewlett
 Packard
 Labs.,
 Palo
 Alto,
 CA
Sanjay
 Dhar -
 Mentor
 Graphics
 Corp.,
 Wilsonville,
 Oregon
Chung-Kuan
 Cheng -
 Univ.
 of
 California,
 San
 Diego,
 CA
Audience:
 The
 tutorial
 is
 intended
 for
 system
 and
 circuit
 designers
 who
 would
 benefit
 from
understanding
 signal
 integrity
 of
 interconnect
 dominated
 designs,
 for
 CAD
 engineers
 (both
 R
 &
D
 and
 support),
 for
 design
 project
 managers,
 and
 for
 academic
 researchers.
D
e
s
c
r
i
p
t
i
o
n:In
th is
tu torial,
 we
p resent
t he
 design
fl ow
an d
 analysis
 of
 signal
i ntegrity
in 
de ep
submicron
 designs.
 We
 first
 talk
 about
 the
 RLC
 parasitic
 extraction.
 
 We
 then
 study
 the
capacitive
 and
 inductive
 effect
 with
 emphasis
 on
 inductance
 for
 high
 speed
 circuitry.
 
 Finally,
we
di scuss
 industrial
pr actices
 and
 cases
 studies.
I
n
t
r
o
d
u
c
t
i
o
n
: We
 introduce
 the
 overall
 design
 flow
 and
 fundamental
 theories
 and
 concepts
 of
RLC
 network
an alysis
 for
 interconnect
do minated
 designs.
RLC
 Extraction:
We 
 describe
 the
 parasitic
 models
 and
 the
 extraction
 techniques
of 
 interconnect
electronic
 parameters.
 
 An
 extraction
 flow
 with
 particular
 emphasis
 for
 cross-coupling
capacitance
 screening
 and
 generation
 of
 net
 delays
 for
 full
 chip
 delay
 analysis
 will
 be
 discussed.
On-Chip
 Inductance
 and
 Coupling
 Effects:
 We
 investigate
 the
 inductance
 and
 coupling
 effects
for
 high
 speed
 designs.
 
 Impacts
 of
 RLC
 power/ground
 network
 modeling
 and
 delta
 i
 noise
 are
discussed.
 Techniques
 to
 minimize
 inductance
 effects
 are
 explored.
 We
 also
 talk
 about
 our
experience
 on
te st
 chip
 modeling
 and
 measurement.
Industrial
 Practices
 and
 Case
 Studies:
 We
 address
 the
 bottlenecks
 regarding
 the
 effects
 of
coupling
 and
 the
 significant
 amount
 of
 parasitics.
 Case
 studies
 from
 different
 industrial
designs
 will
 be
 used
 to
 demonstrate
 the
 importance
 of
 interconnect
 effect
 on
 timing
 and
functional
 behavior.
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Tutorial 5 - Friday, June 9
DESIGN
 TECHNOLOGY
 FOR
 BUILDING
 WIRELESS
 SYSTEMS-ON-CHIP
Organizer: Rajesh
 Gupta -
 Univ.
 of
 California,
 Irvine,
 CA
Presenters:
Mani
 Srivastava
 -
 Univ.
 of
 California,
 Los
 Angeles,
 CA
Charles
 Chien -
 Rockwell
 Science
 Ctr.,
 Thousand
 Oaks,
 CA
Georges
 Gielen -
 Katholieke
 Univ.,
 Leuven,
 Belgium
Rajesh
 Gupta -
 Univ.
 of
 California,
 Irvine,
 CA
Audience:
 This
 tutorial
 is
 targeted
 for
 practicing
 engineers
 interested
 in
 system
 and
 IC
 design
tools
 for
 building
 wireless
 systems.
 CAD
 developers
 and
 researchers
 will
 develop
 an
 appreciation
of
 the
 design
 tool
 requirements
 for
 wireless
 networked
 computing
 systems.

 Minimal
 familiarity
with
 VLSI
 design,
 communications
 basics
 and
 computer
 programming
 is
 assumed.
D
e
s
c
r
i
p
t
i
o
n:The
 progress
 in
 IC
 technology
 is
 making
 possible
 development
 of
 chips
 that
incorporate
 all
 the
 elements
 of
 a
 complete
 wireless
 radio
 system
 on
 a
 chip
 (SOC)
 as
 a
 means
 to
obtain
 low
 system
 cost,
 ease
 of
 system
 insertion
 and
 miniaturization.
 Such
 an
 antenna-tonetwork
chip
 would
 incorporate
 an
 RF
 front
 end,
 baseband
 digital
 signal
 processing,
 link
 layer
coding
 functions
 for
 error,
 compression,
 and
 encryption,
 and
 medium
 access
 control
 and
 other
network
 protocols.
 An
 example
 of
 the
 drive
 toward
 wireless
 system
 on
 a
 chip
 is
 the
 race
 among
1000+
 design
ho uses
ar ound
 the
 world
to 
 develop
 a
 single-chip
 device
 for
 "Bluetooth."
From
 an
 implementation
 point
 of
 view,
 this
 would
 require
 integration
 of
 analog
 circuits,
 high
performance
 custom
 signal
 processing
 datapaths
 and
 cores,
 customized
 logic,
 embedded
processor,
 and
 complex
 software
 environments
 on
 the
 same
 chip
 or
 substrate.
 The
 design,
simulation,
 implementation,
an d
t esting
te chniques
 required
 for
su ch
ch ips
a re
 complex,
as 
ar e
the
 metrics
t o
 evaluate
t he
 performance.
T he
 current
e ffort
 in
s tandardization
o f
p re-designed
core
 cells
 is
 expected
 to
 play
 a
 major
 role
 in
 making
 it
 possible
 for
 designers
 to
 build
 complete
and
 customized
 wireless
 SOCs.
 However,
 the
 diversity
 of
 cores
 required
 in
 such
 systems
represents
 a
 special
 challenge
 in
 almost
 all
 aspects
 of
IC /System
 design.
In
 this
 tutorial
 we
 present
 the
 state
 of
 the
 art
 in
 designing
 such
 systems,
 focusing
 from
 a
system
p erspective,
o n
b oth
th e
CA D
pr oblems
t hat
a rise
fr om
s uch
ch ips
a s
we ll
a s
o n
th e
t ools
and
 design
 techniques.
 The
 presentation
 is
 roughly
 divided
 into
 four
 parts.
 First
 part
 covers
basics
 of
 wireless
 systems
 including
 RF,
 communication
 and
 networking
 subsystems;
representation
 and
 modeling
 of
 wireless
 system
 components
 (RF,
 baseband
 DSP,
 protocol
processing
fo r
ne twork
 interfaces)
an d
 optimization
 across
 heterogeneous
 processing
do mains.
Second
 part
 addresses
 architectural
 design
 techniques
 for
 integrated
 wireless
 systems,
particularly
 tradeoffs
 in
 a
 resource,
 power
 and
 bandwidth
 constrained
 environment.
 Third
 part
addresses
 design
 tools,
 techniques
 and
 cores
 for
 wireless
 systems
 including
 tools
 for
 software
synthesis
 and
 optimization.
 The
 last
 part
 addresses
 design
 tools
 and
 modeling
 for
 RF
 circuits.
 We
address
 the
 technology,
 circuit,
 and
 architecture
 partition
 (e.g.
 where
 to
 draw
 the
 line
 between
analog/RF
 and
 digital
 baseband
 processing)
 issues
 related
 to
 the
 integration
 of
 RF
 and
baseband
pr ocessing
on 
 the
 same
 chip.

Tutorial 6 - Friday, June 9
LOW-POWER
 SYSTEM
 DESIGN:
 APPLICATIONS,
 ARCHITECTURES,
 AND
DESIGN
METHODOLOGIES
Organizer: Anand
 Raghunathan -
 NEC
 USA
 C&C
 Research
 Labs.,
 Princeton,
 NJ
Presenters:
Anand
 Raghunathan -
 NEC
 USA
 C&C
 Research
 Labs.,
 Princeton,
 NJ
Sujit
 Dey
 -
 Univ.
 of
 California,
 San
 Diego,
 CA
Arkady
 Horak -
 Motorola
 Inc.,
 Austin,
 TX
Trevor
 Mudge -
 Univ.
 of
 Michigan,
 Ann
 Arbor,
 MI
Kaushik
 Roy -
 Purdue
 Univ.,
 West
 Lafayette,
 IN
Audience:
 This
 tutorial
 is
 intended
 for
 system
 designers
 who
 are
 involved
 in
 designing
 lowpower
and
 portable
 systems,
 developers
 of
 system-level
 or
 low-power
 design
 methodologies
and
 CAD
 tools,
 managers
 thereof,
 and
 researchers
 interested
 in
 low-power
 system
 design.
D
e
s
c
r
i
p
t
i
o
n:Advances
 in
 semiconductor
 technologies,
 and
 the
 aggressive
 time-to-market,
performance,
 and
 cost
 requirements
 have
 led
 to
 a
 paradigm
 shift
 in
 electronic
 system
 design,
with
 the
 evolution
 of
 system-level-integration
 allowing
 an
 entire
 system
 to
 be
 integrated
 on
 a
single
 chip.
 At
 the
 same
 time,
 the
 rapid
 growth
 in
 battery-driven
 systems,
 such
 as
 wireless
communication
 devices
 and
 information
 appliances,
 has
 elevated
 power
 consumption
 to
 be
 a
primary
 factor
 influencing
 system-level
 design
 decisions.
 This
 tutorial
 will
 highlight
 various
critical
 aspects
 of
 low-power
 system
 design:
 applications,
 system
 architectures,
 design
methodologies
 and
to ols,
 and
 relevant
 technology
 trends.
The
 first
 part
 of
 the
 tutorial
 will
 present
 examples
 of
 low-power
 applications
 from
 the
 wireless
communications
 domain
 and
 analyze
 the
 requirements
 imposed
 by
 application
 trends
 on
 systemlevel
architectures
 and
 design
 methodologies.
 We
 will
 then
 present
 examples
 of
 low-power
system
 architectures
 for
 such
 applications
 to
 illustrate
 current
 design
 practice.
 Examples
 of
 IP
cores
c urrently
av ailable
 in
 the
ma rket
w ill
be 
us ed
to 
il lustrate
th e
 issues
 involved
in 
 selecting
and
 designing
 with
 low-power
 system
 components.
 We
 will
 also
 present
 various
 low-power
architectural
t echniques
 that
 could
b e
e mployed
 in
e mbedded
p rocessor
 cores,
 including
 memory
organization,
 low-power
 instruction
 decoding,
 and
 controlled
 speculative
 execution.
The
 second
 part
 of
 the
 tutorial
 will
 focus
 on
 system-level
 design
 methodologies
 and
 tools
 for
power
 analysis
 and
 reduction.
 Topics
 covered
 will
 include
 system-level
 power
 estimation
 and
profiling,
 HW/SW
 partitioning
 and
 mapping
 for
 low-power,
 low-power
 embedded
 software,
 dynamic
voltage
a nd
p erformance
m anagement
s trategies,
m emory
a nd
I /O
o ptimizations,
p ower
i ssues
i n
bus
ar chitectures,
 system-level
 power
 management,
 and
 battery-friendly
sy stem
 design.
The
 third
 part
 will
 examine
 technology
 trends
 and
 their
 impact
 on
 low-power
 system
 design.
 We
will
 discuss
 trends
 in
 supply
 and
 threshold
 voltages,
 the
 increasing
 importance
 of
 managing
leakage
 power,
 and
 power
 issues
 involved
 in
 the
 integration
 of
 heterogeneous
 technologies
such
 as
lo gic
an d
DR AM,
 and
 multiple
 supply
an d
 threshold
 voltages
 on
a
si ngle
 chip.
55

56
Technical Program Committee
David
 Blaauw
Motorola,
 Inc.
7700
 W.
 Palmer
 Ln.
Bldg.
 C,
 MD:
 PL29
Austin,
 TX
 78729
512-996-7378
b
l
a
a
u
w
@
a
d
v
t
o
o
l
s
.
s
p
s
.
m
o
t
.
c
o
m
Richard
 Brown
Univ.
 of
 Michigan
Dept.
 of
 EECS,
 Rm.
 2403
1301
 Beal
 Ave.
Ann
 Arbor,
 MI
 48109-2122
(313)
 763-4207
brown@engin.umich.edu
Ivo
 Bolsens
IMEC
Kapeldreef
 75
Desics
 Division
Leuven,
 BE
 B-3001
 Belgium
32-16-281-244
bolsens@imec.be
Anantha
Chandrakasan
Massachusetts
 Inst.
of 
 Tech.
Dept.
 of
 EECS,
 Rm.
 38-107
 A
50
 Vassar
 St.
Cambridge,
 MA
 02139
617-258-7619
anantha@mtl.mit.edu
Kwang-Ting
 (Tim)
 Cheng
Univ.
 of
 California
Dept.
 of
 ECE
Santa
 Barbara,
 CA
 93106
805-893-7294
t
i
m
c
h
e
n
g
@
e
c
e
.
u
c
s
b
.
e
d
u
Mojy
 C.
 Chian
Conexant
 Systems
 Inc.
4311
 Jamboree
 Rd.
M/S-E03-301
Newport
B each,
 CA
 92660-3095
949-483-1080
mojy.chian@conexant.com
Jason
 Cong
Univ.
 of
 California
4651
 Boelter
 Hall
Dept.
 of
 CS
Los
 Angeles,
 CA
 90095
310-206-2775
cong@cs.ucla.edu
Srinivas
 Devadas
Massachusetts
 Inst.
 of
 Tech.
Lab.
 for
 CS
545
 Technology
 Sq.
Rm.
 NE43-258
Cambridge,
 MA
 02139
617-253-0454
devadas@mit.edu
Limor
 Fix
Intel
 Semiconductors
 Ltd.
Future
 CAD
 Tech.
MTM
 Industrial
 Ctr.
P.O.
 Box
 498
Haifa,
 31000
 Israel
972-4-8655256
lfix@iil.intel.com
John
 Glossner
IBM
 Corp.,
 T.J.
 Watson
 Research
Ctr.
P.O.
 Box
 218,
 Rte.
 134
M/S-29-237
Yorktown
 Heights,
 NY
 10598
914-945-2719
glossner@us.ibm.com
Patrick
 Groeneveld
Magma
D esign
A utomation,
I nc.
2
 Results
 Way
Cupertino,
 CA
 95014
408-864-2045
patrick@magma-da.com
Rajesh
 K.
 Gupta
Univ.
 of
 California
444
 CS
Dept.
 of
 Info./CS
Irvine,
 CA
 92697
949-824-8052
rgupta@ics.uci.edu
Asawaree
 Kalavade
Chair,
 Embedded
 Systems
Sub-Committee
Lucent
 Technologies
600
 Mountain
 Ave.
Rm.
 2B-239
New
 Providence,
 NJ
 07974
908-582-1711
kalavade@lucent.com
Timothy
 Y.
 Kam
Intel
 Corp.
Strategic
 CAD
 Labs.,
 JFT-102
5200
 NE
 Elam
 Young
 Pkwy.
Hillsboro,
 OR
 97124-6497
503-264-7536
tkam@ichips.intel.com
Kurt
 Keutzer
Univ.
 of
 California
Dept.
 of
 EECS
Cory
 Hall
 566
Berkeley,
 CA
 94720-1770
408-982-9446
keutzer@eecs.berkeley.edu
Andreas
 Kuehlmann
IBM
 Corp.
T.J.
 Waston
 Research
 Ctr.
P.O.
 Box
 218
Yorktown
 Heights,
 NY
 10598
914-945-3458
kuehl@austin.ibm.com
Tadahiro
 Kuroda
Toshiba
 Corp.
System
 ULSI
 Engineering
 Lab.
580-1
Ho rikawa-cho,
S aiwai-ku
Kawasaki,
 210-8520
 Japan
81-44-548-2341
t
a
d
a
h
i
r
o
.
k
u
r
o
d
a
@
t
o
s
h
i
b
a
.
c
o
.
j
p
Luciano
 Lavagno
Politecnico
 di
 Torino
Dip.
 di
 Elettronica
Corso
 Duca
 degli
 Abruzzi
 24
Torino,
 10129
 Italy
39-5644150
lavagno@uniud.it

Alan
 Mantooth
Univ.
 of
 Arkansas
Dept.
 of
 EE,
 Rm.
 BEC
 3217
Fayetteville,
 AR
 72701
501-575-4838
mantooth@engr.uark.edu
Malgorzata
Marek-Sadowska
Univ.
 of
 California
Dept.
 of
 ECE
Engineering
 I
Santa
 Barbara,
 CA
 93106
805-893-2721
mms@ece.ucsb.edu
Hidetoshi
 Onodera
Kyoto
 Univ.
Dept.
 of
 Communications/CE
Sakyo-ku
Kyoto,
 606-8501
 Japan
81-75-753-5314
onodera@kuee.kyoto-u.ac.jp
Ralph
 H.J.M.
 Otten
Delft
 Univ.
 of
 Tech.
ITS/ENS
Mekelweg
 4
Delft,
 CD
 2628
The
 Netherlands
31-15-2781600
otten@cas.et.tudelft.nl
Joel
 R.
 Phillips
Cadence
 Berkeley
 Labs.
2670
 Seely
 Rd.
MS
 11B2
San
 Jose,
 CA
 95134
408-944-7983
jrp@cadence.com
Irith
 Pomeranz
Univ.
 of
 Iowa
Dept.
 of
 ECE
205CC
Iowa
 City,
 IA
 52242
319-335-6054
irith@eng.uiowa.edu
Technical Program Committee
Miodrag
 Potkonjak
Univ.
 of
 California
3532
 Boelter
 Hall
Dept.
 of
 CS
Los
 Angeles,
 CA
 90095-1596
310-825-0790
miodrag@cs.ucla.edu
Anand
 Raghunathan
NEC
 USA,
 C&C
 Research
 Labs.
4
 Independence
 Way
Princeton,
 NJ
 08540
609-951-2967
anand@ccrl.nj.nec.com
Louis
 Scheffer
Cadence
 Design
 Systems,
 Inc.
555
 River
 Oaks
 Pkwy.
M/S-2B2
San
 Jose,
 CA
 95134
408-944-7114
lou@cadence.com
Donatella
 Sciuto
Politecnico
 di
 Milano
Dip.
 di
 Elettronica
 e
 Informazione
P.zza
 L.
 da
 Vinci
 32
Milano,
 20133
 Italy
39-2-23993662
sciuto@elet.polimi.it
Sunil
 D.
 Sherlekar
Silicon
A utomation
S ystems
L td.
3008,
 12th
 B
 Main,
 8th
 Cross
HAL
 2nd
 Stage,
 Indiranagar
Bangalore,
 560008
 India
91-80-528-1461x3005
sds@sasi.com
Vivek
 Tiwari
Intel
 Corp.
3600
 Juliette
 Ln.
M/S-SC12-603
Santa
 Clara,
 CA
 95052
408-765-0589
vivek.tiwari@intel.com
Ingrid
 Verbauwhede
Univ.
 of
 California
Dept.
 of
 EE
744
 OB
 Boelter
 Hall
P.O.
 Box
 951594
Los
 Angeles,
 CA
 90095-1594
310-794-5209
ingrid@ee.ucla.edu
Kees
 A.
 Vissers
Univ.
 of
 California
Dept.
 of
 EECS
524
 Cory
 Hall,
 #1770
Berkeley,
 CA
 94720-1770
510-643-7683
vissers@eecs.berkeley.edu
Kazutoshi
Wakabayashi
NEC
 Corp.
C&C
 Media
 Research
 Labs.
4-1-1
Miyazaki,Miyamae-ku
Kawasaki,
 216-8555
 Japan
81-44-856-2134
wakaba@ccm.cl.nec.co.jp
Telle
 Whitney
Malleable
Technologies
2880
 Zanker
 Rd.,
 Ste.
 104
San
 Jose,
 CA
 95134
408-435-7900x104
telle@malleable.com
Kenji
 Yoshida
Toshiba
 Corp.
580-1
 Horikawa-Cho
Saiwai-Ku
Kawasaki,
 210
 Japan
81
 44
 548
 2400
k
y
o
s
h
i
d
a
@
m
a
i
l
.
s
e
m
i
c
o
n
.
t
o
s
h
i
b
a
.
c
o
.
j
57

58
Technical Program Committee
Nanette
 V.
 Collins
Consultant
37
 Symphony
 Rd.,
 Unit
 A
Boston,
 MA
 02115
617-437-1822
nanette@nvc.com
Randolph
 E.
 Harr
Synopsys,
 Inc.
700
 E.
 Middlefield
 Rd.
Mountain
V iew,
CA
940 43-4033
650-584-1927
rharr@synopsys.com
William
 H.
 Joyner,
 Jr.
Semiconductor
 Research
 Corp.
P.O.
 Box
 12053
Research
 Triangle
 Park,
 NC
27709-2053
919-941-9472
joyner@src.org
Bryan
 Ackland
Lucent
 Technologies
Don
 Bouldin
Univ.
 of
 Tennessee
Panel-Sub Committee
Andrew
 B.
 Kahng
Univ.
 of
 California
Dept.
 of
 CS
3713
 Boelter
 Hall
Los
 Angeles,
 CA
 90095-1596
310-206-7073
abk@cs.ucla.edu
Mike
 Murray
Acuson
 Corp.
1220
 Charleston
 Rd.
Box
 7393,
 MS-E-1
Mountian
V iew,
 CA
9 4039-7393
650-694-5876
mikem@acuson.com
Student Design Contest Judges
Richard
 Gammack
Compaq
 Computer
 Corp.
Steven
 Maciejewski
Advanced
 Micro
 Devices
Sean
 Stetson
Texas
 Instruments
Shishpal
 S.
 Rawat
Intel
 Corp.
M/S-FM5-108
1900
 Prairie
 City
 Rd.
Folsom,
 CA
 95630
916-356-6639
shishpal.s.rawat@intel.com
Rob
 A.
 Rutenbar
Carnegie
 Mellon
 Univ.
2118
 Hammerschlag
 Hall
5000
 Forbes
 Ave.
Pittsburgh,
 PA
 15213-3890
412-268-3334
rutenbar@ece.cmu.edu
Frank
 Sweeney
Dallas
Semiconductor
John
 Wei
Intel
 Corp.

Bryan
 Ackland
Lucent
 Technologies
Bell
 Labs.
101
 Crawfords
 Corner
 Rd.
Rm.
 4E-508
Holmdel,
 NJ

 07733-1900
732-949-7248
bda@lucent.com
Deborah
 Chalmers
Cadence
D esign
 Systems,
I nc.
2655
 Seely
 Rd.
San
 Jose,
 CA

 95134
408-428-5795
debc@cadence.com
Giovanni
 DeMicheli
Stanford
 Univ.
Gates
 Computer
 Science
Bldg.,
 Rm.
 333
Stanford,
 CA

 94305-9030
650-725-3632
nanni@galileo.stanford.edu
Sue
 Drouin
Mentor
 Graphics
 Corp.
8005
 SW
 Boeckman
 Rd.
Wilsonville,
 OR

 97070-7777
503-685-1183
sue_drouin@mentorg.com
Larry
 Eberle
Synopsys,
 Inc.
700
 E.
 Middlefield
 Rd.
Mountain
 View,
 CA
 
 94043-4033
650-584-4418
leberle@synopsys.com
Exhibitor Liaison Committee
Ian
 Getreu
Synopsys,
 Inc.
19500
 NW
 Gibbs
 Dr.
Beaverton,
 OR

 97006
503-748-2137
iang@synopsys.com
Dave
 Guinther
Avant!
 Corp.
Front
 End
 Div.
101
 Billerica
 Ave.,
 Bldg.
 5
N.
 Billerica,
 MA

 01862
978-436-9909x134
daveg@chrysalis.com
Jan
 Houts
QuickLogic
 Corp.
1277
 Orleans
 Dr.
Sunnyvale,
 CA

 94089
408-990-4256
houts@quicklogic.com
Mahendra
 Jain
Sagantec
47308
 Kato
 Rd.
Fremont,
 CA
 94538
510-360-5200
mahendra@sagantec.com
William
 H.
 Joyner,
 Jr.
Semiconductor
R esearch
C orp.
PO
 Box
 12053
Research
 Triangle
P ark,
NC
 
 27709
919-941-9472
joyner@src.org
Tony
 Kasovich
Sente
 Inc.
4655
 Old
 Ironsides
 Dr.
Ste.
 370
Santa
 Clara,
 CA

 95054
408-654-5966
tkasovich@senteinc.com
Marie
 R.
 Pistilli
MP
 Associates,
 Inc.
5305
 Spine
 Rd.,
 Ste.
 A
Boulder,
 CO

 80301
303-530-4333
marie@dac.com
Gary
 Smith
Dataquest
251
 River
 Oak
 Pkwy.
San
 Jose,
 CA

 95134
408-468-8271
gary.smith@dataquest.com
Lee
 Wood
MP
 Associates,
 Inc.
5305
 Spine
 Rd.,
 Ste.
 A
Boulder,
 CO

 80301
303-530-4333
lee@dac.com
Ellen
 J.
 Yoffa
IBM
 Corp.
T.J.
 Watson
 Research
 Ctr.
PO
 Box
 218,
 Rm.
 39-153
Yorktown
 Hts.,
 NY

 10598
914-945-3270
yoffa@watson.ibm.com
59

sponsors
60
S p
Sponsorship
o n s o r s h i p
The
 37th
 Design
 Automation
 Conference
 is
 sponsored
 by
 the
 A
C
M
/
S
I
G
D
A (Association
 for
 Computing
Machinery/Special
 Interest
 Group
 on
 Design
 Automation),
 IEEE/CAS (Institute
 of
 Electrical
 and
 Electronics
Engineers/Circuits
 and
 Systems
 Society),
 and
 EDA
 Consortium (Electronic
 Design
 Automation
 Consortium).
Membership
 information
 is
 available
 on
 pages
 61
 -
 62
 or
 at
 the
 conference
 at
 the
 ACM
 and
 IEEE
 booths.
 Join
before
 registering
 and
 save.
IEEE
 Circuits
 and
 Systems
 Society
The
 IEEE
 Circuits
 and
 Systems
 (CAS)
 Society
 is
 one
 of
 the
 largest
 societies
 within
 IEEE
 and
 in
 the
 world
 devoted
to
 the
ana lysis,
 design,
 and
 applications
of 
c ircuits,
n etworks,
 and
 systems.
 It
 offers
i ts
 members
 an
 extensive
program
 of
publ ications,
 meetings
 and
 technical
 and
 educational
ac tivities,
 encouraging
 an
ac tive
 exchange
 of
information
 and
 ideas.
 The
 Society's
 peer
 reviewed
 publication
 activities
 include:
 Trans.
 on
 CAD;
 Trans.
 on
 CAS-
Part
 I
 (Fundamentals);
 Trans.
 on
 CAS-Part
 II
 (Analog
 &
 Digital
 Signal
 Processing);
 Trans.
 on
 VLSI;
 Trans.
 on
 CAS
for
 Video
 Technology;
 and
 the
 new
 Transactions
 on
 Multimedia
 which
 is
 co-sponsored
 with
 IEEE
 sister
 societies.
CAS
 also
 sponsors
 or
 co-sponsors
 a
 number
 of
 international
 conferences,
 which
 include
 the
 Design
 Automation
Conference
( DAC),
t he
I nt’l
Conf erence
on
 Computer-Aided
 Design
(I CCAD)
a nd
t he
 Int’l
 Symposium
 on
Ci rcuits
&
Systems
(I SCAS).
A
w orldwide
c omprehensive
pr ogram
of 
adv anced
 workshops
i ncluding
a
new 
s eries
on
" Emerging
Technologies
 in
 Circuits
 and
 Systems",
 as
 well
 as
 our
 continuing
 education
 short
 courses
 bring
 to
 our
 worldwide
membership
t he
la test
dev elopments
 in
c utting-edge
te chnologies
of
i nterest
to 
 industry
and
ac ademia
al ike.
The
 IEEE
C AS
 Society
 has
b een
 serving
i ts
m embership
 for
o ver
5 0
y ears
w ith
s uch
m ember
b enefits
 as:
•
 Discounts
 on
 all
 Society
 publications,
 conferences
 and
 workshops
 (including
 co-sponsored
 and
 sister
society
 publications
 and
 conferences)
•
 The
 Society
 newsletter
 which
 includes
 short
 articles
 on
 emerging
 technologies,
 society
 news
 and
 current
events
•
 Opportunities
 to
 network
 with
 peers
 and
 experts
 within
 our
 12
 focused
 committee
 meetings,
 the

 local
events
 of
 over
 60
 chapters
 and
 more
 than
 20
 annual
 conferences/workshops
•
O pportunity
t o
 read
a nd
r eview
p apers,
w rite
 articles
a nd
p articipate
 in
t he
 Society’s
 government
•
 And
 all
 the
 personal
 and
 professional
 benefits
 of
 IEEE
 membership
For
 more
 information,
 please
 contact
 the
 IEEE
 CAS
 Society.
Mail:
 IEEE
 CAS
 Society E-mail:
cas.info@ieee-cas.org
15
 W.
 Marne
 Ave. Phone:
1-219-871-0210
P.O.
 Box
 265 Web:
 http://www.ieee-cas.org
Beverly
 Shores,
 IN
 46301-0265
Free
 IEEE
 and
 CAS
 Membership
 Promotion
 at
 the
 37th
 DAC
Promo Code – XDAX00
The
 IEEE
 Circuits
 and
 Systems
 Society
 is
 offering
 free
 membership
 to
 IEEE
 and
 the
 CAS
 Society
 during
 the
 37th
DAC
 advance
 and
 on-site
 registration.
 The
 only
 stipulations
 are
 that
 you
 must
 be
 a
 first-time
 applicant
 and
join
 both
 the
 IEEE
 and
 the
 CAS
 Society.
 Please
 use
 the
 IEEE
 CAS
 Society
 membership
 application
 form
 found
 on
the
 opposite
 page.
 If
 you
 sign
 up
 for
 free
 membership,
 which
 is
 valid
 for
 the
 remainder
 of
 the
 year
 2000,
 you
may
 also
 apply
 for
 the
 conference
 reduced
 registration
 rate.
 If
 you
 choose
 to
 register
 on-site,
 you
 must
 stop
by
 the
 IEEE
 or
 CAS
 information
 booths
 to
 apply
 for
 free
 membership
 BEFORE
 you
 proceed
 to
 conference
registration.
 This
 will
 allow
 you
 to
 register
 for
 the
 conference
 at
 the
 reduced
 rate.
Note:
 If
 you
 pay
 for
 DAC
 registration
 before
 you
 apply
 for
 your
 free
 IEEE/CAS
 membership,
 you
 will
 be
 unable
 to
receive
a
r efund
f or
t he
d ifference
 between
m ember
an d
n on-member
re gistration
 fees,
a lthough
y ou
 will
 still
 be
able
t o
t ake
adv antage
o f
 all
t he
ot her
be nefits
o f
I EEE/CAS
m embership.

p
IEEE
 Circuits
 &
S ystems Membership Application
mail to: IEEE CAS Society Admin Off i c e
fax to: (219) 871-0211
15 W Marne Ave., P.O. Box 265
Beverly Shores, IN 46301
PLEASE PRINT - If last name is not family name circle first letter of family name.
First Name__________________________________Middle Initial_______
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Home Address________________________________________________
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Were you ever a member of the IEEE? ❑ Yes ❑ No Years 19___ to 19___
❑ Membership Renewal ❑ FREE Membership Offer (details on pg. 60)
(If you were a previous IEEE member the FREE offer is not valid. Please provide payment information.
* Note to FREE Applicants - Please use the promo code as your membership # on the conference registration form . )
Membership #__________________________ Grade _________________
Demographic Information Date of Birth_________________________
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Business Information Business Phone ________________________
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* IEEE Canadian Business Tax No.
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year) and The Institute are included
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Networking
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sponsors
61

S p o n s o rs h i p
Join
 ACM/SIGDA
 Benefit
 Yourself
 and
 Your
 Profession
Join
 now
 and
 SAVE!
 ACM/SIGDA
 members
 receive
 significantly
 reduced
 rates
 for
 DAC
 and
 other
 important
design
 automation
 and
 computer
 science
 conferences.
 You
 can
 join
 electronically
 by
 filling
 out
 our
 on-line
order
 form
 at
 http://www.acm.org/catalog/sigs/sigda.html or
 by
 sending
 e-mail
 to
 acmhelp@acm.org.
 If
you
 join
 now,
 you
 will
 receive
 our
 current
 conference
 Compendium
 CD-ROM
 which
 contains
 the
 proceedings
 of
the
 1998
 DAC,
 ASP-DAC,
 DATE,
 and
 ICCAD
 conferences,
 as
 well
 as
 three
 symposia.
 You
 will
 also
 receive
 the
1999
 Compendium
 CD-ROM
 when
 it
 is
 issued.
 For
 the
 latest
 conference
 scheduling
 information
 access
 our
website
at 
 h
t
t
p
:
/
/
w
w
w
.
a
c
m
.
o
r
g
/
s
i
g
d
a
.
ACM/SIGDA
 members
 gain
 other
 personal
 and
 professional
 DA
 benefits.
 They
 include
 an
 informative
 newsletter,
reduced
 rates
 on
 proceedings
 and
 individual
 conference
 CD-ROMs,
 and
 travel
 grant
 eligibility.
 Membership
 in
ACM/SIGDA
 also
 entitles
y ou
t o
 take
a dvantage
o f
t he
f ull
 array
of 
 ACM
 products
 and
s ervices,
 such
as 
T ODAES
-
ACM's
T ransactions
o n
D esign
Au tomation
o f
E lectronic
S ystems,
 and
t he
A CM
Di gital
L ibrary
- 
AC M's
o nline
l ibrary
of
 the
 ACM
 journals,
 magazines,
 and
 conference
 proceedings.
 Additional
 products
 and
 services
 include
 ACM
sponsored
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 ACM
 journals
 and
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 ACM
 Press
 Books,
 and
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 one
 or
more
 of
 the
 36
 ACM
 Special
 Interest
Gr oups.
 For
 details,
 visit
 the
 ACM
 website
 at
 h
t
t
p
:
/
/
w
w
w
.
a
c
m
.
o
r
g.
 During
the
 conference,
 please
 visit
 the
 ACM
 Booth,
 located
 near
 the
 registration
 area,
 and
t he
 University
 Booth
 on
 the
exhibition
f loor.
S ee
pa ge
2 1
f or
i nformation
a bout
t he
P h.D
F orum/SIGDA
M ember
 Meeting.
SIGDA/DAC
 University
 Booth
Each
 year
 SIGDA
 organizes
 the
 University
 Booth.
 The
 booth
 is
 an
 opportunity
 for
 university
 researchers
 to
display
 their
 results
 and
 to
 interact
 with
 visitors
 from
 industry.
 Priority
 is
 given
 to
 presentations
 that
complement
 the
 conference
 technical
 program.
 Demos
 that
 highlight
 benchmark
 results
 are
 also
 encouraged.
The
 Design
 Contest
 winners
 will
 give
 demonstrations
 presenting
 their
 designs
 at
 the
 University
 Booth,
Tuesday,
 12:00PM
 -
 2:00PM.
 The
 schedule
 of
 presentations
 will
 be
 published
 at
 the
 conference
 and
 will
 also
be
 available
 on
 the
 SIGDA
 website.
 We
 thank
 the
 Design
 Automation
 Conference
 for
 its
 continued
 support
of
 this
 project.
EDA
 Consortium
 (EDAC)
Formed
 in
 1989
 the
 EDA Consortium
 is
 an
 international
 association
 of
 companies
 engaged
 in
 the
development,
m anufacture,
 and
 sale
 of
 design
 tools
a nd
s ervices
 to
t he
 electronic
e ngineering
 community.
The
 Consortium
 Enhances
 the
 EDA
 Industry’s
 Efficiency
 and
 Perceived
 Value
 by:
• Leading
 forums
 to
 discuss
 industry
 issues
• Maintaining
 a
 centralized
 web
 site
• Sponsoring
 the
 DAC and
 DATE
 (Europe)
 conferences
• Reporting
 revenue
 data
 on
 the
 EDA market
• Recognizing
 excellence
 through:
-
 Phil
 Kaufman
 Award
-
 Design
 Acheivement
 Awards
• Supporting
 emerging
 EDA companies
Membership
 Includes
 these
 Benefits:
• Company
 listing
 and
 links
 on
 the
 Consortium
 web
 site
• Invitations
 to
 Consortium
 events
• Member
 discounts
 on:
-
 DAC
 &
 DATE
 exhibit
 spaces
-
 Market
 Statistics
 Service
 -
 the
 only
 source
 for
 quarterly
 EDA
 revenue
 data
Sponsorship
For
 more
 information,
 contact
 EDA
 Consortium,
 111
 West
 Saint
 John
 Street,
 Suite
 220,
 San
 Jose,
 CA
95113,
 Phone:
 (408)
 287-3322,
 Fax:
 (408)
 283-5283,
 E-mail:
 info@edac.org,
 Web
 site:
 www.edac.org.
sponsors
63

64
Proceedings
ACM/SIGDA
 (Association
 for
 Computing
 Machinery/Special
 Interest
 Group
 on
 Design
 Automation)
and
 the
 Design
 Automation
 Conference
 will
 jointly
 publish
 the
 proceedings
 of
 DAC'00
 on
 CD-ROM.
Papers
 can
 be
 accessed
 using
 Adobe
 Reader
 4.0
 (included
 on
 the
 CD-ROM).
 DAC
 Proceedings
 will
also
 be
 available
 on
 the
 World
 Wide
 Web
 after
 the
 conference.
A
 compendium
 CD-ROM
 containing
 the
 conference
 proceedings
 from
 the
 previous
 year
 is
 published
annually,
 beginning
 with
 the
 Compendium'94
 (containing
 DAC,
 EURO-DAC,
 and
 ICCAD).
Compendium'98
 contains
 ASP-DAC'98,
 DAC'98,
 DATE'98,
 ICCAD'98
 and
 proceedings
 from
 four
symposia
 (FPGA'98,
 ISLPED'98,
 ISPD'98,
 and
 ISSS'98.
 Compendium'99
 will
 include
 ASP-DAC'99,
DATE'99,
 DAC'99,
 ICCAD'99,
 FPGA'99,
 ISPD'99,
 ISLPED'99,
 CODES'99,
 and
 ISSS'99.
 SIGDA
conference
 proceedings
 on
 CD-ROM
 and
 Compendium
 CD-ROMs
 are
 available
 from
 ACM.
 Stop
 by
 the
ACM
 Booth
 for
 further
 information.
37th
 DAC
 Proceedings
The
 37th
 DAC
 proceedings
 will
 contain
 160
 papers,
 panels,
 and
 embedded
 tutorials.
 DAC
 is
offering
 each
 conference
 and
 student
 registrant
 the
 proceedings
 in
 both
 the
 hardbound
 edition
and
 the
 CD-ROM
 edition.

 Should
 you
 wish
 to
 purchase
 any
 additional
 copies
 you
 may
 do
 so
 at
 the
ACM
 booth
 for
 $50.00.
 After
 the
 conference,
 mail
 orders
 should
 be
 sent
 to
 ACM;
 approximate
 cost
after
 conference
 is
 $70
 for
 members,
 and
 $140
 for
 non-members

 ACM
 should
 be
 contacted
 before
placing
 your
 order
 to
 determine
 cost
 and
 availability
 of
 the
 proceedings.
 The
 address
 is:
ACM
 Order
 Department
P.O.
 Box
 11315
New
 York,
 NY

 10286-1315
1
 (800)
 342-6626

 (U.S.
 and
 Canada)
1
 (212)
 626-0500

 (all
 other
 countries)
Fax:

 1
 (212)
 944-1318
e-mail:

 orders@acm.org
TODAES
Transactions
 on
 Design
 Automation
 of
 Electronic
 Systems
 (TODAES)
TODAES
 will
 be
 your
 pulse
 in
 the
 rapidly
 changing
 field
 of
 design
 technology
 of
 electronic
 systems.
TODAES
 will
 keep
 you
 current
 in
 the
 areas
 of
 system
 design,
 high
 level
 synthesis,
 physical
 layout,
design
 verification,
 system
 reliability,
 and
 high
 performance
 circuits.
 TODAES
 subscriptions
 are
available
 in
 three
 formats:
 print
 (includes
 an
 annual
 CD-ROM),
 online,
 or
 both.
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print $34 $24 $29 $19 $165 $175
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print
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$41 $31 $35 $25 $200 $210

Los Angeles Attractions
The
s tars
o nly
co me
 out
at 
n ight
 to
e njoy
t he
m usic,
d ining,
t heatre,
s hopping,
m useums
an d
t he
culture
 of
 Los
 Angeles.
 The
e ndless
 attractions
i n
 the
 Los
A ngeles
a rea
 will
p rovide
 entertainment
and
 sumptuous
 dining
 experiences
 into
 the
 wee
 hours
 of
 the
 evening.
 
 Los
 Angeles
 is
 a
 city
 heavily
dominated
 by
 the
 "vagaries
 of
 hipness".
 In
 a
 city
 where
 the
 course
 of
 our
 cultural
 tastes
 are
conceived
 and
 given
 birth,
 drive
 to
 one
 of
 the
 many
 quaint
 or
 trendy
 restaurants,
 first
 class
theater
 productions,
 movies,
 concerts
 or
 clubs
 and
 professional
 sporting
 events.
 
 Shop
 ‘til
 you
drop,
 or
 tour
 one
 of
 the
 many
 fine
 art
 museums
 including
 the
 LA County
 and
 Getty
 Museums.
 A
short
 15
 minute
dr ive
 from
th e
do wntown
 area
 will
 take
 you
 to
th e
 breathtaking
 Santa
M onica
or
Venice
be ach
 for
 a
 sundry
of 
 outdoor
ac tivities
 and
 fine
 beach
 dining.
If
 you
 prefer
t o
v isit
 the
d owntown
c ultural
 sites,
 Little
 Tokyo
 and
O livera
 Street,
 7th
M arket
 Place
and
D odger
 Stadium
 
 are
a 
 short
 distance
f rom
t he
L os
 Angeles
C onvention
 Center.
 
A nd
 don’t
 forget
a
 Universal
 City
 tours
 or
 Mann’s
 Chinese
 Theatre
 in
 Hollywood
 where
 you
 can
 match
 your
 footprints
 to
the
 glamorous
 stars
 who
 have
 stirred
 our
 imagination
 and
 delighted
 us
 with
 their
 colorful
 escapades.
There’s
 something
 for
 everyone
 in
 Los
 Angeles.
 Please
 visit
 the
 Los
 Angeles
 web
 site
 at
www.losangeles.com
 for
 a
 complete
 listing
 of
 all
 activities
 in
 the
 area.
37th
 DAC
 Party Wednesday,
 June
 7,
 7:00PM
 -
 10:00PM
Pool
 Deck
 and
 Beer
 Garden
 (outdoors)
 at
 the
 Westin
 Bonaventure
 Hotel
Enjoy
 a
 Taste
 of
 L.A.
 and
 dancing
 at
 the
 DAC
 party
 this
 year.

 Your
 tour
 of
 local
 cuisines
 starts
on
 "Olivera
 Street"
 for
 fajitas,
 continuing
 on
 to
 "China
 Town/Little
 Tokyo"
 for
 Teriyaki
 and
wontons.

 There
 are
 pasta,
 vegetable
 and
 cheese
 selections
 as
 well
 as
 an
 antipasto
 bar.

 The
party
 includes
 dinner,
 dessert,
 drinks
 and
 dancing.

 The
 music
 will
 be
 provided
 by
 DAC
 favorite,
the
 band
 Scandal.
Guest/Family
Program
A
 $45
 registration
 fee
 will
 admit
 each
 guest
 or
 family
 member
 to
 the
 following:
1. Tuesday
 night
 Cocktail
 Party
 on
 the
 Galaxy
 Patio,
 Los
 Angeles
 Convention
 Center.
2. Wednesday
 night
 37th
 DAC
 Party
 in
 the
 Westin
 Bonaventure.
3. Use
 of
 the
 complimentary
 shuttle
 bus
 services
 between
 all
 DAC
 participating
 hotels
 and
 the
Los
 Angeles
 Convention
 Center.
4. Admission
 to
 the
 exhibit
 hall
 when
 accompanied
 by
 an
 attendee.
REGISTRATION
 for
 the
 Guest/Family
 Program
 will
 be
 at
 the
 Conference
 Registration
 desk
 on
Sunday,
 June
 4
 through
 Wednesday,
 June
 7.
 A
 badge
 will
 be
 provided
 for
 each
 registered
 guest
or
 family
 member.
 This
 badge
 must
 be
 worn
 to
 participate
 in
 the
 above
 activities.
 Look
 for
 the
Guest
 Registration
 sign
 in
 the
 registration
 area.
 Children
 under
 the
 age
 of
 14
 are
 not
 allowed
 in
the
 exhibit
 hall
 or
 demo
 suite
 area.
Weather
Los
 Angeles
 weather
 conditions
 in
 June
 are
 quite
 pleasant.

 It
 is
 usually
 overcast
 in
 the
 morning,
dissipating
b y
N oon.
I t
i s
n ot
ho t
-
t emperatures
a re
in 
th e
 mid
t o
h igh
 70's
F, 
lo ws
in 
th e
60 's
F.
There
 is
 very
 little
 precipitation
 and
 sometimes
 it
 is
 a
 bit
 humid.

 Santa
 Ana
 conditions
 (wind)
 do
not
 usually
 occur
 in
 June.

 Attire
 is
 casual
 for
 most
 events
 and
 restaurants.
65

t
r
a
n
s
p
o
r
t
a
t
i
o
n
66
Busing
Conference
 Shuttle
 Bus
 Service - Complimentary
 shuttle
b us
s ervice
 is
p rovided
f or
a ll
DAC
 registered
 conference
 attendees,
 exhibitors,
 and
 guest
 program
 participants.
 Day
 and
Evening
 Route
 busing
 will
 be
 provided
 to
 and
 from
 the
 Los
 Angeles
 Convention
 Center
 and
 all
participating
 DAC
 hotels.
 Hours
 will
 be
 extended
 to
 accommodate
 the
 DAC
 Demo
 Suite
 attendees.
Wednesday
 Night
 Party
 -
 At
 7:00
 PM
 Wednesday
 night
 the
 buses
 will
 run
 from

 all
 DAC
hotels
 to
 the
 Westin
 Bonaventure
 until
 1:00
 AM.
Day
 Route
 Schedule (service
 every
 10-15
 minutes)
Sunday,
 June
 4 2:00
 PM
 -


 6:30
 PM
Monday,
 June
 5 7:00
 AM
 - 11:00
 PM
Tuesday,
 June
 6 7:00
 AM
 - 11:00
 PM
Wednesday,
 June
 7 7:00
 AM
 - 1:00
 AM
Thursday,
 June
 8 7:00
 AM
 -


 7:00
 PM
Busing
 Routes
 and
 Designated
 Stops
ROUTE
 1 PICK-UP
 LOCATION
Westin
 Bonaventure
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.Figueroa
 Street
 Entrance
Los
 Angeles
 Marriott
 Downtown 
.
.
.
.
.
.
.
.At
 the
 Westin
 Bonaventure
ROUTE
 2
Holiday
 Inn
 City
 Center 
.
.
.
.
.
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.Front
 Entrance
 -
 Curbside
Holiday
 Inn
 Downtown 
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.Garland
 Street
 -
 Opposite
 Sidewalk
Best
 Western
 Mayfair 
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.Front
 Entrance
 -
 Curbside
ROUTE
 3
Los
 Angeles
 Athletic
 Club 
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.Olive
 Street
 -
 Curbside
Regal
 Biltmore
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.Grand
 Avenue
Wyndham
 Checkers
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.At
 the
 Regal
 Biltmore
ROUTE
 4
Kawada 
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.2nd
 Street
 -
 Passenger
 Zone
New
 Otani
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.Los
 Angeles
 Street
 -
 Front
 Bus
 Zone
Miyako
 Hotel
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.Front
 Entrance
 -
 Curbside
Hotel
Inter-Continental
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.Front
 Entrance
 -
 Curbside
ROUTE
 5
Wilshire
 Grand 
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.7th
 Street
 Entrance
Hyatt
 Regency
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.Hope
 Street
 -
 Curbside
ROUTE
 6
Radisson
 Midtown 
.
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.Front
 Entrance
ROUTE
 7
Wilshire
 Royale 
.
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.Front
 Entrance
 on
 Wilshire
 Blvd.
Radisson
 Wilshire
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.Front
 Entrance
 on
 Wilshire
 Blvd.

Air Transportation/Rental Cars
A
 5%
 discount
 off
 the
 lowest
 applicable
 fare
 will
 be
offered
 ONLY
 when
 you
 or
 your
 travel
 agent
 call
 United’s
 toll-free
 number
 1-800-521-4041
 and
refer
 to
 the
 Meeting
 ID
 Number
 5
4
3
Z
L.
 A
 10%
 discount
 off
 the
 unrestricted
 mid-week
 coach
fares
 is
 available
 when
 purchased
 7
 days
 in
 advance.
 An
 additional
 5%
 discount
 will
 apply
when
 you
 purchase
 your
 tickets
 at
 least
 60
 days
 in
 advance
 of
 your
 travel
 date.
 D
i
s
c
o
u
n
t
s
apply
o n
U nited,
 Shuttle
b y
 United,
a nd
 United
 Express.
 Dedicated
r eservationists
a re
o n
d uty
7
 days
 a
 week,
 7:00am
 –
 12:00
 midnight
 ET.
 Book
 early
 to
 take
 advantage
 of
 promotional
 fares
that
 give
 you
 the
 greatest
 discount.
 Mileage
 Plus
 members
 receive
 full
 credit
 for
 all
 miles
 flown
to
 this
 meeting.
T o
q ualify,
 travel
 to
 Los
A ngeles,
 CA
 (LAX)
 must
 be
 between
M ay
 27
 and
 June
13,
 2000.
 There
ar e
8
 flights
a
 day
 from
 San
 Jose
 to
 LAX
 starting
 at
 7:00AM.
You
 may
 purchase
 your
 ticket
 from
 a
 travel
 agent
 or
 by
 calling
 United
 Airlines
 personally.
Whichever
 means
 of
 ticketing
 you
 choose,
 the
 special
 DAC
 fares
 can
 only
 be
 obtained
 when
reservations
 are
 initiated
 by
 telephone
 through
 the
 toll-free
 number
 listed
 above
 using
 the
DAC code
543ZL.
Rental
 Cars
This
 year
 DAC has
 contracted
 discounted
 rates
 with
 Budget
 Car
 Rental.
 To
 receive
 this
 rate
 mention
the
D AC
r eference
# U060179
 when
m aking
 your
r eservation.
B udget
C ar
 Rental
1 -800-826-2090.
Car
 Class Daily Weekly
Compact $33 $165
Full
 Size
 4-Door $43 $215
Luxury $63 $315
Getting
 from
t he
 Airport
Super
 Shuttle
 
 can
 conveniently
 provide
transportation
 from
 the
 Los
 Angeles
International
 Airport
 to
 the
 area
 hotels.
Proceed
 to
 shuttle
 departure
 area,
 outside
Baggage
 Claim
 (lower
 level).
 Contact
 the
Super
 Shuttle
 representative
 on
 the
 center
traffic
 island
 to
 obtain
 a
 ticket.
 Return
Shuttle
 Reservations:
 1-310-782-6600.
Ticket Pricing 1 Way - $12.00
Round Trip - $24.00
Taxis
 are
 readily
 available
 from
 the
 airport
to
 the
 Los
 Angeles
 Convention
 Center
 and
should
 cost
 approximately
 $27.00.
t
r
a
n
s
p
o
r
t
a
t
i
o
n
67

h
o
u
s
i
n
g
68
Housing
Handicapped
 Access/Special
 Needs
The
 Conference
 policy
 has
 always
 been
 to
 fully
 cooperate
 with
 any
 attendee
 who
 has
 a
special
 need
 or
 requirement.
 If
 you
 have
 a
 special
 need,
 we
 ask
 that
 you
 contact
 the
 DAC
office
 at
 (303)
 530-4333
 so
 that
 we
 may
 personally
 handle
 this
 matter
 for
 you.
 If
 you
require
 special
 hotel
 accomodations,
 please
 indicate
 that
 on
 your
 hotel
 reservation
 form.
Housing
THE
 DAC
 OFFICE
 WILL
N OT
H ANDLE
 ROOM
R ESERVATIONS.
ALL
 ROOM
 RESERVATIONS
 MUST
 BE
 MADE
 DIRECTLY
 WITH
 THE
DAC HOUSING
 BUREAU/ITS.
DAC HOUSING BUREAU/ITS phone: (800) 424-5249 (US and Canada)
108 Wilmot Rd. (847) 940-2155 (International)
P.O. Box 825, Ste. 400 fax: (800) 521-6017 (US and Canada)
Deerfield, IL 60015-0825 (847) 940-2386 (International)
Sixteen
 hotels
 in
 Los
 Angeles
 are
 participating
 with
 discounted
 room
 rates
 for
 the
 37th
DAC.
 A
 hotel
 reservation
 form
 is
 on
 page
 70.
 Make
 your
 reservations
 now.
AVAILABLE HOUSING FILLS QUICKLY!
MAKE YOUR RESERVATIONS EARLY!
Reservation
 requests
 will
 be
 handled
 on
 a
 first-come
 first-served
 basis
 by
 the
 DAC
Housing
 Bureau/ITS.
 A
 deposit
 of
 $150
 payable
 to
 the
 DAC
 Housing
 Bureau/ITS
 is
required.
 Confirmations
 will
 be
 made
 by
 ITS.
 The
 special
 DAC
 rates
 will
 be
 honored
 on
 all
reservations
 made
 by
 May
 5,
 2000,
 pending
 availability.
DAC
 Housing
 Bureau/ITS
 will
 attempt
 to
 make
 your
 reservations
 as
 indicated
 by
 the
choice
 of
 hotels
 you
 specify.
 If
 the
 hotels
 you
 choose
 are
 not
 available,
 ITS
 will
 make
your
 reservation
 at
 an
 available
 Conference
 hotel.
Before
 sending
 hotel
 reservations,
 check
 availability

 on
 the
 web
 at
www.dac.com/hotav.html.
See
 page
 69
 for
 a
 map
 of
 the
 Los
 Angeles
 hotels.
N O T E : All meetings and exhibits will be at the Los Angeles Convention Center, with the
exception of the Wednesday DAC Party and Birds-of-a-Feather Meetings held at the We s t i n
B o n a v e n t u r e. All full-day tutorials will be held at the Los Angeles Convention Center.

1.
 Los
 Angeles
 Convention
Center/STAPLES
Center
3.
 The
 Westin
 Bonaventure
4.
 Wilshire
 Grand
5.
 The
 Regal
 Biltmore
6.
 Hyatt
 Regency
Los
 Angeles
7.
 Hotel
 Inter-Continental
at
 California
 Plaza
8.
 Los
 Angeles
 Marriott
9.
 Wyndham
 Checkers
 Hotel
10.
 Holiday
 Inn
 City
 Center
13.
 The
 New
 Otani
Hotel
 &
 Garden
14.
 Kawada
 Hotel
15.
 Holiday
 Inn
 L.A.
Downtown
16.
 Best
 Western
 The
Mayfair
 Hotel
17.
 The
 Los
 Angeles
Athletic
 Club
19.
 Miyako
 Inn
 &
 Spa
20.
 Shrine
 Auditorium
21.
 Exposition
 Park/CA
Science
 Center
22.
 Music
 Center
23.
 Dodger
 Stadium
24.
 Wilshire
 Royale
 HJ
25.
 Radisson
 Wilshire
 Plaza
Los Angeles Hotel Map
h
o
u
s
i
n
g
69

70
Hotel Reservation Form
Hotel reservations, changes, and cancellations are handled by DAC Housing Bureau/ITS prior to May 5, 2000. All reservations
are made on a first-come first-served basis. The following hotels are available:
Before sending hotel reservations, check availability on the web at w w w. d a c . c o m / h o t a v. h t m l.
Or call 1-847-940-2155, or 1-800-424-5249.
HOTEL RATE HOTEL RATE
(prioritize your choices) (choose one) (prioritize your choices) (choose one)
Single Double
___Best Western (The Mayfair Hotel) $108 $108
___Holiday Inn City Center $122 $135
___Holiday Inn Downtown $114 $114
___Hotel Inter-Continental $155 $155
___Hyatt Regency LA $146 $171
___Kawada $102 $102
___LA Atheletic Club $130 $130
___Marriott Downtown $140 $155
___Miyako Inn & Spa $105 $105
* (Headquarter Hotel)
Above rates honored only if your reservation is made by May 5, 2000.
The DAC Housing Bureau/ITS will attempt to make your reservations as indicated by the choice of hotel(s) you specify. If the
hotel(s) you choose are not available, the DAC Housing Bureau/ITS will make your reservation at an available Conference hotel.
R E S E RVATIONS SENT TO THE DAC OFFICE WILL BE DISCARDED!
Send deposit check or credit card information with completed form to:
Single Double
___The New Otani $135 $135
___Radisson Wilshire Plaza $135 $145
___Regal Biltmore Hotel $147 $157
___* Westin Bonaventure $146 $164
___Wilshire Grand (Standard) $138 $138
___Wilshire Grand (Deluxe) $160 $160
___Wilshire Royal HJ Plaza $105 $105
___Wyndham Checkers $149 $149
DAC Housing Bureau/ITS phone: (800) 424-5249 (US and Canada)
108 Wilmot Rd. (847) 940-2155 (International)
P.O. Box 825, Ste. 400 fax: (800) 521-6017 (US and Canada)
Deerfield, IL 60015-0825 (847) 940-2386 (International)
All reservations will be processed by mail, toll-free phone and fax. Hours of operation are 8:00A M - 5:00 P M C S T.
Name ________________________________________________________________________________________
Company ______________________________________________________________________________________
Phone __________________________________________Fax: __________________________________________
Mailing Address__________________________________________________________________________________
City __________________________________________State ____________Zip __________________________
E-mail Address __________________________________________________________________________________
Arrival Date ______________ Departure Date ______________ Sharing with ______________________________
Room Type ❏ single 1 bed ❏ double 1 bed ❏ double 2 beds ❏ triple ❏ quad ❏ ADA accessible room requested
special request (ie smoking) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _Reservations will be confirmed by the DAC/ITS Housing Bureau.
CREDIT
 CARD
 INFORMATION AMEX______Visa______MC______Discover______Diners______
Number
_______________________________________________________________________Exp.
 Date________________________
Cardholder Name ________________________________________________________________________________
(Please type or print clearly)
Cardholder Signature ____________________________________________________________________________
Your credit card will be billed a deposit in the amount of $150/room. If you prefer to guarantee by check, make check
payable to DAC Housing Bureau/ITS. Check must be in U.S. dollars drawn from a U.S. bank, wire transfers will not be
accepted. Please check DAC Housing Bureau/ITS confirmation for cancellation policies.
All changes should be processed by phone or fax with the DAC Housing Bureau/ITS until 5/5/00.
Cancellations occurring after 5/14/00 and prior to 72 hrs. of arrival date are to go directly to the hotel. Attendee will receive t h e
deposit less a $20.00 processing fee. Cancellations made less than 72 hrs. of arrival date will lose the complete deposit.

Index
About
 the
 Conference
.
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.4
Airline
Transportation 
.
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.6 7
Best
 Paper
 Awards 
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.3
Birds-of-A-Feather 
.
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. 21
Busing
.
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.
. 66
Conference
Registration
.
.
.
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.
. inside
 back
 cover
Conference
 Survey 
.
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.
.3
Convention
 Center / Hotel
 Key
 Map 
.
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.6 9
DACnet-2000 
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.
.5
Demo
 Suite
 Hours 
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. 2
Electronic
 Design
 Automation
 Liaison
 Committee
 (ELC) 
.
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.
. 59
Executive
 Committee 
.
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.
. inside
 front
 cover
Exhibit-Only 
.
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. 5
Exhibit
 Highlights 
.
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. 2
Exhibit
 Hours 
.
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.3
Exhibitor
 Listing 
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.
. 6-7
Exhibitor
 Presentation
 Matrix
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.
.8
Exhibitor
Presentations 
.
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.9 - 1 7
Free
 Monday 
.
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.2,
 5
Guest
 Program 
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.6 5
Hotel
 Reservation
 Form 
.
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. 70
Housing
 Information/Handicapped
 Access 
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.6 8
Important
 Information
 at
 a
 Glance
.
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.3
Interoperability
Workshop 
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.
. 20
Los
 Angeles
 Attractions/Weather 
.
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.
. 65
New
 to
 Conference 
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.4
Opening
 Keynote
 Address
.
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. 22
Ph.D
 Forum/SIGDA
 Member
 Meeting 
.
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.2 1
Proceedings 
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. 64
Program
 Highlights 
.
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.1
Program
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.2 4-26
Registration
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.3
Registration
Information
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. 72
Rental
 Cars 
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. 67
Society
 Membership
 Applications 
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.6 1-62
Sponsorship
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.6 0-63
Student
 Design
 Contest
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. 21
Technical
 Program
 Committee
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.5 6-58
Technical
 Sessions 
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.2 8 - 4 9
Thursday
 Keynote
 Address 
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. 23
Tutorial
Descriptions/Schedule 
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.5 0-55
Wednesday
N ight
D AC
P arty
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 .6
5
Workshop
 for
 VLSI
 Design
 Educators 
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. 19
Workshop
 for
 Women
 in
 Design
 Automation
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.1 8
i
n
d
e
x
71

72
Registration Instructions
7
 Easy
 Steps
1
. Complete
Att endee
 Information 7
. Submit
vi a
 fax,
 mail
 or
on-l ine
along
wi th
paym ent:
2
. Complete
Mem bership
 Status
3
. Complete
Tut orial/Workshop
Sel ection
4
. Complete
Regis tration
 Options
5
. Complete
Paym ent
Inf ormation
6
. Complete
Att endee
 Survey
37th
 Design
Au tomation
Conf erence
Attn:
Regis tration
Desk
5305
Spi ne
 Rd.,
 Ste.
A
Boulder,
CO
 
8030 1
TEL
#
(303)
 530-4333
FAX
#
(303)
 530-4334
FOR
INF ORMATION
ONLY, 
CALL
(800) 
 321-4573.
A
. Payment
 MUST
be
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wi th
the
reg istration
form 
 or
it 
 WILL
be
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B
. Registration
 may
 be
 charged
 to
 Visa,
 Mastercard
 or
 American
 Express.
 For
 credit
 card
 payment
 include
the
 complete
credi t
card
number, 
 expiration
date, 
 and
name
 on
the
card.
C
. If
pay ment
i s
rec eived
from 
 a
non- U.S.
bank, 
 the
att endee
 will
b e
c harged
a
 collection
 fee
of
$30.00.
D
. May
 8,
 2000,
is
the
DEADLINE to
 qualify
 for
 the
 advanced
 registration
 rate.
 Payment
 transactions
 must
be
 completed
 on
 or
 before
 May
 8,
 2000
 in
 order
 to
 receive
 the
 early
 registration
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 After
 May
 8,
2000,
 early
 registrants
 with
 incomplete
 payment
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 will
 be
 discarded
 and
 be
 required
 to
register
 at
 conference.
E
. The
 DAC
 office
 will
 continue
 to
 accept
 registrations
 until
 May
 15,
 2000,
 at
 the
 at-conference
 rate.
After
May 
 15,
 2000,
 all
regis tration
mus t
be
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at
conf erence.
F
. Register
 ONE
 person
 per
form 
 (copy
form 
 as
 needed).
G
. Refund
 Policy:
 
 Written
 requests
 for
 cancellations
 must
 be
 received
 in
 the
 DAC
 office
 by
 May
 8,
 2000,
and
 are
 subject
 to
 a
 $25.00
 processing
 fee.
 Cancellations
 received
 after
 May
 8,
 2000,
 will
 NOT
 be
honored
and
 all
regis tration
fees 
 will
 be
forf eited.
H
. Membership
number
m ust
be
inc luded
at 
ti me
 of
s ubmission
t o
recei ve
t he
members hip
rate.
No
ref unds
will
 be
 made
 for
 change
 in
 membership
 status. If
 you
 would
 like
 information
 on
 becoming
 an
 IEEE
 or
 ACM
member,
 refer
 to
 pages
 60
-
62 .
S
t
u
d
e
n
t
s
A
 special
 student
 rate
 applies
 to
 individuals
 who
 are
 members
 of
 IEEE
 or
 ACM
 and
 are
 currently
 enrolled
 in
school.
 
 Students
 who
 advance
 register
 must
 include
 a
 valid
 IEEE
 or
 ACM
 student
 membership
 number
 and
 a
valid
s tudent
I D.
 
S tudents
reg istering
 at
co nference
m ust
pres ent
a
 valid
I EEE
o r
ACM 
m embership
c ard
and
a
 Student
 ID.
 
 Student
 registration
 includes
 a
 copy
 of
 the
 proceedings;
 it
 does
 NOT
 include
 any
 social
 events.
One/Two
 Day
One/Two-Days
 Only
 registration
 includes:
 the
 day(s)
 you
 select
 for
 the
 Technical
 Conference,
 all
 three
 days
of
 the
 Exhibits
 and
 the
 proceedings
 in
 both
 the
 hard
 bound
 edition
 and
 CD-ROM.
 
 One/Two-days
 only
registration
 does
 NOT
 include
 any
 social
event s.
T
u
t
o
r
i
a
l
s
Full-day
 tutorials
 are
 offered
 on
 Friday,
 June
 9,
 2000.
 You
 must
 register
 for
 at
 least
 one
 day
 of
 the
Technical
 Conference
 to
 attend
 a
 tutorial. Tutorial
 registration
 fee
 includes:
 continental
 breakfast,
lunch,
 breaks,
and
tut orial
n otes.
S ee
 pages
50 -55
for
tut orial
desc riptions.
 
Space
i s
l imited
 to
the
fi rst
125
 persons.
 If
 your
 tutorial
 selection
 is
 filled
 and
 you
 do
 not
 indicate
 a
 second
 choice
 on
 the
 registration
form,
 we
 will
 refund
 the
 tutorial
 registration
 fee.
 For
 tutorial
 availability,
 check
 the
 DAC
 homepage
 at
w
w
w
.
d
a
c
.
c
o
m
/
t
u
t
a
v
.
h
t
m
l.
Registration
 Hours
Sunday,
 June
 4,
 2000,
 the
 registration
 desk
 will
 be
open
 from
8:00
 AM
 to
10:00
 AM,
ONLY 
f or
t hose
 wishing
to
 attend
 the
 Workshop
 for
 Women
 in
 Design
 Automation,
 the
 VLSI
 Teachers
 Workshop
 or
 the
Interoperability
 Workshop.
The
regis tration
desk
wi ll
 be
open
 to
 all
from 
 3:00
PM
to
5:00
 PM.
Register
 on
-
li ne
 at
 w
w
w
.
d
a
c
.
c
o
m
.