ALU Design 4-bit Ripple Carry Adder RCA Equations

ALU Design 

The fundamental operation of the arithmetric is 

addition. 

All others: 

Subtraction 

Multiplication 

Divison 

are implemented in terms of it. 

We need therefore an efficient implementation. 

3BA5, 11 th Lecture, M. Manzke,Page: 1 

N-bit Ripple-Carry-Adder (RCA) 

n full adders 

An n-bit ripple-carry-adder is constructed from 

n full-adders 

S = x ¯ y ¯ C in 

C out =XY + xC in +yC in 


4-bit Ripple Carry Adder 

RCA Equations 

S i = x i ¯ y i ¯ C i 

C i+1 =X i Y i + xC i +yC i 

Hence, using an AND+wired-OR and n-bit RCA 

intruduces n gate delays. 

For 64 bit calculations this is too slow 

(64 gate delays) 


3BA5, 11 th Lecture, M. Manzke,Page: 4

Carry Lookahead 

Boolean Expression 

C i+1 = x i y i + C i (x i + y i ) 

C 1 = x 0 y 0 + C 0 (x 0 + y 0 ) 

C 2 = x 1 y 1 + C 1 (x 1 + y 1 ) 

= x 1 y 1 + [x 0 y 0 + C 0 (x 0 + y 0 )](x 1 + y 1 ) 

with g i = x i y i 

p i = x i + y i 

Generate Carry 

Carry Propagate 

C i+1 = g i + p i C i 

Carry Lookahead 

Boolean Expression 

C 1 = x 0 y 0 + C 0 (x 0 + y 0 ) 

= g 0 + C 0 p 0 

C 2 = x 1 y 1 + C 1 (x 1 + y 1 ) 

= x 1 y 1 + [x 0 y 0 + C 0 (x 0 + y 0 )](x 1 + y 1 ) 

= g 1 + p 1 g 0 + p 0 p 1 C 0 

C 3 = g 2 + p 2 g 1 + p 1 p 2 g 0 + p 0 p 1 p 2 C 0 

C 4 = g 3 + p 3 g 2 + p 2 p 3 g 1 + p 1 p 2 p 3 g 0 + p 0 p 1 p 2 p 3 C 0 

C i+1 = g i + p i C i 



4-bit Carry Lookahead Adder 

C 4 Carry Block 

C 4 = g 3 + p 3 g 2 + p 2 p 3 g 1 + p 1 p 2 p 3 g 0 + p 0 p 1 p 2 p 3 C 0 



Carry Lookahaed Adder 

Groups of Input Bits 

C i+1 = g i + p i g i-1 + p i p i-1 g i-2 + … + p i p i-1 …p 0 C 0 

This requires just two gate delays: 

One to generate g i and p i 

Another to AND them 

Again we can use wired OR 

But, it requires AND gates with a fan in of n 

In practice we can only efficiently build single gates 

with a limited fan-in 

we build the lookahead circuit as a multi-level circuit 


For example, let fan-in = 4 and define: 

G i ’ A carry out is generated in the i th group of four input bits 

P i ’ A carry out is propagated by the i th group of four input bits 

G 0 ’ = g 3 + p 3 g 2 + p 2 p 3 g 1 + p 1 p 2 p 3 g 0 

P 0 ’ = p 0 p 1 p 2 p 3 

C 4 = G 0 ’ + C 0 P 0 ’ 

C 8 = G 1 ’ + P 1 ’G 0 ’ + P 0 ’P 1 ’C 0 

C 12 = G 2 ’ + P 2 ’G 1 ’ + P 1 ’P 2 ’G 0 ’ + P 0 ’P 1 ’P 2 ’C 0 


C 4 = G 0 ’ + C 0 P 0 ’ 

Genetate G’’ and Propagate P’’ 

C 8 = G 1 ’ + P 1 ’G 0 ’ + P 0 ’P 1 ’C 0 


The next level of genetate G’’ and propagate P’’ 

terms will caover 16 bits 

G’’ = G 3 ’ + P 3 ’G 2 ’ + P 3 ’P 2 ’G 1 ’ + P 3 ’P 2 ’P 1 ’G 0 

P’’ = P 3 ’P 2 ’P 1 ’P 0 


64-bit Adder Propergation Delay 

Carry Save Adder (CSA) 

We can implement a 64-bit adder using AND-or logic 

with a fan-in = 4 and a maximum propergation delay of: 

t pmax = 3(G 1 ’) + 2(G 1 ’’) + 2(C 48 ) + 2(C 60 ) + 3(S 63 ) 

= 12 gate delays 

Compare this with RCA using AND-wiredOR which 

requires 64 gate delays. 

If we add a third layer (G’’’, P’’’) we can construct 

a 4x64 = 256 bit adder with maximum delay: 

t pmax = 3 + 2 + 2 + 2 + 2 + 2 + 3 

= 16 gate delays 


In situations where we have a lot of numbers to add: 

Multiplication (adding partial products) 

Accumulation Loop 

We can defer the propergation of carries until the 

last last addition. 

S = X + Y + Z + W 

= (X + Y + Z) + W -- CSA 1 

= 2 x C1 + S1 + W -- CSA 2 

= 2 x C2 + S2 -- CLA 

= S3

ALU Design 4-bit Ripple Carry Adder RCA Equations

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