Presentation on System-Level Design and Verification using ADS ...

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System-Level Design & Verification Using 

ADS Behavioral Modeling

Design & Verification Flow 

System 

Definition 

EM 

Circuit/RFIC 

Design 

Baseband 

Tape Out 


Integration 


Verification 

Asia EEsof Spring Technology Forum Page 2

End-to-End System Verification 

Reducing Integration Risks from Design to the End Product 

Wireless Pre- 

Configured Templates 

EM 

Tape Out 



Circuit/RFIC 







Verify HW System 

Performance as 

Soon As Possible 



Co-Simulation and 

Modeling Technology 

Predictive 

Measurement 

Algorithms 

• RF/Baseband integration can be a major bottleneck !! 

• Verify as soon as possible in both simulation and test 

• Consistent measurement algorithms from definition to 

verification testing for more predictive design 

• System metrics- EVM, BER, BLER (as opposed to CW 

measurements) 

• System-level verification begins before entire system is 

available 

• Create measurement-based simulation models to re-iterate 

design in simulation, if needed 


ADS Top-Down Design Flow 

Bottom-Up Verification 

System-Level 

Circuit-Level 

Transistor-Level 

Hardware-Level 


Co-Simulation with Agilent Ptolemy 


ADS System-Level Modeling 

Amplifier 

from Schematic Design 

OR 

from Measurements 

Behavioral Model 

Populated from 

Simulations or 

Measurements 

Amplifier HW 


Benefits of System-Level Modeling 

Design Flow Timeline 



Circuit/RFIC 






Design Specs Partitioned 

Circuits are 

Designed 

Circuits Works OK in 

System Simulation 

Remaining HW Becomes Available 

and System-Level Testing Finally 

Begins…Integration Problem 

Found…Re-work Design in 

Simulation or on the Testbench? 

4 months later?.. 6 months later? 

Component DUT HW 

Becomes Available 

This Paper Will Show How to Identify Potential System Integration Issues Earlier 

in the Design Cycle and How to Create Behavioral Models from Hardware to Re-Work 

Designs in Simulation 


Applying System-Level Modeling 

in a Design Flow 

Design Flow Timeline 



Circuit/RFIC 






Re-Work 

Design in 

Simulation 

OR 

Evaluate 

IP Re-Use of 

Existing HW 

Speed Simulation by 

Encapsulating IP in 

Data Model 

Behavioral 

Model from 

Simulation 

Verify End-to-End 

System-Level 

Performance with 

Component HW 

Behavioral 

Model from 

Measurements 

Provide Simulation 

Models to Others 

Amplifier Circuit Design 

Create Simulation Model from DUT Hardware to Re-work System Design in Simulation 

Amplifier 

DUT HW 


Where System-Level Modeling Fits In… 

System Modeling: 

Component Model, not 

Device Model 

Created from Simulation 

Schematic or 

Measurements 

Use to Improve 

Simulation Speed After 

Circuit Design is 

Complete 

Use to Re-Work Designs 

In Simulation After Fab 

Use to Provide Simulation 

Models of Final HW to 

Others 


Case Study: 

Transmitter Design Example

System Definition: 

Put Together Top Level Design 

EM 



Circuit/RFIC 


• Interpret System Design Specifications 

• Put Together Top-Level Design with 

Parameterized Behavioral Elements 

Tape Out 




• Partition Design Requirements for Circuits 




Design Specifications for 

Example Transmitter Design 

WCDMA: 

• Output Power= +24 dBm min. at 1950 MHz 

• ACLR = 33 dB or better at +/- 5 MHz Offset 

• ACLR =43 dB or better at +/- 10 MHz Offset 

• EVM= 17.5% or Less 


Put Together Top-Level Design with RF 

Parametric Behavioral Models 

Specify LO Phase Noise vs. Frequency Offset 

Specify Amplifier Gain, 

P1dB, TOI… 


Perform Simulation and Verify ACLR Design 

Performance 

Meets +24 dBm Output 

Power Specification 

Meets ACLR Specifications 

at 5 & 10 MHz Offsets 


Perform Simulation and Verify EVM Design 

Performance 

EVM at Output of 1 st Behavioral Amplifier, Behavioral Pre-Amplifier, 

and Final Output- meets 17.5% Specification 

Top-Level Design Meets System-Level Design Specifications 


Circuit/RFIC Design: 

RF Circuit and Baseband Designs 



• Design Transistor-Level Circuits or Re-Use 

Existing Circuit Designs 

EM 

Tape Out 

Circuit/RFIC 





• Design Fixed-Point or Floating-Point 

Baseband Sections 

• Verify that Top-Level Design Still Meets 

Specifications with Circuit and Baseband Designs 



• Use Automatic Verification Modeling (AVM) to 

Enhance System Simulation Speed 


Insert Circuit Designs and Fixed Point FIR 

11-Bit Fixed-Point FIR 

IF Amplifier Circuit Design 

RF Pre-Amplifier Circuit Design 


Verify ACLR Design Performance 






Verify EVM Design Performance 

EVM at Signal Source Output is 

Degraded by the Fixed-Point FIR 

Effects of 11-Bit 

Fixed-Point FIR 

EVM at Output of 1 st Circuit Amplifier, 

Circuit Pre-Amplifier, 


Top-Level Design Still Meets Specifications with RF Circuits 

and Fixed-Point Baseband Design 

…Now Use AVM to Enhance System Simulation Speed 


Automatic Verification Modeling (AVM) 

New simulation technology based on static non-linear behavior of 

circuits 

Intended for fast co-simulation from Agilent Ptolemy- not for use in A/RF 

schematic window alone 

Automatic characterization when Agilent Ptolemy simulation is launched 

Re-use previous characterization data for additional speed improvements 


Use AVM to Enhance Simulation Speed 

(fast co-simulation) 

Q 

I 

Mod 

FIR 

RF_ModFIR 

R1 

PowerAmp_sub_evm 

X5 

EnvOutShort 

O1 

Characterization (time=0) 

Port 

P1 

Num=1 

Normal Co-simulation 

BJT_NPN 

BJT3 

Envelope 

BJT_NPN 

BJT2 

BJT_NPN 

BJT1 BJT_NPN 

BJT4 

Port 

P2 

Num=2 

Port 

P1 

Num=1 

V_1Tone 

SRC1 

HB 

BJ T_NPN 

BJ T3 

BJT_NPN 

BJT2 

BJ T_NPN 

BJ T1 BJ T_NPN 

BJ T4 

Port 

P2 

Num=2 

Fast Cosim 

Validation 

Vout = F(|Vin+Nin|)*exp(j*H*Ph(Vin+Nin)) 

Ma g 

.DS 

1 

Ph 2 

Port V_Noise 

P1 

SRC1 

Fast Cosim 

_FIR 

Xopt 

_NL 

X1 

Port 

P2 


Setup Circuit Envelope Controller for AVM 


Comparison: Circuit Co-Sim and AVM 

Good Agreement Between AVM Simulation Results and Circuit 

Co-Simulation…Use AVM for Further System-Level Simulations 


System Integration: 

RF Behavioral Model, Verilog HDL, Verilog-A 



• Circuit Designs are Complete- Encapsulate IP in 

Behavioral Model to Share Model with Colleagues 

EM 

Circuit/RFIC 


• Integrate Verilog HDL FIR Root-Raised-Cosine Filter 

Tape Out 




• Integrate Verilog-A Mixer Circuit Design 




Extracting the AmplifierP2D Model from 

the Pre-Amplifier Circuit Design 

Specify Frequency Sweep 

Characteristics 

Specify Power Sweep 

Characteristics 


Example of AmplifierP2D Model 

Small Signal Two-Port 

S-Parameter Data 

Amplifie rP 2D 

AMP 1 

Freq=850 Mhz 

P2DFile="amp.p2d" 

Power-Dependent 

S-Parameter Data 

At Each Frequency 


Compare Gain & Phase of Extracted 

Behavioral Model to Circuit Design 


Replace Circuit Design with Behavioral Model to 

Verify Modulated Performance 


Circuit & AVM Co-Sim, and Behavioral Model 

Behavioral Model Accurately Represents Circuit Design Performance 

… Can Now Provide a Simulation Model to Colleagues 


Replace Fixed-Point FIR Filter with Verilog HDL Code 

to Co-Simulate with NCSim 

Verilog HDL 

Filter Design 


Replace Behavioral Mixer with Verilog-A 

Mixer Subnetwork 

Verilog-A 

Mixer Design 


ACLR Performance of Final Design with Verilog HDL 

Filter and Verilog-A Mixer Design 





Note: Simulation used one HDL filter co-simulation and one fixed-point behavioral filter 


EVM Performance of Final Design with Verilog HDL 

Filter and Verilog-A Mixer Design 

EVM at Output of 1 st Circuit Amplifier, Circuit Pre-Amplifier, 


System Design Still Meets Specifications with Verilog HDL Digital 

Filter and Verilog-A Mixer Design…Integration Complete 

Note: Simulation used one HDL filter co-simulation and one fixed-point behavioral filter 


System Verification: 

Start System-Level Testing with Component Hardware 



• Component Hardware Available, but Remaining 

Hardware is Still Missing 

EM 

Tape Out 

Circuit/RFIC 





• Use Hardware DUT-in-the-Simulation Path to 

Test Component at a System-Level 

• If Integration Problem is Identified, then Create 

a Simulation Model from Hardware DUT to Modify 

System Design in Simulation 




Begin System-Level Verification Testing on 

Hardware Amplifier Component 

Amplifier DUT 

ESG Sig. Gen. 

Signal Analyzers 

HW Avail. 

for Test 

Design Modeled in ADS 

Find and Fix Issues Early in the Design Process-Reduce System 

Integration Risk 


Insert HW DUT in the Simulation Path: 

Download to ESG Signal Generator 

Download Simulated I and Q to 

E4438C ESG Arbitrary Waveform Generator 


Picture of Connected Solutions Test Setup 

Power Meter, 

DC Supply 

E4440A PSA 

E4438C ESG 

89640 VSA 

Laptop with ADS 2003C 

E8358A PNA 


Picture of Test Signal Downloaded from ADS to ESG 

(input to DUT) 

Spectral Re-growth from 

Verilog-A Mixer and IF 

Amplifier Circuit Design 

Effects of 11-Bit 

Fixed-Point FIR 

Note that this is a system-level test signal which reflects the 

simulated design impairments at the input of the DUT 


Measured vs. Simulated Results at 

Amplifier Output 

Measured 

Simulated 

Main Ch. Power 13.22 dBm 14.67 dBm 

% EVM 4.54 % 4.32 % 

ACLR, +10 MHz 44.57 dB 44.44 dB 

ACLR, +5 MHz 33.63 dB 34.43 dB 

ACLR, -5 MHz 33.4 dB 34.26 dB 

ACLR, -10 MHz 43.8 dB 44.33 dB 

DUT Component Meets Specifications, but Has Less Gain Than 

Expected…What is the Impact to the Overall System Performance? 


Access Impact on System Performance: 

Read DUT Output from VSA into Simulation 

to Run End-to-End System Analysis 

Read Measured DUT Signal 

from 89640 VSA into ADS 


New Predicted System Performance with 

HW DUT in the Simulation Path 

Original New Predicted w/ 

Simulated DUT-in-Simulation-Path 


% EVM 4.54 % 4.71 % 

ACLR, +10 MHz 44.67 dB 44.54 dB 

ACLR, +5 MHz 33.41 dB 32.66 dB 

ACLR, -5 MHz 33.21 dB 32.47 dB 

ACLR, -10 MHz 44.57 dB 44.24 dB 

System Integration Problem Found…System Will Not Meet 

Specifications With Component Hardware 

…Create Simulation Model From DUT Hardware to Re-Work System 

Design in Simulation 


Create Simulation Model of Amplifier DUT 

to Re-Work Design in Simulation 

Select PNA. 

Enter power range. 

Select measurement. 

Select Amplifier Model. 

Click ‘Measure.’ 


Connected SolutionsTest Setup and 

Characterization Parameters 

PNA Measurement Parameters 

• Center Frequency = 1.95 GHz 

• Frequency Span = 40 MHz 

• 201 Frequency Points 

• RF Power Swept from –15 dBm to 

+ 7 dBm in 1 dB Steps 

• Port 1 Power Set to -5 dBm for Calibration 

• E8358A PNA (300 kHz- 9 GHz) Used 


Compare Simulated vs. Measured ACLR for 

Meas-Based Amplifier Model 

• ADS Signal Downloaded to E4438C ESG 

• ESG Amplitude Calibrated for Cable Loss 

• Measured vs. Simulated Results Compared 

at Various RF Power Levels 

• ACLR Measurements Made with E4440A PSA (top) 

• EVM Measurements Made with 89640 VSA (left) 


Compare Sim. vs. Meas. Main Channel Power and EVM 

for Meas-Based Amplifier Model 

• ADS Signal Downloaded to E4438C ESG 

• ESG Amplitude Calibrated for Cable Loss 

• Measured vs. Simulated Results Compared 

at Various RF Power Levels 

• Power Measurements Made with E4440A PSA (top) 

• EVM Measurements Made with 89640 VSA (left) 


Include the Effects of Residual EVM 

on Meas-Based Model Evaluation 

Downloading the ADS Signal to the E4438C results in a residual EVM of approximately 1.22% @ 0 

dBm, Measured with the 89640 VSA 

RSS’ing the 1.22% residual EVM with the model simulation results show improved agreement 

between simulated and measured results (e.g. EVM_RSS= sqrt(EVM_simulated^2 + 1.22^2) to 

reflect test equipment characteristics 


Meas-Based Model Reflects 

HW DUT in the Simulation Path 

Predicted w/ 

DUT-in-Simulation-Path 

Meas-Based 

Model 


% EVM 4.71 % 4.59% 

ACLR, +10 MHz 44.54 dB 44.75 dB 

ACLR, +5 MHz 32.66 dB 32.94 dB 

ACLR, -5 MHz 32.47 dB 32.72 dB 

ACLR, -10 MHz 44.24 dB 44.66 dB 

Simulation Model Created from DUT Hardware Agrees with 

DUT-in-the-Simulation Path Results. Use Model to Re-Work System 

Design in Simulation 


Use the Meas-Based Model to Re-Iterate 

the System Design to Meet Specifications 

Modified Verilog-A Mixer Subnetwork 

And PA Requirements to Re-Iterate System Design 

Model Created from DUT 

Component Hardware 


Rapid Design Iteration: Final System Design ACLR 

Performance Meets Specifications 






Final System Design EVM Performance 

Also Now Meets Specifications 

EVM at Output of 1 st Circuit Amplifier, Circuit Pre-Amplifier, 


System Design was Re-Iterated Immediately After the First Component 

DUT Became Available for Testing and Integration Problem Was 

Discovered…Helps to Save Time and $$$ 


Summary 

• Behavioral modeling, measurement-based modeling, and 

Verilog-A, can be used for model creation and IP transport 

• Consistent ACLR and EVM simulation results were observed 

between circuit co-simulation, AVM fast co-simulation, and 

behavioral modeling 

• Connected Solutions DUT-in-the-simulation-path allows 

system-level verification testing to begin earlier to identify 

potential system integration issues with component hardware 

• Measurement-based modeling enables models to be created 

from DUT hardware to re-work system designs in simulation 

if integration issues are found 


Appendix

Ag ile nt T e c hno log ie s 

Ag ile n t T e c h nolog ie s 

Ag ile nt T e c hno log ie s 

Agilent Technologies 

Other RF Data-Based Behavioral Models 

Lo a d P ull 

Setup 

• Simulation Control 

Components that Create 

Structured Data Sets To 

Describe Circuit Behavior 

• Data Set is used by a Unique 

Component to implement 

Model Behavior 

LoadPullSetup 

X5 

Freq=1 GHz 

Order=10 

Pin_Start=-50 _dBm 

Pin_Stop=-20 _dBm 

Pin_Step=10 _dB 

GamAng_Start=-180 _degrees 

GamAng_Stop=180 _degrees 

GamAng_Step=20 _degrees 

GamMag_Start=0.1 

GamMag_Stop=0.9 

GamMag_Step=0.1 

in 

in 

H1H2 

Setup 

Am p H1H2_S e tu p 

X6 

F re q =1.0 G Hz 

Order=10 

Pin_Start=-50.0 _dBm 

Pin_Stop=-20.0 _dBm 

Pin_Step=10.0 _dB 

out 

P2D 

Setup 

out 

Am p lifie rP 2 D _ S e tu p 

X1 

Filename="p2dfile.p2d" 

Order=10 

F re q _S ta rt=1.0 G Hz 

Freq_Stop=2.0 GHz 

Freq_Step=0.1 GHz 

Pin_Start=-50.0 _dBm 

Pin_Stop=-20.0 _dBm 

Pin_Step=10.0 _dB 

AmpLoadPull 

AMP 2 

Da ta s e t="d a ta s e t.d s " 

In s tru m e n tID = "X1 " 

Am p H1H2 

AMP 3 


G1expr="Vout[1]/Vin[1]" 

G2expr="Vout[2]/Vin[1]" 

Am p lifie rP 2 D 

AMP 1 


P2DFile="p2dfile.p2d" 

I 

Q 

RF 

IQ M o d ula to r 

Setup 

IQ_Mod_Setup 

X2 


Order=10 

Pin_Start=-40 _dBm 

Pin_Stop=10 _dBm 

Pin_Step=2 _dB 

IQ_Mod_Data 

X4 



In s tru m e n tID = "X1 " 


IQ Modulator Measurement-Based Modeling 

Test Setup 

Ref: Joel Dunsmore, Greg Jue, and John Kikuchi, 

Agilent Technologies, 

A Measurement-base Behavioral Model for I/Q RF 

Modulators, Microwave Journal, December 2002. 

Measurement-Based Model Shows Good 

Agreement between Simulated and Measured 

EVM Comparisons 

8 

EVM (%) 

6 

4 

2 

Simulated 

Measured 

IQ Simulation 

Model File 

0 

0.14 

0.18 

0.22 

0.26 

0.30 

0.34 

IQ Input Voltage (V) 

0.38 

This is a custom application of Connected Solutions, and shows it’s flexibility in 

applications such as creating measurement-based simulation models 


Additional Literature 

Application Note 1482: Importing SystemC Designs into Advanced 

Design System 

Application Note 1394: Connected Simulation and Test Solutions 

Using the Advanced Design System. 

Application Note 1471: RF/IF-to-Digital Connected Solutions Bit Error 

Rate using the Advanced Design System. 


Demo: ADS Simulation with 89600 VSA SW 

(click on each VSA display in slide show mode) 


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