Presentation on System-Level Design and Verification using ADS ...
Presentation on System-Level Design and Verification using ADS ...
Presentation on System-Level Design and Verification using ADS ...
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Benefits of <strong>System</strong>-<strong>Level</strong> Modeling<br />
<strong>Design</strong> Flow Timeline<br />
<strong>System</strong><br />
Definiti<strong>on</strong><br />
Circuit/RFIC<br />
<strong>Design</strong><br />
<strong>System</strong><br />
Integrati<strong>on</strong><br />
<strong>System</strong><br />
Verificati<strong>on</strong><br />
<strong>Design</strong> Specs Partiti<strong>on</strong>ed<br />
Circuits are<br />
<strong>Design</strong>ed<br />
Circuits Works OK in<br />
<strong>System</strong> Simulati<strong>on</strong><br />
Remaining HW Becomes Available<br />
<strong>and</strong> <strong>System</strong>-<strong>Level</strong> Testing Finally<br />
Begins…Integrati<strong>on</strong> Problem<br />
Found…Re-work <strong>Design</strong> in<br />
Simulati<strong>on</strong> or <strong>on</strong> the Testbench?<br />
4 m<strong>on</strong>ths later?.. 6 m<strong>on</strong>ths later?<br />
Comp<strong>on</strong>ent DUT HW<br />
Becomes Available<br />
This Paper Will Show How to Identify Potential <strong>System</strong> Integrati<strong>on</strong> Issues Earlier<br />
in the <strong>Design</strong> Cycle <strong>and</strong> How to Create Behavioral Models from Hardware to Re-Work<br />
<strong>Design</strong>s in Simulati<strong>on</strong><br />
Asia EEsof Spring Technology Forum Page 7
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