Presentation on System-Level Design and Verification using ADS ...

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Meas-Based Model Reflects HW DUT in the Simulation Path Predicted w/ DUT-in-Simulation-Path Meas-Based Model Main Ch. Power 23.71 dBm 23.62 dBm % EVM 4.71 % 4.59% ACLR, +10 MHz 44.54 dB 44.75 dB ACLR, +5 MHz 32.66 dB 32.94 dB ACLR, -5 MHz 32.47 dB 32.72 dB ACLR, -10 MHz 44.24 dB 44.66 dB Simulation Model Created from DUT Hardware Agrees with DUT-in-the-Simulation Path Results. Use Model to Re-Work System Design in Simulation Asia EEsof Spring Technology Forum Page 47
Use the Meas-Based Model to Re-Iterate the System Design to Meet Specifications Modified Verilog-A Mixer Subnetwork And PA Requirements to Re-Iterate System Design Model Created from DUT Component Hardware Asia EEsof Spring Technology Forum Page 48
Page 1 and 2: Agilent EEsof EDA This document is
Page 3 and 4: Design & Verification Flow System D
Page 5 and 6: ADS Top-Down Design Flow Bottom-Up
Page 7 and 8: ADS System-Level Modeling Amplifier
Page 9 and 10: Applying System-Level Modeling in a
Page 11 and 12: Case Study: Transmitter Design Exam
Page 13 and 14: Design Specifications for Example T
Page 15 and 16: Perform Simulation and Verify ACLR
Page 17 and 18: Circuit/RFIC Design: RF Circuit and
Page 19 and 20: Verify ACLR Design Performance Meet
Page 21 and 22: Automatic Verification Modeling (AV
Page 23 and 24: Setup Circuit Envelope Controller f
Page 25 and 26: System Integration: RF Behavioral M
Page 27 and 28: Example of AmplifierP2D Model Small
Page 29 and 30: Replace Circuit Design with Behavio
Page 31 and 32: Replace Fixed-Point FIR Filter with
Page 33 and 34: ACLR Performance of Final Design wi
Page 35 and 36: System Verification: Start System-L
Page 37 and 38: Insert HW DUT in the Simulation Pat
Page 39 and 40: Picture of Test Signal Downloaded f
Page 41 and 42: Access Impact on System Performance
Page 43 and 44: Create Simulation Model of Amplifie
Page 45 and 46: Compare Simulated vs. Measured ACLR
Page 47: Include the Effects of Residual EVM
Page 51 and 52: Final System Design EVM Performance
Page 53 and 54: Appendix
Page 55 and 56: IQ Modulator Measurement-Based Mode
Page 57 and 58: Demo: ADS Simulation with 89600 VSA

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