experiment 6: flip-flops and feedback devices - The Circuits and ...

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Figure 6.1 RS NAND Latch. A simple application of the RS NAND latch is illustrated in Figure 6.2. By connecting the latch, as shown, to a switch, a contact bounce free signal is provided. This circuit output changes only once no matter how many times the switch makes and breaks contact as it bounces. The circuit is based on the assumption that TTL floating inputs act as if they were provided with HIGH inputs. The momentary breaks in contact of the switch pole with a switch terminal while the contacts are bouncing (after the switch makes initial contact) provides the circuit with floating inputs. However, since the latch remains unchanged when both inputs are HIGH, the output is unaffected by contact bounce. The circuit should be made more reliable by connecting pullup resistors to both contacts of the switch to assure that an input is a logic 1 when the switch is not connected to it. Figure 6.2 Switch Debounce Circuit. From Figure 6.2, it is clear that the latch output immediately follows changes in the inputs after one or two gate propagation delays. In this configuration, it is not possible to control the moment at which the output changes as a result of an input change. The input change alone 6.2
triggers the subsequent output change. Circuits constructed from such unclocked devices as latches are referred to as asynchronous circuits. The design of asynchronous circuits is much more involved than that of synchronous circuits, in which changes of the memory element outputs are synchronized by a clock. Sequential circuit design is greatly simplified through the use of clocked flip-flop (FF) memory elements. Virtually all complex sequential systems use them. In synchronous circuits, the length of the clock period can be controlled so that when the outputs of FFs change, these changes are allowed to propagate through the combinational logic and provide stable inputs to the FFs before the next clock pulse enables the FFs to change again. Hence, any glitches in the outputs of combinational logic that may occur are not important in synchronous circuits. GATED LATCHES The gated NAND RS latch memory element is illustrated in Figure 6.3(b). (This circuit is also called a transparent latch or a latch with enable.) Its operation can be synchronized with a clock signal by connecting the gate to a clock, but by itself, it is not a clocked FF, i.e., it does not avoid many of the problems mentioned above. Figure 6.3 Gated RS Latch Controlled by a Gate Signal. 6.3
Page 1: EXPERIMENT 6: FLIP-FLOPS AND FEEDBA
Page 5 and 6: Figure 6.4 Master-slave JK FF. Whil
Page 7 and 8: Figure 6.6 Setup and Hold Times. Th
Page 9 and 10: PRELAB 1. Suppose a gated RS NOR la
Page 11 and 12: B. Master-Slave Flip-Flop 1. Comple
Page 13 and 14: EXPERIMENT 6--FLIP-FLOPS AND FEEDBA
Page 15 and 16: c). Based upon your observations in

experiment 6: flip-flops and feedback devices - The Circuits and ...

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