Chapter 5 Test Bench for the Doubly-Fed Induction Generator based ...

Chapter 5
Test Bench for the Doubly-Fed Induction Generator
based Wind Turbine Generator System
This chapter describes in detail the realized test bench. The dimensioning of
major components is also discussed. It is organized such that Section-5.1
provides the test bench layout while Section-5.2 and Section-5.3 describe the
power handling and the control system components respectively.
The developed setup is for a 10 kW DFIG based WTGS, controlled by Digital
Signal Processing (DSP) cards from the manufacturer dSPACE [dSPACE 2011].
The Semiteach converter is from the manufacturer Semikron [SEMIKRON 2005].
The necessary transducers and hardware protection against short-circuit, overvoltage
at the DC-link and over-temperature have been included inside chariots
especially made for the test bench. The user’s manual attached as Appendix-D
provides detailed information on the chariots. Special effort has been placed to
ensure safe operation of the equipment and safety of the user. Apart from the
functions provided by the IGBT drivers, the additional fault protection features
designed are
• The measurement signals (low power) are accessible at the front while
the high power currents and voltages are connected at the back of the
chariot.
• Phase indicator lamps: to show the availability of each of the grid phases.
• Status LEDs: to indicate which of the contactors are currently operating.
• DC-link voltage panel meter: to indicate capacitor voltage at all times.
• DC-link over-voltage circuit: to avoid damage to the capacitors.
• Thermal over-load circuit: to avoid damage to the semiconductors.
• Audible alarm generator and latch function: to prevent further operation
unless the cause of the fault has been removed.
• Desktop emergency push-button: to isolate the system quickly and from a
safe distance, to avoid fault propagation.
5.1 Test Bench Layout
The layout of the test bench is presented in Figure-5.1. The components, marked
with numbers, are listed in Table-5.1. The arrow, to the left of the figure, signifies
the fact that the wind turbine drive train i.e. the blades, the low-speed shaft and
the gear-box are to be emulated by a motor controlled by a drive. This drive
takes its reference from a DSP card that runs the model of the drive-train. The
other DSP cards control the electrical part of the generator. They send proper
switching signals to the IGBT drivers and the measured currents and voltages are
fed-back to the cards, after signal-conditioning and filtering. Several of the
components have been recuperated from existing material in the laboratory due
to large time delays, up to 4 months, in delivery.
5-1

Figure 5.1 – The DFIG based WTGS test bench.
Table 5.1 – List of components for the DFIG based WTGS test bench.
Component
No.
1
3
5
8
10
12
14
Description
Drive-Train
Emulator-Motor
Drive
(30 kVA)
Speed Encoder
(360 pulses/rev)
Doubly-Fed
Induction Generator
(15 kW)
DC-link Capacitor
(1100 μF, 750 V)
Machine Contactors, Circuit
Breakers, Over-load Relays
(for a 15 kW machine)
Digital Signal
Processing Card
(DS1104)
Signal Conditioning +
Filtering
(±10 V, ≤ 500 Hz)
Component
No.
2
4
6 & 7
9
11
13
15
16 Desktop Computer (PC) 17
Miscellaneous
Description
Drive-Train
Emulator-Motor
(15 kW)
Torque Meter
(100 Nm)
IGBT based
Converter
(20 kVA)
Inductance Filter
(6 mH, 30 A)
Digital Signal
Processing Card
(DS1104)
Current and Voltage
Transducers
(50 A, 860 V)
DC Power Supply
(± 15V, 5 V, 24 V)
Charging Resistors
(330 Ω, 300 W)
Cables, Connectors, Panel Meters, Indicator Lamps etc.
(5 % added to the total component costs)
5-2

5.2 Power Handling Components
Proper dimensioning is required especially for components which handle power,
such that they do not fail for routine operation.
5.2.1 Back-to-Back Converter
The 20 kVA back-to-back converter is formed using two commercially available
Semiteach converters [SEMIKRON 2005]. Each converter has a diode bridge
rectifier, a three-phase IGBT inverter, an IGBT chopper leg and DC-link
capacitors. The drivers for the IGBTs, the heat-sink temperature measurement
sensor, a protective thermal switch and a cooling fan are integrated in the
converter module. The converter schematic is given in Figure-5.2.
Figure 5.2 – The schematic of the Semiteach converter [SEMIKRON 2005].
5.2.1.1 Component Description
5.2.1.1.1 IGBT Modules
The individual IGBT modules SKM 50 GB 123 D are rated at 1200 V, 50 A but the
maximum current recommended by the manufacturer for the Semiteach unit is
30 A [Sargos 2008] [SEMIKRON 2005]. The input voltage signal level required to
turn the IGBT on and off is +15 V and -15 V respectively. The typical turn-on
threshold voltage is 5.5 V. The maximum saturation collector to emitter voltage is
3 V (3.7 V), for junction temperature of 25 ˚C (125 ˚C), at the rated current of 50 A
[SEMIKRON 2006]. The peak collector current can be 80 A but with a maximum
pulse duration of 1 ms. The IGBTs have a high short-circuit current capability of
500 A, at full DC voltage of 1200 V, but this short-circuit must be detected and
removed within 10 μs otherwise there is a risk of thermal breakdown [Sargos
2008]. A maximum of 1000 short-circuit events are allowed, which must be at
least 1 s apart. When the short-circuit current reaches 10 times the nominal, the
IGBT starts to de-saturate, the voltage between collector and emitter increases
and the current is limited [Sargos 2008].
5.2.1.1.2 IGBT Drivers
The SKHI 22A drivers can provide an output peak current of 8 A with the +15 V
and -15 V required to switch the IGBT. The gate resistor value is 30 Ω. The
drivers require a supply voltage of 15 V and consume 16 mA per driver. The
maximum switching frequency for the drivers is 50 kHz. There is interlocking to
prevent simultaneous switch-on for the IGBTs in the same inverter leg. The
driver inserts an interlock dead time of 3.3 – 4.3 µs by default.
5-3

The drivers also provide an error output for protection at faults like short-circuit
of the IGBT, by monitoring the collector to emitter voltage V CE, and the driver
supply under-voltage 13 V. A short-circuit is detected within 5 μs [Sargos 2008].
The error input to output propagation time is 0.6 μs. In fault case, the input firing
pulses are ignored and the output error latch is set. In order to reset the latch,
both the signal inputs should be put to zero for at least 9 μs. The absence of a
fault condition is indicated by a +15 V level at the error outputs. This error
output has to be included when designing an application. The driver also has an
integrated short pulse suppression function, which suppresses switching pulses
less than 500 ns, caused by high frequency interference at the driver input
[SEMIKRON 2008].
5.2.1.1.3 Snubber Capacitors
The MKP type snubber capacitors, rated at 22 μF, 1600 V, are mounted directly
between the collector and emitter terminals of the IGBT modules. They limit
over-voltage, due to the parasitic inductances, and the high rate of change of
IGBT currents. A snubber also reduces the switching losses but this function is
less important for an IGBT, since it can be switched at full current with full rated
voltage e.g. 1200 V [Sargos 2008].
5.2.1.2 Component Dimensioning
For a DFIG, the power flows through the stator ps and the rotor pr are given as
[Santos-Martin et al. 2006]
p
s
pe
≈ (5.1)
1 − s
pr ≈ −s. p s
(5.2)
The selected rated slip s = – 0.12, for a rated power p e = 10 kW of the DFIG
system, gives a rotor power p r equal to 1.1 kW. Now, the rotor voltage v r at a
specific slip s is given as
v
= v .s
(5.3)
r s r s=
1
v
v r =
s=
1
r
s
t
(5.4)
r t is the turns ratio between the stator and the rotor while v s is the stator voltage.
Turns ratio is an important factor for converter current dimensioning since a
large ratio requires larger currents in the rotor, for the same slip power. It is
therefore recommended to select a small turns ratio, if possible [Rabelo &
Hofmann 2005] [Petersson, Lundberg & Thiringer 2005] [Serban et al. 2006]
[Lindholm 2003]. The turns ratio for the generator used in the test bench is 1.91,
which is rather large. With a rated line (phase-phase) voltage of 380 V, this gives
a rotor line voltage around 24 V at the rated slip and the resulting rotor phase
current is 26.6 A, which is within the recommended limit.
5-4

5.2.2 DC-link Capacitor
Electrolytic capacitors are mostly used in automotive and industrial applications
from 1 kW to 1 MW and DC voltages from 200 V to 1000 V [Sargos 2008]. The
advantage, when compared to other capacitor technologies, is greater
capacitance per unit volume while the disadvantages are the higher ESR and the
inability to withstand reverse voltages of a significant value. The heating losses,
incurred due to current flow through the ESR, put a limit on the RMS value of the
ripple current that the capacitor can withstand [Anwar & Teimor 2002].
5.2.2.1 Component Description
Two electrolytic DC-link capacitors, each rated at 2200 μF, 400 V, are connected
in series to provide an equivalent 1100 μF, 800 V rating. The capacitor voltage
balancing resistors are 22 kΩ each. The DC-link capacitor will discharge through
the voltage balancing resistor across it with a time constant of about 48 s.
5.2.2.2 Component Dimensioning
The maximum DC-link voltage specified in the datasheet of the Semiteach
converter is 750 V. The peak DC-link voltage ripple ∆vDC for the converter at
rated conditions, Sconv = 20 kVA, CDC = 1100 μF, vDC = 750 V and ω1 = 314.16 rad/s,
is calculated to be 38.6 V or 5 % of the average DC-link voltage using Equation
(5.5) [Lindholm 2003] [Bojrup 1999].
Sconv
1
∆ vDC
= .
(5.5)
v .C 2. ω
DC
DC
sync
For the rated slip power S conv = 1.1 kVA with C DC = 1100 μF, v DC = 380 V and ω sync =
314.16 rad/s, it gives a 2.0 % peak-peak voltage ripple on the DC-link.
Apart from ensuring equal voltage drop on the series connected capacitors, the
voltage sharing resistors provide a discharge path to the capacitors. This is
important from a safety point of view. This Equation (5.6) gives the expression to
calculate the voltage sharing resistance Rvsr1 for a capacitance value C1 [Evox Rifa
n.d.]. For C1 = 2200 μF capacitance value this gives 30 kΩ which is close to the
available 22 kΩ resistances on the Semiteach.
R
vsr1
1000
= (5.6)
0.015 × C
1
[ ] [ k Ω ] µ F
For high reliability, the power loss in the resistor should be less than 50 % of its
rated value while the tolerance should be better than 5 %. The consequence of
omitting the voltage sharing resistor is that the DC-link voltage is limited, due to
tolerance in capacitance value. This is found using Equation (5.7) [Evox Rifa n.d.].
For an electrolytic capacitor of the type used in this converter, a tolerance of 20
% normally exists. For a v DC = 700 V, maximum tolerance T max = 1.2, minimum
tolerance T min = 0.8 and number of capacitors in series n c = 2, the voltage v cap on
the minimum value capacitor would be 420 V which exceeds its rating.
5-5

v
cap
= vDC
.T max
T + ( n − 1).T
(5.7)
max
c
min
The determination of the capacitor combination, series or parallel, is dependent
on voltage rating and the calculation of power losses. The power losses depend
on the ESR value and the RMS ripple current through the capacitor, which are
application dependent themselves. The current through the capacitor consists of
different frequencies, which depend on the converter switching frequency and
the duty cycle of the output [Anwar & Teimor 2002]. The power loss should be
determined at each frequency, with the RMS value of current and the
corresponding ESR, and added up [Evox Rifa n.d.]. The hot spot temperature, and
thus the operational life time, can then be determined using the thermal
resistance table usually available on request from the manufacturer. The ripple
current limit, for the capacitor used in this converter, is 8.2 Arms at 100 Hz, 85 ˚C
[Sargos 2008].
5.2.3 Inductance Filter
The idea of the inductance filter or the L filter is to put adequate impedance at
the output of the converter to limit the flow of currents around the switching
frequency. Although additional inductance is contributed by the grid interface
transformer, but if the transformer leakage inductance is significant i.e. the grid
is weak, the harmonic currents can cause voltage harmonic distortion at the lowvoltage
side of the transformer [Chen 2005]. This can disturb the PLL on which
the complete control loop relies. Therefore, the major impedance contribution to
the harmonic current flow should come from the inductance of the filter.
The advantage of using an L filter as opposed to an LCL filter is the simple design
concept. The disadvantage is that, for a specific amount of attenuation required
at a switching frequency, a larger overall value of inductance is needed. The
larger the inductance, the greater is the voltage drop across it thereby requiring
a larger converter output voltage and the required minimum DC-link voltage
[Lindholm 2003]. For good dynamic current control performance an additional
increase in DC-link voltage is often required [Lindgren & Svensson 1995]. The
larger DC-link voltage leads to a higher ripple in the current component
associated with active power and therefore a higher ripple in the active power
[Lindgren & Svensson 1995]. Furthermore, the converter output has a higher
dv/dt, when the voltage switches alternately between 0 and vDC, which can cause
EMI problems for nearby equipment and insulation stress. Also the amplitude of
the harmonics in the converter output voltage depends on the ratio of the DClink
voltage and fundamental output voltage. It is therefore recommended to use
the PWM strategy that gives a higher converter output voltage thereby limiting
the DC-link voltage required. The DC-link voltage is usually not set more than
two times the phase-phase voltage [Lindgren & Svensson 1995].
To reduce the inductor size, a higher switching frequency can be used but the
overall switching losses increase since there will be more switching events. It
might also lead to sub-harmonic output currents due to non-ideal switching, if
the time to turn an IGBT on and off becomes larger than a critical percentage of
5-6

the overall switching time period [Lindgren & Svensson 1995]. One solution to
reduce EMI is also to turn an IGBT on and off more slowly but the sub-harmonic
problem may appear, as explained above. To realize an inductance value for
higher power ratings, the cost of the material and weight of the product also
become a concern.
5.2.3.1 Component Description
The three L filter units are three-phase single-core 2 mH, 30 A, 50 – 60 Hz each,
provided by the manufacturer Gestufir. These filter inductances are shown in
Figure-5.3.
Figure 5.3 – The L filter units.
5.2.3.2 Component Dimensioning
The converter can be modelled as a superposition of two voltage sources, one
with a frequency equal to that of the grid and the other with the switching
frequency. On the other hand, the grid itself can ideally be modelled as a single
voltage source at the fundamental frequency, while being a short circuit for other
frequencies [Liserre, Blaabjerg & Hansen 2005]. Thus, the harmonic frequency
circuit is just a voltage source with frequency dependent impedance at its output.
The transfer characteristics from converter voltage to phase current are given by
Equation (5.8). i h, v h are the h order harmonic current and voltage of the
fundamental frequency f sync respectively.
i
v
h
h
1
= (5.8)
2. π .( h. f ).L
sync
f
The frequency response is shown in Figure-5.4 for different values of L f. As a 1 st
order filter it has an attenuation of -20 dB/decade [Serban et al. 2006] [Lindgren
5-7

& Svensson 1995] [Peltoniemi et al. 2006]. The standards related to harmonic
quality of currents exchanged with the grid are IEEE 519-1992 and IEC 1000-3-4
[Liserre, Blaabjerg & Hansen 2005] [Roufi & Lamchich 2004]. A criterion of a
maximum THD of 5 % is usually set for the current exchanged with the grid
[Liserre, Blaabjerg & Hansen 2005] [Peltoniemi et al. 2006]. This is met at a
minimum fundamental-frequency RMS current of 10 A, with simulations carried
out using an inductance of 6 mH and switching frequency of 1.95 kHz. The
voltage drop over the filter, in this case, is 2.0 % of the grid line voltage 220 V.
From simulations, for a fundamental-frequency RMS current of 2.9 A equivalent
to 1.1 kW slip power, the THD of the currents is 11 % but this current is only a
fraction of the total current of the generator. The THD is calculated using
Equation (4.24).
Figure 5.4 – Frequency response of the inductance filter transfer characteristics.
5.2.4 Emulator Motor
As mentioned in Section-5.1, the drive train of the WTGS is emulated through an
induction motor coupled to the DFIG, as shown in Figure-5.5.
Figure 5.5 – The emulator motor (left) and the DFIG (right).
5-8

5.2.4.1 Component Description
The squirrel-cage induction motor selected for the emulator function is an IEC 34
15 kW, 400 V, 50 Hz, 1460 rpm machine from the manufacturer 2EC. The name
plate is shown in Figure-5.6.
Figure 5.6 – Name plate of the induction motor for the wind turbine emulator.
5.2.4.2 Component Dimensioning
The catalogue data of the 15 kW slip ring induction machine, used as a DFIG, is
given in Table-5.2 [VEM n.d.]. It is necessary to determine the rating of the
emulator motor, which allows one to generate 10 kW from this machine. With a
rated efficiency of 85 %, the input power required at the shaft is 10 kW/0.85 =
11.76 kW.
Table 5.2 – Catalogue data of the 15 kW, 400 V, 50 Hz, 4-pole slip ring induction
machine SPH 160 M4 from VEM [VEM n.d.].
Stator
Voltage
[ V ]
Stator
Current
[ A ]
Speed
[rpm]
Rotor
Voltage
[V]
Rotor
Current
[A]
Eff.
[%]
Power
Factor
Inertia
[kg.m 2 ]
Y 380
∆ 220
Y 31.5
∆ 54.5
1440 205 45 85 0.85 0.128
The rated slip s for the DFIG is -0.12. This is equivalent to 176 rad/s or 1680 rpm.
The torque required at the shaft is therefore 11760/176 = 66.84 Nm.
To run the emulator motor at n m = 1680 rpm the output frequency f d of the drive,
for a machine with poles p = 4, is 56 Hz determined using
p
f d = nm
.
120
(5.9)
The load capacity curves of IEC 34 motors are given in Figure-5.7 [ABB n.d.].
Curve 1 is the typical continuous load capacity curve of a self-ventilated motor.
The motor rated frequency and the flux weakening point are at 50 Hz.
5-9

The shape of the curve is defined by the required cooling and flux weakening.
Below 50 Hz, the cooling capacity of the self-ventilated motor is reduced while at
frequencies above, the flux weakening region, the voltage cannot be increased
further. Thus in both cases, the load capacity is reduced.
At 56 Hz, the specified load capacity is 90 %. Thus the nominal torque of the
emulator motor is 66.84/0.90 = 74.27 Nm. Finally, the rated power of the
required emulator motor is 74.27*1500*(2*π/60) = 11.67 kW.
The higher standard offering after 11 kW is 15 kW. Thus a 15 kW squirrel-cage
induction machine is selected for the emulator function.
Figure 5.7 – Load Capacity Curves for IEC 34 motors [ABB n.d.].
5.2.5 Generator
The name plate data of the DFIG is given in Table-5.2. The stator of the generator
has been rewound to study winding short-circuit faults. The construction details
of the machine are given in Table-5.3. All dimensions are in mm. Figure-5.8
shows the rotor.
Figure 5.8 – The DFIG rotor.
5-10

Table 5.3 – Construction details of the DFIG with dimensions in mm.
Stator
No. Property Value
1 Stack length 170
2 Stack diameter 176
3 End turns length (terminals side) 60
4 End turns length (opposite side) 50
5 Winding diameter (internal) 185
6 Winding diameter (external) 230
7 Slots 48
8 Slot opening 2.65
9 Slot width 7
10 Slot depth 21
11 Conductors in parallel 2
12 Conductor diameter 1.6
13 Poles 4
14 Cable terminals 6
15 Coil pitch 11 th slot
16 Turn length 700 approx.
17 Sensor PT 100
Rotor
No. Property Value
1 Stack length 169
2 Stack diameter 175
3 Slots 36
4 Slot opening 2.65
5 Slot width 8
6 Slot depth 34
7 Conductors in parallel 4
8 Conductor diameter 0.95
9 Coil pitch (concentric) 8 th and 6 th slot
10 Turns 15 approx.
11 Turn length 770 approx.
12 Skew angle 5˚
The stator winding scheme is presented in Figure-5.9. Figure-5.10 shows the
rewound stator.
5-11

Figure 5.9 – Scheme of the rewound DFIG stator.
5-12

(a)
(b)
Figure 5.10 – The rewound DFIG stator. (a) Stator core. (b) Winding terminals.
5.2.6 The Encoder
The speed measurement is provided by an encoder integrated within an inline
torque meter DR-2112 from Lorenz Messtechnik [Lorenz n.d.]. The torque output
is ±5 V for 100 Nm with a sample rate 10 kSamples/s. Two TTL channels, A and B,
provide 360 pulses per revolution, which are 90˚ phase shifted to allow the
determination of the direction of rotation. The torque meter is shown in Figure-
5.11.
5-13

Figure 5.11 – The torque meter.
5.3 Control Hardware
The control hardware consists of data acquisition and data processing devices.
5.3.1 Current Transducers
Five current transducers are provided for each converter. The instantaneous
value transducers, LT-100S from LEM, have a bandwidth DC…150 kHz and an
output of ±9.8 V for a ±50 A current input (DC/AC/pulsed). The response time at
90 % of the nominal current is less than 1 μs while the accuracy and linearity are
±0.5 % and less than 0.1 % respectively [LEM n.d.].
5.3.2 Voltage Transducers
Five voltage transducers are provided for each converter. The instantaneous
value transducers, LV100 from LEM, provide ±7.5 V output for an input of ±860 V
(DC/AC/pulsed). The response time at 90 % of the nominal voltage is 20 μs to
100 μs while the accuracy and linearity are ±0.7 % and less than 0.1 %
respectively [LEM n.d.].
5.3.3 DS1104 Rapid Prototyping System
The dSPACE DS1104 R&D Controller Board is based on MPC8240 processor with
PPC603e core and on-chip peripherals. It is a 64 bit floating-point processor with
a 250 MHz CPU. The slave DSP responsible for PWM generation is based on
TMS320F240 from Texas Instruments. It is a 16 bit fixed-point processor with a
20 MHz clock frequency. The hardware interface panel is shown in Figure-5.12.
Figure 5.12 – Connector panel for the DS1104 R&D Controller Board.
5-14

Other features of the rapid prototyping system, related to the control system of
the DFIG, are described below.
5.3.3.1 Analogue to Digital Converters (ADC)
The ADC inputs are present to interface with the transducers. They consist of 8
channels. ADCH1 to ADCH4 are multiplexed, 16 bit resolution, to a single ADC
while ADCH5 to ADCH8 are four independent ADC, each with 12 bit resolution.
The input voltage limit is ±10 V. The conversion time for the multiplexed
channels is 2 μs while for the parallel channels it is 800 ns.
5.3.3.2 Digital to Analogue Converters (DAC)
The DAC outputs are present to interface with actuators. There are 8
independent DAC channels. DACH1 through DACH8 have a 16 bit resolution and
voltage output limits of ±10 V. The output current limit is ±5 mA.
5.3.3.3 Master PPC Digital Input/Output
The 20 parallel Input/Output (I/O) provided by the master processor are
indicated as Digital I/O on the connector panel. They have a TTL level and a
current limit of ±5 mA.
5.3.3.4 Slave PWM Digital Input/Output
The digital I/O controlled by the slave DSP and marked as Slave I/O PWM on the
connector panel are reserved for functions related to the generation of PWM
signals. They also have a TTL level but a higher current limit of ±13 mA.
5.3.3.5 Incremental Encoder Interface
The 24 bit digital incremental encoder interfaces, 2 in number, are present for
speed and position measurement. They are single-ended TTL or differential
RS422, input selectable, with a maximum input frequency of 1.65 MHz.
5.3.3.6 Serial Interface
Two serial Universal Asynchronous Receiver and Transmitter (UART), one with
RS232 and the other, selectable, RS422/RS485 transceiver mode are also
present.
5.3.4 Measurement Filter
The prototype of the 2 nd order low-pass Butterworth measurement filter,
discussed in Section-3.4.8, is shown in Figure-5.13. The electronic circuit
equivalent to the transfer function H f of the 2 nd order filter, given in Equation
(5.10), is shown in Figure-5.14. OP07 is the operational amplifier used.
H
f
( s )
1
= (5.10)
⎛ C f 1C
f 2
⎞ ⎛ 1 1 ⎞
⎜ ⎟ 2
s + C ⎜
f 2 + ⎟s
+ 1
G f 1G
f 2 G f 2 G
⎝ ⎠ ⎝
f 1 ⎠
Gf1 and Gf2 are the respective conductance of resistors Rf1 and Rf2 while Cf1 and Cf2
are the capacitance values. This transfer function form implies that as long as the
5-15

atio between the reactance and the resistance is maintained, the frequency
response will remain the same [Maxim 2003]. This will help in adjusting the
values of components.
Figure 5.13 – The measurement filter.
Figure 5.14 – Circuit of the 2 nd order low-pass filter.
Equation (3.11) can be rearranged to the form of Equation (5.10). A comparison
of the corresponding coefficients of s, in the denominator of the two functions,
yields the components values. With the resistor values chosen to be R f1 = R f2 = 1
kΩ, the capacitance values are found to be C f1 = 450 nF and C f2 = 225 nF. Using
standard values of capacitors C f1 = 470 nF and C f2 = 220 nF, the cut-off frequency
is recalculated to be 494.95 Hz which is close enough to the design value of 500
Hz.
The delay and the attenuation introduced by the realized filter are given in
Table-5.4 measured using the HAMEG 8030-5 function generator. For rotor
electrical frequencies, maximum 6 Hz at s = -0.12, the delay is not noticeable even
when observed with an oscilloscope.
Table 5.4 – Performance of the realized measurement filter with a sinusoidal
input signal of 10 V peak value using HAMEG 8030-5 function generator.
Test No.
Input Frequency Time Delay Output Voltage
[ Hz ]
[ ms ]
[ V ]
1 5 0 10
2 50 0.4 10
3 500 0.5 7
5-16

5.4 Conclusions
This chapter has introduced the components related to the developed DFIG
based WTGS test bench. Component dimensioning has also been discussed.
Complete details of the fabricated chariots such as the protection circuits and
wiring schematics can be found in the user’s manual attached as Appendix-D.
5-17

Chapter 6
Experimental Results
This chapter describes the tests to determine parameter values of components
and the experiments carried out on the test bench. It is organized such that
Section-6.1 discusses the estimation of grid impedance, DFIG electrical circuit
parameters and the delay of the converter. The experiments reported in Section-
6.2 and Section-6.3 are in the context of DFIG start-up, discussed in Section-3.7.
Section-6.2 demonstrates the operation of the GSC, with the charging of the DClink
capacitor and controller performance for reference tracking, disturbance
rejection and reactive power generation. Section-6.3 follows the start-up steps of
stator voltage generation, phase difference minimization and grid
synchronization. A grid line voltage of 220 V is used. The simplified phase
difference minimization technique, developed in Section-3.7.2.1, and the
harmonic suppression property of the control system, highlighted in Section-
4.2.3, are shown to work in reality. The stand-alone operation of the generator is
also tested to determine the performance of the voltage controller. An
investigation into the erroneous oscillations observed in the RSC operation is
carried out in Section-6.4. Section-6.5 is a brief treatment of the stator current
frequency harmonics, for the rewound machine in the motor mode, to
demonstrate the ones most affected by the winding asymmetry. Finally, some
conclusions are drawn in Section-6.6.
6.1 Parameter Estimation Tests
The parameter values of interest need to be determined for simulations, to
decide the controller gains and to account for non-ideal factors such as the
converter delay.
6.1.1 Grid Impedance Estimation
In order to make simulations representative of the test bench, measurements to
ascertain the grid impedance have been carried out. The three-phase Dy11
distribution transformer in the laboratory is rated at 100 kVA, 380 V/500 V and
50 Hz. The test circuit layout is presented in Figure-6.1. The voltage at the
secondary side of the transformer can be changed in steps of 20 V. The
measurements have been carried out at a line voltage of 100 V and maximum 86
A, to avoid exceeding the rated voltage limits of the devices used to load the
transformer and to respect the transformer fuse limit of 100 A. V o, Z T and Z L
represent the open-circuit voltage, the transformer impedance and the
impedance of the load respectively.
Figure-6.2 plots the measurements carried out on the secondary side of the
transformer. Two types of load were used for the test. R L represents the lighting
load, which is predominantly resistive. It consists of 110 V, 115 W lamps, a
maximum of 60 in each phase. X L is predominantly inductive and consists of
three banks. Each bank is made up of three 25.68 mH inductances, which are
delta-connected. Each bank is rated at 4500 VA, 50 Hz, Y 190 V / ∆ 110 V, Y 13.6 A
6-1

∆ 23.6 A, cosΦ = 0.05. Therefore, the calculated impedance per phase of a bank
is 0.401 + i8.056 Ω.
Figure 6.1 – Circuit layout to measure the grid impedance.
Figure 6.2 – Voltage regulation of the grid transformer.
An almost linear voltage reduction with a similar slope is observed for the two
cases. The transformer per-phase impedance is calculated to be 0.018 Ω and the
total three-phase short-circuit power S kg at 100 V is therefore 586.8 kVA.
6.1.2 Machine Parameter Estimation
The equivalent circuit parameters of the rewound DFIG have been determined
by the classical no-load, blocked-rotor and DC resistance tests [Chapman 1999].
The name plate data of the DFIG are given in Table-5.2. For the no-load test, the
emulator motor could not be decoupled from the DFIG since the speed
measurement is given by the inline torque meter. For this reason the slip is
larger. The rotor is short-circuited via a liquid rheostat and the stator is fed from
the grid. The no-load measurements have been recorded in plots of Figure-6.3,
where the measurement corresponding to the rated phase-neutral voltage of 220
V is marked. Figure-6.3(a) to Figure-6.3(f) present the stator current, the slip, the
rotor current, the per-phase active power, the per-phase reactive power and the
6-2

estimated rotational losses respectively. Below 100 V, the slip is already quite
large to assume the rotor as an open-circuit.
(a)
(b)
(c)
(d)
(e)
(f)
Figure 6.3 – No-load test on the rewound DFIG to determine equivalent circuit
parameters. (a) Stator current. (b) Slip. (c) Rotor current. (d) Active power perphase.
(e) Reactive power per-phase. (f) Estimated rotational losses.
Table 6.1 – Blocked-rotor test on the rewound DFIG to determine equivalent
circuit parameters.
Stator
Voltage
[ V ]
Stator
Current
[ A ]
Active
Power
[ W ]
Reactive
Power
[ VAr ]
Rotor
Current
[ A ]
Rotor
Speed
[ rpm ]
22.1 16.35 185.8 315 28.85 0.0
6-3

Figure 6.4 – The calculated magnetizing inductance of the rewound DFIG.
Table 6.2 – The estimated electrical parameter values of the rewound DFIG
determined with classical tests (referred to the stator).
Stator
Resistance
R s [Ω]
Stator
Leakage
Inductance
Lls [mH]
Magnetizing
Inductance
L m [mH]
Rotor
Leakage
Inductance
Llr [mH]
Rotor
Resistance
R r [Ω]
0.37 1.90 62.03 1.90 0.28
The blocked-rotor test, Table-6.1, has been performed for a stator current lower
than rated, since the applied line voltage could only be increased in steps of 20 V.
The magnetizing inductance curve, determined from the tests, is shown in
Figure-6.4. Finally, the determined parameter values, referred to the stator, of
the electrical equivalent circuit are given in Table-6.2.
6.1.3 Converter Delay
The consequences of converter and control system delay are readily apparent
when synchronization has to be carried out with the grid. This delay causes a
current flow, as soon as the converter function is enabled, which activates either
the DC-link over-voltage protection or the over-current protection. Figure-6.5
shows the typical delays of components in the test bench obtained from the
datasheets. It includes the delay to generate the voltage, the delay of the
measurement transducer and the delay of the ADC. The components are: the
buffer GD74LS07, the driver SKHI 22 A, the IGBT module SKM50GB123D, the
voltage transducer LEM LV-100 and the ADC of DS1104 [Datasheet4U n.d.]
[SEMIKRON 2008] [SEMIKRON 2006] [LEM n.d.] [dSPACE 2011]. t PLH, t PHL, t r, t f
and T dt represent the propagation time for low to high logic, high to low logic,
rise time, fall time and the dead time respectively.
Two types of tests have been carried out to determine the source and the
dependence of the system delay. In one type, the sampling and the switching
frequency are changed while a 50 Hz reference signal is given to the converter.
6-4

For the other type, the frequency of the reference signal is changed while the
sampling and the switching frequency are kept the same. These tests determine
the total system delay, starting from reference generation by the control system.
Figure 6.5 – System delay for generation of voltage through the converter.
The total system delay T sd is determined experimentally in the form of phase
difference θ diff, by recording both the reference voltage and the measured
converter voltage in steady-state and doing an FFT on both. The equivalent time
to the phase difference, for the reference voltage frequency f ref, is found using
Equation (6.1a). The results of the tests are given in Table-6.3 and Table-6.4. It
can be seen that the major contributor to the total system delay is the selected
switching frequency. When the switching frequency is doubled, keeping the same
sampling frequency, the phase difference reduces almost by half. The net system
delay, apart from the converter, is approximated by subtracting the switching
time period T sw from T sd. It can also be seen that the net system delay is affected
by the sampling frequency.
Table 6.3 – System delay with different sampling and switching frequencies
at the reference voltage frequency fref = 50 Hz.
Test No.
Sampling
Frequency
[ Hz ]
Switching
Frequency
[ Hz ]
Switching
Time
Period
Tsw
Phase
Difference
θ diff
[ ° ]
Equivalent
Time
Delay
Tsd
Net
System
Delay
[ ms ]
[ ms ]
[ ms ]
1 7500 750 1.33 26.3 1.46 0.13
2 7500 1500 0.67 14.3 0.79 0.13
3 15000 1500 0.67 13.6 0.76 0.09
4 15000 750 1.33 25.6 1.42 0.09
Table 6.4 – System delay at different frequencies f ref for reference voltage
with 1.25 kHz switching and 10 kHz sampling frequency.
Test No.
Frequency of
the Reference
Signal fref
[ Hz ]
Phase
Difference
θdiff
Equivalent
Time Delay T sd
[ ms ]
Net
System Delay
[ ms ]
[ ° ]
1 6 1.98 0.92 0.12
2 12 4.01 0.93 0.13
3 24 7.88 0.91 0.11
4 50 16.33 0.91 0.11
6-5

T
sd
θdiff
1
= .
(6.1a)
360 f
ref
T
sd
Ts
+ 2Tsw
= (6.1b)
2
The average total system delay can also be approximated by Equation (6.1b),
provided the delay introduced by the components apart from the converter is
small. Consider Figure-6.6, which has been adapted from [le Roux & van Wyk
2000]. The reference voltage amplitude and the step-wise output, fundamentalfrequency
voltage amplitude, from the converter can be seen. The instants when
the reference voltage is sampled are marked, on the time axis, with solid vertical
lines while the instants when the converter generates the corresponding output
are marked with dashed vertical lines.
Figure 6.6 – Approximation of total system delay Tsd [le Roux & van Wyk 2000].
The converter delay is compensated by adding an equivalent angle to the angle
used for the dq-abc conversion of the control voltage output [Park & Kwon 2004]
[Kuperman, Rabinovici & Zhong 2004]. This way the initial large current
transient is avoided. Thus the converter can be connected to the grid.
Afterwards, the current control implicitly nullifies this angle by modifying the
reference voltages in response to the current observed.
The switching waveforms are presented in Figure-6.7(a). The first two plots are
the switching signals, for the top and bottom IGBTs of a branch, sent to the
drivers. The last plot is the corresponding phase voltage at the output of the
converter, measured w.r.t. the negative terminal of the DC-link. This figure is
redrawn from the observation made using an oscilloscope, at a switching
frequency of 1.25 kHz with 325 V at the DC-link. Figure-6.7(b) shows a typical
6-6

charging of the gate-emitter circuit of an IGBT [Sargos 2008]. This is the output
of the driver. The gate resistor along with the, IGBT characteristic, gate
capacitance can be approximated as an RC circuit. The gate resistor is used to
improve the Electro-Magnetic Compatibility (EMC) performance and limit the
rate of gate current and consequently the over-voltage due to parasitic
inductance but causes switching losses.
(a)
(b)
Figure 6.7 – Converter switching.
(a) Input switching signal and the converter output.
(b) A typical driver output waveform [Sargos 2008].
The CMOS compatible IGBT drivers have the following characteristics, related to
the switching performance [SEMIKRON 2008]:
6-7

• The maximum and minimum input thresholds are 12.5 V and 4.7 V for the
high and low logic respectively.
• The maximum input to output turn-on and turn-off propagation time
delay is 1.15 μs.
• An IGBT interlock dead-time of 3.3 – 4.3 μs is inserted by default and
cannot be changed.
• The maximum frequency for the input switching signal is 50 kHz.
6.2 Grid-Side Converter Operation
This section discusses the performance of the GSC control. Tests for reference
tracking, disturbance rejection and reactive power generation are carried out. A
comparison between simulation and experimental results is also provided,
where some difference is observed between the two despite efforts to model the
system as accurately as possible. These differences can be due to the values
assumed for components in simulations. For example, the actual value of ESR
and the impedance of cables used to connect different components are not
known. Nevertheless, the system model is close enough to the real setup to allow
the use of same controller gains. The schematic of the GSC control part, from the
overall DFIG system, is shown in Figure-6.8. Figure-6.8(a) shows the layout of
the test setup components while Figure-6.8(b) shows the control system layout.
The switching frequency is 1950 Hz or 39 p.u., while the sampling frequency is
3900 Hz or 78 p.u. The compensation angle for converter delay is 13˚, determined
experimentally for the sampling and switching frequency used. The gains of the
PI controllers are found in Table-3.3.
The component values used in simulations are repeated here: Lf = 6 mH, Rf = 0.1
Ω, C 1 = C 2 = 2C DC = 2200 μF, R DC = 0.03 Ω, R vsr1 = R vsr2 = 22 kΩ, S kg = 586.8 kVA and
the DC-link charging resistors R ch = 330 Ω. The actual X/R ratio of the grid is not
known, thus for simulations a value of 2, 5, 7 and 9 was taken. The measurement
noise has not been considered to observe the differences clearly. In general, the
X/R ratio of transformers increases with their power rating. An X/R value of 7 is
the default value suggested by SimPowerSystems while an X/R value of 2 was
taken from the ANSI Standard C37.010 for a 100 kVA power transformer
[Arcadvisor n.d.].
Currrent
Source
+
s
-
i
+ -
C1
C2
Switch
+
-
IdcRSC
v
Rvsr
1
Rvsr
2
Vdc
pulses
g
+
A
B
-
C
GSC
Current
Measurement
A
Vabc
Iabc
B a
b
C
c
A
B
C
If
A
B
C
Filter Inductance
Lf = 6 mH
Grid Voltage
Measurement
Va Van
Vb
Vc
Vbn
n
Vcn
Contactor
A
B
C
A
B
C
a
b
c
A
B
C
Charging
Resistance
Rch = 330 Ohm
A
B
C
Vgrid
N
Grid
220 V, 50 Hz
Skg = 586.8 kVA
Idc
RSC1
Step
Idc
RSC2
(a)
6-8

Step
1
Vdc*
2
Vdc*
1
PLL
Enable
Vgrid_ac
Vgrid_bc
Grid
Voltage
Measurement
Switch
1
Vac
Vbc
Ifa
Ifb
Ifc
Step
2
Current
Measurement
PLL
Ifd*
2
Ifd*
1
Switch
2
ifa
Ifd
ifb
ifc
thetaPLL
Ifq
(a,b,c)--> (d,q)
Power Invariant
Vd,grid
Vq,grid
thetaPLL
fPLL
Ifd*
Vdc*
Ifd
Ifq
Vd,grid
Vq,grid
thetaPLL
Vfa
Vfb
Vfc
Control
On/Off
SVM_PWM
Vfa
Vfb
Vfc
Vdc
PWM
On/Off
DC_a
DC_b
DC_c
DC_a
DC_b
DC_c
PWM Stop
Pulses
DS1104SL_DSP_PWM
pulses
Vdc
Vdc
Vector Control
(b)
Figure 6.8 – Schematic of the GSC system. (a) Test setup. (b) Control system.
Figure 6.9 – GUI for the GSC control in dSPACE Control Desk software.
Figure-6.9 shows the Graphic User Interface (GUI) developed in dSPACE Control
Desk software. The experiment can be controlled in steps using the On/Off
buttons. The status of I/O can be seen and the captured variables displayed. The
6-9

layout is divided into different sections, like the ‘start-up’ to charge the DC-link
capacitors via the anti-parallel diodes of the GSC, the ‘vector control’ to boost the
DC-link voltage to the operational level and the ‘acquisition’ section to control
how the data is acquired.
6.2.1 Reference Tracking
The reference tracking performance is tested through charging of the DC-link
capacitors up to the operational DC voltage of 380 V. Figure-6.10 presents the
experimental results of the charging process and the performance of the PLL. At
time t = 1 s, capacitor charging begins via the charging resistors. The resistors are
shorted out at t = 12 s and the DC-link voltage achieves the nominal value of
about 320 V for the grid voltage of 225 V, see Figure-6.10(a). The PLL is enabled
at t = 13 s and its recorded output is shown in Figure-6.10(c). At t = 15 s, the
control system is enabled with a reference voltage of 320 V for the DC-link. A
transient is observed in the DC-link voltage when this is done. This is due to
small error between the reference and the measured value resulting from the
measurement noise, for example. After t = 18 s, the reference voltage is stepped
up to 380 V and at around t = 23 s it is stepped down to 320 V again. The currents
measured on the grid side are shown in Figure-6.10(b) and Figure-6.10(d). It is
seen in the close-up provided that although the currents are periodic they are
dominated by harmonics. The current harmonic content is presented in Figure-
6.10(e), where the harmonic magnitudes Ih are reported with respect to the
magnitude I1, of the 50 Hz fundamental frequency component, and the numbers
indicate the harmonic order.
(a)
(b)
(c)
(d)
6-10

(e)
Figure 6.10 – DC-link capacitor charging. (a) Capacitor voltage. (b) Filter
currents. (c) PLL output. (d) Filter currents – close-up. (e) FFT i fb.
A comparison between experiments and simulations is presented in Figure-6.11.
The experimental results are in the left-hand column while the simulations are in
the right-hand column. Figure-6.11(a) is a close-up of Figure-6.10(a) and focuses
on the time during which the control is ON. In Figure-6.11(b), two cases are
presented. For X/R = 2, the controller is already ON when a step change, at t = 1 s
from 320 V to 380 V, in voltage reference is made. For all others, the controller is
turned ON with 380 V as reference. It can be seen that the overshoot is larger in
the latter case. It is due to the fact that it takes some time for the controller to
establish the right voltages as reference to the converter since the initial
condition for the integrators of the PIs is zero. A similar observation, for the
same application, has been reported in literature with 1.5 p.u. current flow due to
the control system delay [Teodorescu et al. 2003]. This is easily understood,
since the grid can readily source current while the response time of the control
system to achieve the proper converter voltage, to limit this current, is larger.
The reference is achieved in about 200 ms.
Figure-6.11(c), (d) and Figure-6.11(e), (f) provide the comparison for ifq and ifd
current components respectively. For the experiments, the increased oscillations
in the dq component currents in steady state are due to offset errors of the
transducers and measurement noise. For the simulations, there is only a slight
difference in the reference tracking performance for different X/R ratios where a
larger overshoot is seen for a higher value of the ratio, see Figure-6.11(b).
(a)
(b)
6-11

(c)
(d)
(e)
(f)
Figure 6.11 – Comparison between experiment (left-hand column) and
simulation (right-hand column) for reference tracking performance of the GSC
control.
(a) and (b) DC-link voltage. (c) and (d) ifq. (e) and (f) ifd.
6.2.2 Disturbance Rejection
The disturbance rejection performance is tested by connecting a load at the DClink.
For the experiments, a resistive load consisting of lamps while for the
simulations a controlled current source, shown in Figure-6.8(a), is used. A
current of 3.15 A is drawn at the operational DC-link voltage of 380 V. The
disconnection of this load is equivalent to the injection of current in the DC-link,
from the RSC. It corresponds to a power injection of 1197 W. Figure-6.12
presents the disturbance rejection test. The experimental results are in the lefthand
column while the simulations are in the right-hand column.
(a)
6-12

(b)
(c)
(d)
(e)
(f)
(g)
(h)
6-13

(i)
Figure 6.12 – Comparison between experiment (left-hand column) and
simulation (right-hand column) for disturbance rejection performance of the GSC
control.
(a) Lamp load current. (b) and (c) DC-link voltage. (d) and (e) i fq. (f) and (g) i fd.
(h) Filter currents. (i) FFT i fb.
Figure-6.12(a) shows the lamp load current. A circuit breaker is used as a switch
to manually connect and disconnect the load. Therefore, the connection is not
instantaneous due to the spring loaded mechanism. The simulations are started
with a DC-link voltage of 380 V. At t = 0.1 s, the control is enabled and a transient
can be seen. The load is connected at t = 1.3 s and disconnected at t = 4 s. For the
experiments, the load was connected and disconnected at t = 3 s and t = 8.5 s
respectively. A comparison of Figure-6.12(b) and Figure-6.12(c) indicates a
notable difference in the DC-link voltage waveforms. The X/R ratio does not
seem to make much difference in these simulations. The filter currents are
shown in Figure-6.12(h) and the harmonic content is presented in Figure-6.12(i).
6.2.3 Reactive Power Generation
The current control loop performance has been tested by injecting reactive
power into the grid. A step change in i fd from 0 A to 9 A is made at the DC-link
voltage of 380 V. This is equivalent to an injection of about 2 kVAr. Figure-6.13
presents the comparison for reactive power injection into the grid. Here a
significant difference is observed for the DC-link voltage comparison shown in
Figure-6.13(c) and Figure-6.13(d). Figure-6.13(g) shows the filter currents while
Figure-6.13(h) shows the current harmonic content.
(a)
(b)
6-14

(c)
(d)
(e)
(f)
(g)
(h)
Figure 6.13 – Comparison between experiment (left-hand column) and
simulation (right-hand column) for reactive power generation performance of
the GSC control. (a) and (b) ifd. (c) and (d) DC-link voltage. (e) and (f) ifq.
(g) Filter currents. (h) FFT ifb.
6-15

6.3 Rotor-Side Converter Operation
The schematic of the RSC control part, from the overall DFIG system, is shown in
Figure-6.14. Figure-6.14(a) shows the layout of the test setup components while
Figure-6.14(b) shows the control system layout. The voltage source shown on
the DC-link in Figure-6.14(a) signifies that the voltage is maintained constant
either through the GSC or the diode bridge rectifier supplied from the grid.
Figure-6.15 shows the GUI developed in dSPACE Control Desk software. The
experiment can be controlled in steps using the On/Off buttons. The status of I/O
can be seen and the captured variables displayed. The layout is divided into
different sections, like the ‘start-up’ to measure the grid voltages and activate the
PLL, the ‘vector control’ section for stator voltage generation and
synchronization with the grid etc.
A
N B
C
Grid
220 V,
50 Hz
Grid Voltage
Measurement
A
B
C
Vabc
a
b
c
A
B
C
Vgrid
Contactor
Is
Vs
A
Vabc
a Iabc
b
c
B
C
a
b
c
Stator Output
Measurement
Speed
Speed
w
A
B
C
DFIG
m
a
b
c
Ir
A
Vabc
Iabc
B a
b
C
c
Rotor Current
Measurement
pulses
g
+
A
B
-
C
RSC
Vdc
v + -
C1
C2
Rvsr
1
Rvsr
2
(a)
Ps*
2
Ps*
Qs*
Measurements
Step
1
Ps*
1
Qs*
2
Switch
1
Control
On/Off
Ir
Vs
Is
Ir
Vs
Is
Current Control Enable
Var
SVM_PWM
pulses
Step
2
PLL
Enable
Qs*
1
Vac,grid
Vbc,grid
Grid
Voltage
Measurement
Switch
2
Vac
Vbc
Control
On/Off2
Control
On/Off1
PLL
Vd,grid
Vq,grid
thetaPLL
fPLL
Control
On/Off3
Speed
poz_error_enable
Voltage Control Enable
Power Control enable
Vd,grid
Vq,grid
thetaPLL
fPLL
Speed
Vbr
Vcr
Var
Vbr
Vcr
Vdc
PWM
On/Off
DC_a
DC_b
DC_c
DC_a
DC_b
DC_c
PWM Stop
Pulses
DS1104SL_DSP_PWM
Vdc
Vdc
Control System
(b)
Figure 6.14 – Schematic of the RSC system. (a) Test setup. (b) Control system.
6-16

Figure 6.15 – GUI for the RSC control in dSPACE Control Desk software.
As mentioned at the beginning of this chapter, the RSC operation has some
problems. Erroneous periodic oscillations are observed as shown in the next
section. Nevertheless, the tests done show that the steps defined in Section-3.7.2
for DFIG start-up are indeed valid. Furthermore, same parameter and gain values
are applicable here. The results of the investigation carried out to isolate the
cause or determine the conditions under which this oscillation problem occurs
are reported in Section-6.4. The sample-and-hold technique presented in
Section-3.7.2.1, to minimize the phase difference between the stator and the grid
voltage due to the unknown position of the rotor when the control is activated, is
tested here experimentally. It has not been found in the consulted literature and
is a contribution of this thesis.
6.3.1 Generation of Stator Voltage and Synchronization with the Grid
This section corresponds to the discussion in Section-3.7.2 regarding the
generation of stator voltages, correction of the initial rotor position error and the
synchronization of stator voltage to the grid before connection. The results of the
same experiment have been divided into Figure-6.16 and Figure-6.17 to make
the commentary easier. The sampling and switching frequency are both 1950 Hz
while the bandwidth of the current and voltage control loop is 0.07 p.u. and 0.007
p.u. respectively on a 50 Hz basis, as used for simulations in Section-3.7.
6-17

(a)
(b)
(c)
(d)
(e)
(f)
(g)
Figure 6.16 – Stator voltage generation and rotor position error correction.
(a) Rotor dq currents close-up. (b) Stator and grid dq voltages close-up.
(c) Speed. (d) Stator and grid dq voltages. (e) Rotor dq currents.
(f) Correction angle. (g) Synchronized stator and grid voltages.
6-18

6.3.1.1 Generation of Stator Voltages and Angle Correction
This section focuses on the generation of stator voltages through closed-loop
rotor current control and the correction of initial error due to the unknown rotor
position at the start of the experiment. The experiment starts with the DFIG
being rotated by the grid-fed emulator motor near synchronous speed as seen in
Figure-6.16(c). The rotor current control is enabled at t = 3.45 s and the speed
drops due to an opposing torque exerted by the DFIG. Although the stator
terminals are open, the rotor flux causes currents in the stator core.
The reference for irq is zero while the reference for ird is -10.3 A or 0.15 p.u. on a
15 kW, 220 V basis. The performance of the current control loop is shown in
Figure-6.16(a) where the reference is achieved within 350 ms. The generated
stator voltages in the dq form are seen in Figure-6.16(b) and (d). It is seen that
there is a difference between the stator and the reference grid voltages, in the dq
form. This is due to phase error caused by the initial unknown rotor position.
These figures can be compared to Figure-3.27(b) in terms of the settling time for
the generated stator voltages. The phase angle error θ corr, shown in Figure-
6.16(f), is corrected at around t = 28 s. A transient is seen in the dq rotor currents
shown in Figure-6.16(e). The result of this corrective action is seen in Figure-
6.16(g) where the stator voltage becomes almost in phase with that of the grid.
6.3.1.2 Stator Voltage Control
In order to ensure perfect synchronization before the stator is connected to the
grid, the control is handed over to the voltage control loop around t = 38 s. This is
evident from Figure-6.16(e) where the current reference starts varying under
the control of the external voltage loop. The nature of the erroneous periodic
oscillation changes and it becomes bidirectional. This can be seen in Figure-
6.16(d), (e) and (f). In principle, the stator is now ready to be connected to the
grid provided these oscillations are not present.
6.3.1.3 Harmonic Suppression
One contribution of this work is to lay emphasis on the fact that the control
system tends to suppress harmonics in the current. This is the argument in
Chapter-4 where fault detection based on negative-sequence current is favoured
as a result of the frequency harmonic and symmetrical component analysis
carried out on the currents for stator winding short-circuit faults. The
suppression of harmonics could be due to the use of Park’s transformation which
is based on the assumption of perfect symmetry in the phases and a principal
frequency on the respective stator and rotor side which converts the alternating
three-phase quantities to DC values on the rotating dq reference frame. Any
deviation from the DC reference values amounts to a deviation from the pure
sinusoid and thus leads to control action, thereby suppressing the harmonics.
The suppression of harmonics is illustrated in Figure-6.17, which is part of the
same experiment as Figure-6.16. It can be seen in Figure-6.17(a) that the rotor
currents are sinusoidal, as compared to those seen in Figure-6.21(c) for the
open-loop operation, see Section-6.4.2. The references to the converter are
modified by the control system to achieve this. This is evident when the duty
cycles in the two cases are compared; see Figure-6.17(b) and Figure-6.21(b). The
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control voltages are shown in Figure-6.17(c) and (d), which should normally be
sinusoidal and constant DC values respectively.
(a)
(b)
(c)
(d)
Figure 6.17 – Suppression of current harmonics by the control system.
(a) Rotor currents. (b) Duty cycles. (c) Control voltages in abc.
(d) Control voltages in dq.
6.3.2 Stand-alone Generator Operation
Tests are done for the stand-alone operation to check the performance of the
control system for the stator voltage control objective. Since the stator can not be
connected to the grid due to the oscillation problem, this test was done instead to
create a disturbance at the stator terminals in terms of current flow. In standalone
operation, the generator has to maintain voltage and frequency for the load
connected to its terminals. In steady-state, the derivative terms in Equation
(3.1a) and Equation (3.1b) are zero since the fluxes are constant. Expressing
these equations in terms of currents gives
v
sd
= −R
i + ω L i − ω L i
(6.2a)
s sd
d
s sq
d
m rq
v
sq
= −R
i − ω L i + ω L i
(6.2b)
s sq
d
s sd
d
m rd
With the stator voltage vector aligned with the q axis, vsd = 0, and Rs ≈ 0 as before,
the same relation for stator isq current and active power is obtained as given in
Equation (3.45a) and Equation (3.46a) respectively. irq is related to isq by a
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constant factor L m/L s. Thus i rq will cater to the active power demand of the load.
The current i rd will fulfil the reactive power demand of the DFIG and the load. If
there is no reactive power exchange at the stator terminals then the same
relation is obtained as Equation (3.40) with v sq maintained by i rd. Thus the value
of i rd will remain the same in steady-state, as before the connection of load.
Figure-6.18 presents the results of this test. In this experiment, a higher
bandwidth 0.25 p.u. for the current control loop is used since the stator is not
going to be connected to the grid. The test starts with the DFIG being rotated by
the grid-fed emulator motor as shown in Figure-6.18(c). The rotor current
control is enabled around t = 1 s. The rotor dq currents and the generated stator
dq voltages are given in Figure-6.18(a) and Figure-6.18(b) respectively. The
three-phase rotor currents, stator line voltages and phase currents are presented
in Figure-6.18(d), (e) and (f) respectively.
At t = 8 s, the initial rotor position angle is corrected. This is actually not required
here since the generator is working in the stand-alone mode without requiring
any synchronization with the grid. The correction angle and the corrected slip
angle are shown in Figure-6.18(k) and Figure-6.18(l) respectively. It confirms
again that the sample-and-hold technique is working satisfactorily.
The stator voltage control is enabled at t = 16 s and therefore the stator voltage,
Figure-6.18(b), comes in phase with the reference. The reference is given as a
constant voltage with 50 Hz frequency rather than through a PLL working on the
grid.
(a)
(b)
(c)
(d)
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(e)
(f)
(g)
(h)
(i)
(j)
(k)
(l)
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(m)
(n)
Figure 6.18 – Stand-alone operation of the DFIG.
(a) Rotor dq currents. (b) Stator dq voltages. (c) Speed. (d) Rotor abc
currents. (e) Stator abc voltages (f) Stator abc currents. (g) Stator active and
reactive power (h) Rotor dq voltages. (i) Rotor abc voltages. (j) Duty cycles.
(k) Correction angle. (l) Slip angle. (m) Stator abc voltages close-up.
(n) Stator abc currents close-up.
At t = 22 s, a resistive load consisting of lamps is connected to the stator
terminals of the DFIG. The DFIG works as a generator supplying a total power of
2500 W to the load as shown in Figure-6.18(g). The slip of the DFIG increases
which leads to an increased frequency for rotor related quantities shown in
Figure-6.18(d), (h), (i), (j) and (l). Finally, a close-up of the stator voltages and
currents is provided in Figure-6.18(m) and Figure-6.18(n) respectively when the
load is connected.
6.3.2.1 Frequency Harmonic Analysis
A close-up of the steady-state stator voltages and currents is presented in Figure-
6.19(a) and Figure-6.19(b) respectively. Since they have been low-pass filtered
with a cut-off frequency of 500 Hz, the harmonics with a lower frequency are not
affected. The harmonic analysis of the stator currents i as and i bs, given in Figure-
6.19(c) and (d) respectively, shows that the harmonic content is very low. The
same can be observed for the stator voltage harmonics in Figure-6.19(e) and (f).
Harmonic analysis on the generated stator voltage and currents shows that the
fundamental frequency is indeed 50 Hz. It can be concluded that the developed
control system works well.
(a)
(b)
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(c)
(d)
(e)
(f)
Figure 6.19 – Harmonic analysis of stator currents and voltages in stand-alone
generator mode.
(a) Stator line voltages close-up. (b) Stator phase currents close-up.
(c) FFT ias. (d) FFT ibs. (e) FFT vac,stator. (f) FFT vbc,stator.
6.4 Tests to Determine the Cause of the RSC Problem
6.4.1 DFIG Rotor Balance
First test is to determine if the DFIG rotor phases are balanced. For this, the rotor
is fed from the grid with a line voltage at 60 V, 50 Hz.
Figure 6.20 – Imposed grid voltage and the resulting currents measured in the
rotor.
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The DFIG is not rotating during this test and the stator terminals are opencircuited.
The sampling frequency is 1950 Hz. The measured voltages and the
currents are shown in Figure-6.20. It is clear that the rotor phases are balanced.
6.4.2 Open-Loop Test
The same test reported in Section-6.4.1 is repeated with the rotor now supplied
through the converter in order to observe the currents. The stator terminals are
open circuited, as before. Both the sampling and switching frequency are 1950
Hz. A constant voltage reference is imposed on the converter, without activating
the control. It is given in the dq form and the slip angle is used for the dq to abc
transformation, in order to obtain the three-phase reference voltages for the
converter. The speed is measured and the PLL is used to obtain the grid angle,
for subsequent calculation of the slip angle. The DFIG is rotated by the emulator
motor that is fed directly from the grid.
(a)
(b)
(c)
(d)
(e)
(f)
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(g)
(h)
Figure 6.21 – Open-loop test to observe rotor currents when supplied from the
converter. (a) Speed. (b) Duty-cycles. (c) Rotor phase currents.
(d) Stator line voltages. (e) Slip angle. (f) Rotor dq currents.
(g) Stator and grid dq voltages. (h) DC-link voltage.
Figure-6.21 presents the measurements from this experiment. Figure-6.21(a)
shows the speed of the coupled machines. The grid supplied emulator motor is
turned ON around t = 18 s and OFF at t = 62 s. The form of the imposed duty
cycles, Figure-6.21(b), is ideal. The resulting rotor currents, however, are
severely distorted; see Figure-6.21(c). The waveform is the result of a 5 th
harmonic superimposed with a phase shift of 180˚ on the fundamental frequency
current. As a consequence, the generated stator voltage shown in Figure-6.21(d)
is also distorted and has an envelope form. The large oscillations observed in the
stator voltage before and after the machine is rotating could not be explained.
The slip angle is shown in Figure-6.21(e), while the rotor currents and the stator
voltages in dq form are shown in Figure-6.21(f) and (g) respectively. Finally, the
DC-link voltage is shown in Figure-6.21(h), where a slight reduction is seen in
the loaded condition.
6.4.3 Closed-loop Test
The closed-loop test is done to observe the effect of control bandwidth.
Increasing the bandwidth of current control gives an improvement but then the
system becomes unstable when connection to the grid is effected. Figure-6.22
compares two cases with bandwidths of 0.04 p.u. and 0.25 p.u. on left-hand and
right-hand columns respectively. The bandwidth of the outer voltage control
loop is 10 times less for both the cases. It is seen that with a higher bandwidth
the situation is improved. The magnitude of oscillations in the rotor dq currents
and stator dq voltages is less as can be seen in Figure-6.22(b) and Figure-6.22(d)
respectively. The rotor three-phase currents shown in Figure-6.22(f) are also
more sinusoidal.
The good performance of the developed sample-and-hold technique, for initial
rotor position error correction, is evident from Figure-6.22(c) and (d) where the
phase error with the grid voltage is minimized no matter what the initial position
of the rotor.
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(a)
(b)
(c)
(d)
(e)
(f)
Figure 6.22 – Effect of increasing the current control bandwidth on the
problematic oscillations.
Bandwidth: 0.04 p.u. (left-hand column), 0.25 p.u. (right-hand column)
(a) and (b) Rotor dq currents. (c) and (d) Stator dq voltages.
(e) and (f) Rotor three-phase currents.
6.4.4 Conclusion of the Investigation
Investigation into the cause of the problem reveals that the oscillations occur
when the rate of change of the duty cycle is large as can be seen in Figure-6.23.
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Figure 6.23 – Duty cycles and the periodic oscillations.
This figure is for the test reported in Section-6.3.1. At higher slips the oscillations
occur more frequently as can be deduced from the figure. This has also been
verified by operating the emulator motor with a drive at different speeds. Other
steps taken to identify the source of the problem are listed below:
1) Interchanging the chariots to observe if the problem is due to a
component installed in the chariot.
2) Measuring all three rotor currents instead of two.
3) Testing various switching and sampling frequencies.
4) Changing the SVM modulation technique to sinusoidal PWM.
5) Using both the absolute encoder angle and the angle difference between
successive samples (both given by the speed sensor). Also testing
different filters on the measured speed.
6) Changing the solver.
7) Imposing ideal constant magnitude and frequency grid voltages as input
to the PLL.
8) Correcting the offset errors of the current and voltage transducers.
9) Using a diode rectifier to maintain voltage at the DC-link and boosting it
with the GSC.
From the steps mentioned above it has be concluded that the source of the
oscillation problem is not the hardware installed inside the chariot or the
software based control algorithm. It could not be traced to a single component.
However, the speed measurement and/or the switching circuit have to be the
cause of the problem, as concluded from Section-6.4.2.
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6.5 Frequency Harmonic Analysis – Motor Mode
Figure-6.24 presents the recorded data during the uncontrolled motoring mode
of the DFIG. The grid line voltage is 380 V, 50 Hz while the sampling frequency is
1 kHz. Unfortunately, the squirrel-cage induction machine could not be loaded,
thus no-load stator current measurements are analysed. The stator is connected
to the grid around t = 1 s where a large stator current transient is observed as
shown in Figure-6.24(b). When this is done the machine starts rotating due to
currents in the rotor core although the rotor terminals are open-circuited; see
Figure-6.24(a).
(a)
(b)
(c)
Figure 6.24 – Measurements on the DFIG in the motoring mode.
(a) Speed. (b) Stator phase currents. (c) Rotor phase currents.
(a)
(b)
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(c)
(d)
(e)
(f)
Figure 6.25 – Harmonic analysis of stator voltages and currents for the
uncontrolled DFIG with a shorted rotor in the motor mode.
(a) Stator line voltages close-up. (b) Stator phase currents close-up. (c) FFT i as.
(d) FFT i bs. (e) FFT v ac,stator. (f) FFT v bc,stator.
At t = 5 s, the rotor phases are short-circuited slowly via a liquid rheostat and the
machine starts to accelerate rapidly. The rotor currents are given in Figure-
6.24(c). At t = 12.5 s, the rotor is completely short circuited and the machine
achieves near synchronous speed.
The steady-state stator line voltages and phase currents are shown in Figure-
6.25(a) and Figure-6.25(b) respectively. The harmonics in the stator voltage and
current are analysed by FFT. Figure-6.25(c) and Figure-6.25(d) present the
harmonic content of the stator currents ias and ibs respectively while Figure-
6.25(e) and Figure-6.25(f) show the harmonic content of the stator line voltages
vac,stator and vbc,stator respectively. The harmonic magnitudes are reported as
compared to the 50 Hz fundamental frequency magnitude. Since one pole in each
of the two phases of the DFIG stator has been rewound, Section-5.2.5, the
winding asymmetry is exacerbated. It is seen that the 3 rd and the 5 th harmonic in
the stator current are the most affected and have a different magnitude in the
two phases while the stator line voltage harmonics are the same. A similar
observation is reported in Section-4.2.2 for the no-load singly-fed induction
generator, although the modelled machine is different.
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6.6 Conclusions
This chapter has presented parameter estimation tests for the test bench
components and the experiments on the GSC and RSC in the context of DFIG
start-up. The designed controllers have been validated for reference tracking and
disturbance rejection performance. The method developed in Section-3.7.2.1 for
initial rotor position correction has been demonstrated to work in reality. The
harmonic suppression property of the control system has been demonstrated.
The oscillation problem in RSC operation has been extensively investigated and
possible causes have been identified. A test with stand-alone operation of the
DFIG has also been conducted on the side to observe the performance of the
system, although it is not the main objective. Finally, the harmonic content of the
stator currents in the motoring mode is analyzed and it is observed that the 3 rd
and the 5 th harmonic are affected by the winding unbalance, which exists due to
the rewound stator. The same observation was made in Section-4.2.2 when the
developed machine model, to simulate stator winding unbalance due to shortcircuits,
was validated.
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