Ethernet Technology

Some International standard of of P(x) or or G(x)
CRC Error Detection
CRC12:
CRC16:
CRCCCITT:
CRC-32:
P(
x)
x
P(
x)
x
P(
x)
x
12
16
16
P(
x)
x
x
x
+ x
32
x
x
11
15
12
x
11
2
x
+ x
26
x
3
x
2
5
x
10
x
x1
1
+1
23
2
x
8
1
x
22
+ x
x
7
16
x
x
5
12
x
4
• Error detection capability of CRC
- All single-bit error
- All double-bit errors, as long as P(x) has at least three 1’s
- Any odd number of errors, as long as P(x) contains (x+1)
- Any burst error with burst length < length of P(x)
(i.e., the length of FCS)
- Most larger burst error (a small set of bits near a single location)
CRC P x x x x in ATM cell
8 2
8: ( ) 1 ( )
• CRC does not covers preamble and SFD
Ethernet Technology 77
Ethernet Technology 78
• Implementation of CRC by digital logic
(by XOR gates and 1-bit shift registers (SR))
- # of registers = n = the length of the FCS
- # of XOR gates up to n
- the presence (absence) of an XOR
the presence (absence) of a term in P(x)
- All SRs are clocked simultaneously and thus shift along SRs
• General CRC implementation architecture for P(x)
XOR
Input bits
SR
a a a n-1
a n-2 2
1
Multiplier
• Transmitter’s s action:
- Reset all SR = 0 and shift in message one-by-one,
MSB first
- Checksum (FCS) is left in SR after the last data
bit is transmitted
- Shift FCS to channel
• Receiver’s s action:
- Implementing the same H/W as the Txer does
- Rxed data is shifted to the input end and resulted in
R in SR, then R is coming on in
- If SR = 0 no error
-If SR 0 erred
With a 0 = 1, and a n = 1
Ethernet Technology 79
Ethernet Technology 80