Lecture 4: Seven Segment Display - TU Clausthal

Lecture 4: Seven Segment Display
G. Kemnitz ∗ , TU Clausthal, Institute of Computer Science
May 25, 2011
The test board has a four digit seven segment display with combined cathode signals and a
common anode signal per digit, so that in every time interval only one digit can be displayed. To
visualize multiple digits the single digits has to be displayed multiplex, which means one after the
other. In this lecture such a display, where the digits are set by buttons will be developed step by
step.
1 Test of the seven segment display
The seven segment display on the test board has four digits. The cathode signals of all segments
a to g and dp are grouped together to save wires. The four anode signals »AN0« to »AN3« of
each digit are separately available and inverted by transistors between the FPGA and the display
(figure 1). To turn on a display element the corresponding cathode signals, which are a, b, ... and
dp, have to be set to »0« and the corresponding anode signal »AN0«, »AN1«, ... or »AN3« has
to be set also to »0.
sw0
sw1
sw2
sw3
sw4
sw5
sw6
sw7
BTN3
BTN2
BTN1
BTN0
F12
G12
H14
H13
J14
J13
K14
K13
L14
L13
M14
M13
FPGA
a
b
c
d
e
f
g
dp
AN3
AN2
AN1
AN0
E14
G13
N15
P15
R16
F13
N16
P16
E13
F14
G14
D14
0
0
1
0
0
1
0
1
1
1
1
0
seven segment display
a
a
a
f b f b f b f
g
g
g
e c e c e c e
d dp d dp d dp
values to display the number 2 in the most right digit
a
g
d
b
c
dp
Figure 1: Test of the seven segment display
In the first experiment as shown in figure 1, the cathode signals are provides by switches and
the anode signals by buttons and inverters. Design an appropriate architecture description to the
following entity description
entity Test1_Seg7 is
port(sw: in std_logic_vector(7 downto 0);
btn: in std_logic_vector(3 downto 0);
a, b, c, d, e, f, g, dp, AN0, AN1, AN2, AN3: out std_logic);
end entity;
∗ Tel. 05323/727116
1

and the constraint file. Program the circuit in the FPGA on the test board and test it. Fill in
the truth table at the handout sheet for the seven segment decoder in figure 2 and test it with the
programmed circuit.
y 0
y 6 y 1
x 0000 0001 0010 0011 0100 0101 0110 0111
y 5 y
y 4 y 2
y 3 x 1000 1001 1010 1011 1100 1101 1110 1111
y i = 0
y i = 1
y
Figure 2: Function of the seven segment decoder
2 Design of the seven segment decoder
Design a seven segment decoder as a package function:
library ieee;
use ieee.std_logic_1164.all;
package Seg7_pack is
function DecSeg7(x: std_logic_vector(3 downto 0)) return std_logic_vector;
end package;
package body Seg7_pack is
function DecSeg7(x: std_logic_vector(3 downto 0)) return std_logic_vector is
variable y: std_logic_vector(6 downto 0);
begin
return y;
end function;
end package body;
Test the package function by simulation with the following testbench, which calls the function
after another with all combinations of the input vector and prints the results on the screen:
library ieee;
use ieee.std_logic_1164.all;
use work.Seg7_pack.DecSeg7;
library Tuc;
use Tuc.Ausgabe.all;
use Tuc.Numeric_sim.all;
entity TestDecSeg7 is end entity;
architecture a of TestDecSeg7 is
begin
process
variable x: std_logic_vector(3 downto 0):="0000";
variable y: std_logic_vector(6 downto 0);
begin
while not x="1111" loop
y := DecSeg7(x);
write("x=" & str(x) & " y=" & str(y));
x := x+1;
end loop;
wait;
2

end process;
end architecture;
Test the same function »DecSeg7« by embedding it in the circuit in figure 3, synthesize the circuit
and downloading it into the FPGA.
sw0
sw1
sw2
sw3
F12
G12
H14
H13
FPGA
DecSeg7
1
1
1
1
0
E14
G13
N15
P15
R16
F13
N16
P16
E13
F14
G14
D14
a
b
c
d
e
f
g
dp
AN3
AN2
AN1
AN0
Figure 3: Test circuit for the seven segment decoder
3 Multiplex display
At the same time only one digit can be displayed. Multiple digits must be displayed cyclic after
another. In the circuit in figure 4 the 50MHz input clock is scaled down by a 10 bit binary counter,
i.e. by 2 10 = 1024. A clock divider has already been used in the previous lectures. It is described
by a process with the 50MHz clock in the sensitivity list, in which with each rising edge of the
input clock a counter register is increased by one and on overflow the output clock is inverted. The
down scaled clock is the sample clock of the process, producing the 4-bit sliding zero vector for the
anode signals. The rest of the circuit should be described in a combinatorial process. If the two
left display elements are selected, the constants »1110« and »1010«, which are converted in the
characters »E« and »A«, respectively, should be displayed. The values for the right digits should
be selectable via the switches and transformed by the seven segment decoder into the anode signals
a to g. Combinatorial process means that all input signals, here the signals from the switches and
the anode signals, must be in the sensitivity list. Sampling of the asynchronous switching signals
is in this special case unnecessary for the bouncing does inf fact disturb the output signals, but
not in a perceptible way.
4 Via buttons selectable display values
In the next design, the four 4-bit hexadecimal values to be displayed should be provided by
counters. There should be one counter per digit controlled by own push button each as shown
in figure 5. The button signal is sampled as in the lecture before by a 2-bit shift register. If the
button is pressed and was released in the sample step before, the counter value will be increased
by one, circularly. Circular means that the next step after »1111« is »0000«. The debouncing
clock frequency should be about 50 Hz. The circuit in figure 5 should be described as a separate
design unit and simulated with the input waveform on the handout sheet. Complete the sketch
on the handout sheet withe the simulation results.
3

sw7
sw6
sw5
sw4
sw3
sw2
sw1
sw0
GCLK0
K13
K14
J13
J14
H13
H14
G12
F12
T9
bit 3
bit 2
bit 1
bit 0
bit 3
bit 2
bit 1
bit 0
”1110”
”1010”
4
4
4
4
FPGA
combinatorial process
0111
1011
1101
1110
DecSeg7
4
sampling process with the 50 kHz
clock
clock to produce the cicle
devider
1110 1101 1011 0111
1:2 10
4
1
E14
G13
N15
P15
R16
F13
N16
P16
E13
F14
G14
D14
a
b
c
d
e
f
g
dp
AN3
AN2
AN1
AN0
Figure 4: Circuit of the multiplex display
entity EingabeCt
+1
0
1
4
y
x
Clk
&
x button signal
y 4-bit counter value
Clk clock (ca. 50 Hz)
Figure 5: Counter units for setting a 4-bit value by a button
Next, four instances of the counter unit in figure 5 should be inserted in the previous description
in figure 4 to set the displayed values by the buttons. Figure 6 shows the complete circuit, that
should be designed, programmed, tested and presented to the supervisor 1
1 Keep also the programming files of the circuits in the figures 1, 3 and 4, to be also able to present it on request
to the supervisor.
4

BTN3
BTN2
BTN1
BTN0
GCLK0
(50 MHz)
L14
L13
M14
M13
T9
x EingabeCt
FPGA
Clk
y
combinatorial process
x EingabeCt
4
Clk
y
0111
4
1011 4
x
4
EingabeCt
1101
Clk
y 4
1110
DecSeg7
divider
1110 1101 1011
process 1:2 10 0111
x EingabeCt
Clk
y
4
sampling process with the 50 kHz
clock 1:2 20
clock to produce the cicle
1
E14
G13
N15
P15
R16
F13
N16
P16
E13
F14
G14
D14
a
b
c
d
e
f
g
dp
AN3
AN2
AN1
AN0
Figure 6: Multiplex display with counter units to set the display values
5 Check list for the compliance test
Exercise 1:
• presentation of the circuit description to figure 1
• filled in truth-table of the seven segment decoder on the hand-out sheet
Exercise 2:
• presentation of the simulation and the correct operation of the final downloaded circuit in
figure 3
Exercise 3:
• presentation of the operation of the final downloaded circuit to figure 4
Exercise 4:
• simulation results on the handout sheet to figure 5
• presentation of the final downloaded circuit in figure 6
5