LAB3 - Suraj @ LUMS

CS 523 Advanced Computer Architecture
LAB 3
(Due Date: April 21, 2006)
1. Introduction
The aim of this lab is to familiarize students with the SimpleScalar simulation tool set.
After a brief introduction of the tool set, an experiment will be performed to get a feel of
the working of simulator. The experiment will record miss rate of a single processor for
various cache configurations.
2. SimpleScalar Tool Set
The tool set contains several simulators, each of them oriented toward a specific type of
analysis:
• sim-safe: minimal SimpleScalar functional simulator
• sim-fast: fast (optimized sim-safe) SimpleScalar functional simulator
• sim-profile: program profiling simulator
• sim-cache: multi-level cache simulator
• sim-cheetah: multi-configuration cache simulator
• sim-outorder: the most complex and detailed SimpleScalar simulator in the tool
set
All these programs help you simulate the hardware, the SimpleScalar architecture. For
details about each individual simulator please refer to Todd Austin’s SimpleScalar
hacker’s guide (www.simplescalar.com/docs/hack_guide_v2.pdf ). All these programs can
be found under the directory /home/SimpleScalar03/simple-sim3.0/ at the EDA machine
server.

3. Pre-Lab
The EDA machine at RICE lab will act as a server for this lab. You will login to the
machine remotely using “PUTTY” telnet client. Course Web site has an internet link
from where you can download PUTTY. IP address of EDA machine is 172.28.6.88.
Every student will login with the login ID of the format “aastudentID”. For instance a
student with ID 2005-06-007 will login as aa05060007. Initially the password has been
set same as the student ID. But we strongly recommend you to change this first time you
log in using the command passwd. You have to set up the PATH variable to refer to
directories where SimpleScalar tools are located. To set the PATH give the following
command.
$export PATH=$PATH:/home/SimpleScalar03/simplesim-3.0/.
First ‘$’ represents your command prompt.
4. Cache Simulator
In this lab we will use the multilevel cache simulator sim-cache. The commands to simcache
are given through a configuration file. In order to learn about the cache simulator
itself type
$ sim-cache
Study the output of the above command very carefully, as it clearly explains options and
arguments used while writing a configuration file. Specifically note the format of
specifying a cache configuration. A five colon separated fields
name:sets:block_size:associativity:replacement_method. For instance a 32 kilobyte
level 1 data cache with 32 byte blocks, an associativity of 4 and least recently used
policy is specified as dl1:256:32:4:1, as 256 sets of four 32 byte blocks each have a total
capacity of 32 Kbytes.

You will be modifying the configuration file to get different parameters of a simulated
cache. In order to get a sample configuration file type
$ ./sim-cache –dumpconfig myconfig
There are two ways two evaluate performance of a functional cache simulator. One
way is to use some benchmark programs and obtain the statistics of a cache design
and the other way is develop own code to exploit properties of a design. In this lab we
will go with the first method. SPEC95 bench mark programs are located under the
directory /home/SimpleScalar03/Spec95/. We will use the ijpeg.ss binary to simulate
performance of cache. The command is:
$sim-cache –config myconfig /home/SimpleScalar03/spec95-little/ijpeg.ss
A whole bunch of information will be displayed. There are cache statistics with default
configuration. We will be focusing on the dl1.miss_rate parameter.
4.1 Assignment
In this experiment we will assume no L2 instruction or data caches. In the configuration
file use the following configuration for L1 instruction cache.
-cache:il1 il1:512:32 :1:1
Also to disable any TLB for either instruction or data do this
-cache: dl2
-cache:il2
-tlb:itlb
-tlb:dtlb
none
none
none
none

Use sim-cache to simulate the performance (miss rate) of the cache under the following
conditions:
a) Vary the number of sets in level 1 data cache from 1 to 1024 in powers of 4 while
keeping the block size at 32 bytes, the associativity at 4 and the algorithm as least
recently used. Comment on the effects of increasing the cache size on program
execution and recommend a size for this particular application. Plot Miss Rate
versus cache size.
b) Change the associativity of the level 1 data cache from 1 to 32 in powers of 2
while keeping the same block size and replacement policy as before. Keep the
total size of the data cache fixed at 8192 bytes. What can you say about the effects
of assosiativity on the effectiveness of the cache. Generate a plot to verify your
answer.
c) Adjust the block size of the level 1 data cache (8 bytes, 32 bytes, 128 bytes, 512
bytes, 2048 bytes) while preserving the same assosiativity, replacement policy and total
cache capacity. Why does performance degrade for small block sizes. Again generate an
appropriate plot.