Static Timing Analysis slides - UCSD VLSI CAD Laboratory
Static Timing Analysis slides - UCSD VLSI CAD Laboratory
Static Timing Analysis slides - UCSD VLSI CAD Laboratory
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Non-linear effects reflected in tables<br />
• D G = f (C L , S in ) and S out = f (C L , S in )<br />
• Non-linear<br />
• Interpolate between table entries<br />
• Interpolation error is usually below 10% of SPICE<br />
Output<br />
Capacitance<br />
Output<br />
Capacitance<br />
Input<br />
Slew<br />
Intrinsic<br />
Delay<br />
Input<br />
Slew<br />
Output<br />
Slew<br />
Delay at the gate<br />
Resulting waveform<br />
ECE 260B – CSE 241A <strong>Static</strong> <strong>Timing</strong> <strong>Analysis</strong> 40<br />
Andrew B. Kahng, <strong>UCSD</strong>
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