Tools or Users - UCSD VLSI CAD Laboratory - UC San Diego

Tools or Users:Which is the Bigger Bottleneck?John Szetela, AMDHilton Kirk, PhilipsPatrick Groeneveld, MagmaLavi Lev, CadencePaul Rodman, ReShapeRon Collett, NumetricsModerator: Andrew B. Kahng, UC San DiegoDAC02 Panel: Tools or Users1

The Productivity GapDAC02 Panel: Tools or Users2

Semiconductor Quality/Cost = Job #1• “Cost of design is the greatest threat tocontinuation of the semiconductor roadmap”– International Technology Roadmap for Semiconductors, December 2001• Semiconductor productivity fuels wealth creation• Productivity gap– “ASIC vs. custom” quality gap– Schedule risk, #respins, design TAT, design NRE à cost gap• Workarounds are not pretty– Programmable silicon implementation platforms?– Software?• We (tools/users/semi) are in this together !DAC02 Panel: Tools or Users3

ITRS 2001 Design Technology Crises• 2-3X more verification engineers than designers• Software = 80% of system development cost• Analog and mixed-signal design hasn’t scaled andisn’t reusable• Cost of Design > 10’s of $M• TAT of Design = years• Without DFT, test cost per transistor growsexponentially relative to mfg costDAC02 Panel: Tools or Users4

ITRS Design Needs (Back-End)• Analog layout synthesis and reuse• Layout-BIST synergies for UDSM fault models• New paradigms for global signaling, synchronizationand system-level interconnect• Modeling and simulation (interference, reliability, …)• Management of increased process variability and nonrecurringcosts in mask and foundry flows• Multi-(V dd , V t , t ox , biasing) performance optimization• = reliable front-end signoff + SOC productivity + mfg i/fDAC02 Panel: Tools or Users5

Four Questions• Tools or Users: Who’s to Blame?• What are specific problems and their costs?(Support with metrics, data.)• Why do design teams still succeed despitethese problems?• Shopping / wish list: What would solve theproblems you’ve cited?• Structure: Panelist presentations, moderatorquestions, audience questions• Goal: Illumination, and some progress !DAC02 Panel: Tools or Users6

Tools or Users:Which is the Bigger Bottleneck?John J. SzetelaManager, CAD Tools & SystemsAMDDAC02 Panel: Tools or Users7

Tools or Users: Who is to Blame?• Tools are the Bottleneck, of course !!!• The CAD Tool problem areas have shifted…….– “Minor” issues are MAJOR, in “new” denser fab process technologies– Simple fixes incur significant time for designs with large data sets– Infinite sized files are impractical as a “Standard” tool interface– Tools unable to shield users wrestling with design complexity• Cannot expect users to become vastly more proficient at tool usage !– Tools assume internal “design” experts on 3 rd party IP• The experts are elsewhere but the tools are “local”• “Brownie Points” for Tools:– New Point tools address some of the identified problem areas– Tools partially “manage” data size and design complexity problemsDAC02 Panel: Tools or Users8

Specific Tool Problem Areas• Design Closure is THE issue !!!– Complete design validation is an oxymoron !– Late changes in the design cycle are inevitable– The automated flow from “design” to “silicon” is too S-L-O-W• A TWO week repair cycle for a “final” timing fix is NOT effective• Timing Analysis ECO Placement Routing Analysis• Custom fixes with a half dozen metal layers are near ineffective• New technology, old “closure” problems….– The BIG FOUR problems:• IR Drop, Electromigration, Antenna, Signal Integrity• Previous rules of thumb do NOT play well in “deep” submicron• Much easier to design in reliability than to “repair” it at tape-out– Point Tools’ fixes for BIG FOUR, conflict with Timing ClosureDAC02 Panel: Tools or Users9

Why Design Teams Still Succeed ?• Because, we eat our very own dog food !!– Faster Compute Platforms• Processors are now 3 – 10x faster than before• 2- Way Multi-Processor are common• Even faster with distributed computing• “Server Farms have replaced Cherry orchards in Silicon Valley”– Network performance is 10X what it used to be– Disk Storage is “free” and “centralized”• The tools are getting much better– Handling “large” designs– “Fixing” most problem areas, BUT they create new problems• IP has been a saving grace, though it often seems like a curse !– Has anyone used this “IP stuff” without finding problems?DAC02 Panel: Tools or Users10

My Shopping / Wish List• Integrated tool set that understands all the design closure issues– “Fix” design convergence issues between point tools– “I do NOT really place much hope for this integration !”• Standard tool interfaces that use more than files– The two CAD database efforts here are worth watching– “Of course, we users usually write our own, don’t we?”• Verification tools that allow clean “final” netlists to the back end– “See, I can’t even avoid saying netlist, even if it is RTL” !• IF the above wish-list is “asking for the moon”, THEN….– AT LEAST an ECO system that works with good point tools !• Did some one say Wish List?– STOP saying “2½D Extraction”, means UNKNOWN accuracy– DO NOT say “hierarchical flow”, when you mean TWO levels– How about NOT saying “It’s fixed in our next release”, FIRST JDAC02 Panel: Tools or Users11

Tools or Users:Which is the Bigger Bottleneck?Hilton Kirk (for Lambert van den Hoven)Design Technology GroupPhilips SemiconductorsDAC02 Panel: Tools or Users12

Tools or Users: Who's to Blame?• Mainly the Tools (= Vendors)• Focus on point solutions not flows– performance of tool– testing of tool– quality of result of tool• Delivery of flows = additional revenue stream• Slow introduction of new methods (also slowtakeup by users)– eg. higher levels of abstractionDAC02 Panel: Tools or Users13

Specific Problems and Costs• Errors & time lost in tool interoperability– >30 beltstop faults in debugging new flow– multiple view formats• cost of update for libraries• data semantics lost/misinterpreted between tools• Verification (>50% errors in Spec)– Formal verification rarely used– Functional verification expensive (time & $)• Physical implementation– time to achieve area, power, timing closureDAC02 Panel: Tools or Users14

Why Design Teams Still Succeed• Emulation/Prototyping of the IC– FPGA’s & Rapid Silicon prototyping• (Over)Guardbanding, ‘don’t touch’ hard blocks• Re-Use– experts in the various domains• application system, synthesis, layout, test…– larger blocks of IP: platform derivatives• Cookbooks & workarounds– high cost to produce & maintain– users reluctant to read!DAC02 Panel: Tools or Users15

My Shopping / Wish List• Fast and efficient RTL to layout flow– tunable for power, area, performance– Value proven on specific design!• Stable flow– controlled introduction of proven improvements• Inituitive flows and UI’s• An easy to use formal design & verificationmethodology• Common database - open access to facilitateimproved flows & minimizing format changeDAC02 Panel: Tools or Users16

Tools or Users:Which is the Bigger Bottleneck?Patrick GroeneveldMagma Design AutomationDAC02 Panel: Tools or Users17

Tools or Users: Who's to Blame?• It’s the tool flow that is to blame• Ruthless automation is required to keepup with Moore’s law and• to keep ASIC’s financially andtechnically viable.DAC02 Panel: Tools or Users18

Specific Problems and CostsIt must deal with many Zero tolerance‘nitty gritty’ detailsfor sloppynessAlgorithms do only one thing well(and cannot handle multiple objectives)Algorithms use inaccurate models ofthe layout reality.Layout/logic Synthesis algorithms are unreliableDAC02 Panel: Tools or UsersThe IC layout RTL to GDSIIflow is a long chain ofdifferent algorithms.Algorithmic steps dothings that could causeproblems at later stepsWe often need tostart over iterate torecover such errors19

Why Design Teams Still Succeed• .. Because of sweat and tears:painstaking manual work andcorrection.• Succeed due to ‘super designers’ whoknow the ins and outs– they are rare.• Not all do succeed!DAC02 Panel: Tools or Users20

My Shopping / Wish List• A strong generic datamodel– (not to be confused with a database)• Common sense ABC approach thatattempts to avoid issues.DAC02 Panel: Tools or Users21

Let the tool flow around the data!RTLRoutingMask layoutPlacementCDFGDAC02 Panel: Tools or UsersNet list of Super Cells22

The ABC of an IC design flowA: AvoidDetect specific serious problem patterns early and fix them.- Fast- Many are not a problem, resource expensiveB: BuildSynthesize using a simple model and algorithm- Capture 1st order effect of problem as objectiveHope for the best- … Hope for the bestDAC02 Panel: Tools or UsersC: CorrectPerform accurate analysis, detect remaining problems andFix problems the hard way (ECO).- This is typically slow and it- might not work.- If its real bad, iterate back to step A or B23

Tools or Users:Which is the Bigger Bottleneck?Lavi LevExecutive Vice President &GMCadence Design Systems, Inc.DAC02 Panel: Tools or Users24

Tools or Users: Who's to Blame?• Nothing really failed, it just hurts a lot– EDA failed to understand, and users failed tocommunicate, all the headaches• Key ingredients to design team success– Tools’ performance (we got that)– Tools’ interoperability (didn’t get that)– Design team size and project complexity (didn’t getthat either)DAC02 Panel: Tools or Users25

Specific Problems and Costs• The specifics– EDA guys decide for Chip guys what their problems are– EDA guys considering victory when their competitionfails, not when their customer wins• The cost– Customers invests heavily in EDA infrastructure– EDA guys invest heavily on things that can be common– SOC creation market can’t growDAC02 Panel: Tools or Users26

Why Design Teams Still Succeed• Teams succeed, the market does not– There is a workaround to almost everythingCurrent state of affairs for most designers!Flow1XFlow2Tool‘n’db‘n’XXFlow ‘n’DAC02 Panel: Tools or Users27

My Shopping / Wish List• Mature EDA– Agree on standards first and then compete• OpenAccess is offered: We hope the industry adopts it– Standards around SOC creation are still missing• Knowledgeable EDA– Add chip designers to your management team• You might even solve real problem….OpenAccess DatabaseFlow1Tool‘n’DAC02 Panel: Tools or UsersCommonDatabaseFlow2Flow ‘n’28

Tools or Users:Which is the Bigger Bottleneck?Paul RodmanCTOReShape, Inc.DAC02 Panel: Tools or Users29

Tools or Users: Who's to Blame?• Users!– The Captain is Responsible for theShip• Tools Vendors Follow the Money– Stimulus-Response– If you don’t like it, don’t buy itDAC02 Panel: Tools or Users30

Specific Problems and Costs• Technical Issues Cause < 40% SlipsSubcontractor issues6%Unrealistic targets6%Poor management5%Late changes tothe product requirement13%Other15%Resource shortfall16%Unanticipatedtechnical difficulty39%Source: Pittiglio Rabin Todd & McGrathSemiconductor design benchmark study, 2002Complexity is Not Being Managed– The “second computer” problemDAC02 Panel: Tools or Users31

Why Design Teams Still Succeed• “Nothing is a substitute for intelligent, diligentengineers working well together.”-- Dan Smith, NVIDIA, EDP 2002• Concurrent Design– Discover RTL coding issues early• Good Project Management– A bad plan is better than no planDAC02 Panel: Tools or Users32

My Shopping / Wish List• Interoperability solved– Each Vendor provide open sourceparser used for each format• Make tools easier to automate flows– Error/Warning/Exit status– License handling– Batch mode trap doors• Hire people with track records ofcompleting complex ICsDAC02 Panel: Tools or Users33

Tools or Users:Which is the Bigger Bottleneck?Ronald CollettPresident & CEONumetrics Management Systems, Inc.DAC02 Panel: Tools or Users34

Tools or Users: Who's to Blame?• Events invariably occur that cause “bottlenecks”• Sometimes it’s users, sometimes it’s tools,sometimes it’s both, sometimes it’s neither,but…DAC02 Panel: Tools or Users35

It’s the Usual Suspects that CauseBottlenecks!• Changing specification• Inadequate engineering resources• EDA tool/flow problems• Mfg. process/library instability• Lack of management commitment• “Unexpected” design bugs• Etc.DAC02 Panel: Tools or Users36

Why Teams Succeed: Better Planning• Chip Complexity = ƒ(ckt. types, timing, reuse, power . . .)• Design Productivity =ComplexityEffort– Effort = ƒ(Eng. & mgmt. skills, EDA tools, specstability, mfg. process stability, etc.)• Rate of Effort Consumption = ƒ(best practices)• Quality of Design Process – e.g. spin count probabilitydensity function• Key Milestones -- e.g. ƒ(effort consumed, bug rate)DAC02 Panel: Tools or Users37

Silicon Spin Count can be ModeledSilicon Spins, High Complexity Communications ICs*Probability30%20%31.03% 31.03 %17.24 %High AnalogContent10%10.34%10.34 %First-timeSilicon Success1 2 3 4 5 Or MoreDAC02 Panel: Tools or UsersSpin Count*High Complexity = >1 Million Complexity Units38

Shopping List: Project Plan SynthesisIndividualProductivityEDA Tools& FlowsManagementInfluenceCustomerInfluenceTeam ProductivitySynthesis InputsProjectConstraintsSynthesis OutputPeakRampStaffing LimitsKey PeopleAvailabilityCriticalMilestonesTapeoutsPhysical DesignFunctionalityReuse LevelsModel CalibrationUses EmpiricalProject DataTeam SizeA/MSLogic DesignVerification/Validation.PeakStaffTargetTechnologyProject Duration(Time -to-Market)Chip ComplexityDAC02 Panel: Tools or Users39

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The Value of Interoperability• All:– Define what it means for a tool X to be“interoperable”.• Users:– How many more licenses, at how much higher aprice per license, would you buy of a new“interoperable” version of tool X, if it wereavailable?• Tools:– Estimate the costs of providing “interoperability”according to the definitions given.• All:– So, what form of “interoperable” is even possible?DAC02 Panel: Tools or Users41

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On Openness• Tools– In the spirit of openness, will you allow your toolsto be benchmarked, and the results freelyreported? (If not, why not?)• Users– If open benchmarking is permitted, what resourcesand design IP would your organization/companycommit to whatever entity fulfills such a need?• All– (Or, is there any need to benchmark EDA …?)DAC02 Panel: Tools or Users43

Who Should Define the Methodology?• All– Should tools define the methodology?– Who should (or, can) define new and improvedmethodologies: tool vendors or design teams?DAC02 Panel: Tools or Users44

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So What’s Really Different Today?• All– [Who remembers SPINE99 J ? (Do tools and/orusers simply “get religion” every few years?)]– Is this a panel that we’ll have every 5 DAC’s for thenext 20 years, or is something fundamentallydifferent and more urgent today?DAC02 Panel: Tools or Users46

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Technology Lag• All– Do tools have an inherent “technology lag” ?– What do you see as lower / upper bounds on thislag ?• Users– Given that one technology node now arrives everytwo years, is this lag bearable?• Tools– Is the lag in any way attributable to how users workwith available tools?– What measures (internal to EDA, or joint betweensemi+EDA companies) would enable systematicreduction of the “technology lag”?DAC02 Panel: Tools or Users48

“Mother Nature” vs. “Integration/Flow”• All: Why haven’t we be talking about these specificissues?– Easy?– Less important?• Analog layout synthesis and reuse• Layout-BIST synergies for UDSM fault models• New paradigms for global signaling, synchronization and system-levelinterconnect• Modeling and simulation (interference, reliability, …)• Management of increased process variability and non-recurring costs inmask and foundry flows• Multi-(V dd, V t, t ox, biasing) performance optimization• = reliable front-end signoff + SOC productivity + mfg i/fDAC02 Panel: Tools or Users49

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So…• All– Who is to blame for the productivity (value / cost)gap – tools or users?– What’s the solution?DAC02 Panel: Tools or Users51

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Other Questions• Do vendors understand the design problem?• Is it impossible for tools to be both easy to use andhave reliably high quality of result?DAC02 Panel: Tools or Users53