Tools or Users - UCSD VLSI CAD Laboratory - UC San Diego
Tools or Users - UCSD VLSI CAD Laboratory - UC San Diego
Tools or Users - UCSD VLSI CAD Laboratory - UC San Diego
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Specific Problems and Costs• Err<strong>or</strong>s & time lost in tool interoperability– >30 beltstop faults in debugging new flow– multiple view f<strong>or</strong>mats• cost of update f<strong>or</strong> libraries• data semantics lost/misinterpreted between tools• Verification (>50% err<strong>or</strong>s in Spec)– F<strong>or</strong>mal verification rarely used– Functional verification expensive (time & $)• Physical implementation– time to achieve area, power, timing closureDAC02 Panel: <strong>Tools</strong> <strong>or</strong> <strong>Users</strong>14
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