The Haystack 2nd generation digital‐backend system - CIRA

RDBE: 2 nd Generation VLBI
Digital Backend System
Alan Whitney
MIT Haystack Observatory

DBE development at Haystack
• DBE1 (developed 2004-2006)
• Hardware is based on a flexible FPGA-based signal-processing
board from UC Berkeley (“iBOB”)
• Developed collaboratively between Haystack and UC Berkeley
Space Sciences Laboratory
• DBE design based on Polyphase Filter Bank (PFB) concept
• Processes each of two 500MHz IFs to 16 32MHz channels on
VSI-H output connector; total 4096Mbps on two VSI-H outputs
• Includes sample-clock synthesizer with temp coef

DBE System
DBE: 2x (iADC + iBOB);
8Gbps output (4xVSI-H)
• DBE Total system cost ~$65K
Mark5B+: 2Gb/s VSI-H each
(DBE supports 4 Mk5B+s)
Current modes: 15 channels, each 32MHz, 2-bit = 1920Mb/s
15 channels, each 16MHz, 2-bit = 960Mb/s

DBE1 vs DBE1 with
no phase adjustments
whatever
RMS phase across
frequency channels:
RMS: 2.5 deg
Theor: 1.0 deg
Comparable to best
we’ve seen even
with ‘manual’
adjustments to
embedded phase-cal

2 nd generation: RDBE
• RDBE
• 2 nd -generation DBE, based on ROACH board developed by
Berkeley, NRAO and South Africa; 10 GigE data output(s) to
Mark 5C
• Colloborative firmware/software development by Haystack,
NRAO, Berkeley and South Africa
• Haystack developing system-level FPGA framework, PFB
signal-processing module, and software framework
• Goal is to support up to 2x1000MHz IF inputs, total max output
data rate 8Gbps
• NRAO creating tunable DDC version to replace (dubbed
‘VCBE’) to replace analog BBCs; part of VLBA upgrade to
4Gbps
• South Africa developed PowerPC OS

RDBE block diagram

RDBE housed in ‘ROACH Hotel’
(2x ROACH boards)

Three Initial Designs using a Common
Firmware & Software Architecture
• NASA VLBI2010 Geodetic Mode
– Two 16 channel PFB’s
– Output is any 16 of the 32 channels for 2Gbps output in Mark5B legacy format
• Astronomy Mode 1
– Two 16 channel PFB’s
– 4Gbps output in Mark5B legacy format
• NRAO
– Flexible DDC to replace PFB

Common RDBE/VDBE features
• Common hardware
• Common FPGA, OS and software framework
– VSI-S compatible control/monitor
– IF AGC using external digitally controlled attenuator
– Continuous state-count monitoring
– Tsys measurements using synchronously-controlled noise diode
– Multiple-channel real-time phase-calibration extraction
– RDBE/VDBE personality is software changeable (few minutes)

RDBE diagram (PFB mode)
1024MHz
V5SX95T FPGA
Julian
Clk
512MHz
IF0
IF1
ADC
8-bit
2 chan
256MHz
Clk
FIR
FIR
BiPlex
FFT
Interp
Filter
32 Ch
2-bit
Quantization
Mk5B
Format
Header
Gen
GPS 1 PPS
To ALC
Input
Power
Level
Phase
Cal
Switched
Tsys
Digital
Gains
---------
State
Counts
10Gb
Ethernet
4Gb/s
Each 512 MHz IF split into 16 channels, each 32 MHz.
Mk5C

RDBE diagram (DDC mode)
1024MHz
V5SX95T FPGA
Julian
Clk
512MHz
IF0
IF1
ADC
8-bit
2 chan
256MHz
Clk
NRAO
DDC
32 Ch
n-bit
Quantization
Mk5B
Format
Header
Gen
GPS 1 PPS
To AGC
Input
Power
Level
Phase
Cal
Switched
Tsys
Digital
Gains
---------
State
Counts
10Gb
Ethernet
4Gb/s
DDC’s: 62.5kHz - 128 MHz, tunable over full IF range.
Goal to replicate current VLBA BBC capability.
Mk5C

RDBE Software Architecture
Commands in
VSI-S format.

Sweep Through PFB Channels
10GbE data output processed in MATLAB

Noise and Tone Testing
10GbE data output processed in MATLAB. Testing by Spencer Cappallo

RDBE VLBI Demonstration
• Stations
– Westford 18m
– MV3 5m at GGAO
• Source 4C39.25
– 10 minute scan
• Cooled broadband dual linear polarization feed
and LNAs covering 2-12 GHz
– 512 MHz band selected around 8.5 GHz
• RDBE at both sites
– Eight 32-MHz channels from each of two polarizations merged onto single
10GigE line at 2 Gbps
– Data recorded on Mark5C in Mark5B data format
• Processed on Haystack Mark4 correlator

VLBI Results from RDBE test
Autocorrelation Spectrum
Amp & Phase vs time on Westford-to-MV3 baseline (SNR~20)

Work in progress
• Select channels to be recorded in geodetic mode
• Noise-diode synchronous switching and detection for Tsys
measurement
• Digital down conversion (DDC) FPGA code
[being done by NRAO]
• Astronomy ‘Burst Mode’ – 4x500MHz IFs, 4 channels,
single 10GigE output, 8 Gbps
• Phase-cal extraction
• VDIF output format
• Work to be completed by ~Q2 2011

Summary
– PFB versions completed for 2 different personalities.
• Mixed IFs for dual polarization at 2 Gbps on one 10GigE line.
• Two IFs at 2 Gbps each on two separate 10GigE lines.
– Data recorded on Mark5C in Mark5B format.
– Successful VLBI test of PFB version
– DDC personality to be ready within few months (NRAO)
– Remaining modules to be implemented: Tsys, phase-cal.
– Hardware can be purchased from Digi-Com Electronics,
Richmond, CA

Questions?