The Haystack 2nd generation digitalâbackend system - CIRA
The Haystack 2nd generation digitalâbackend system - CIRA
The Haystack 2nd generation digitalâbackend system - CIRA
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DBE development at <strong>Haystack</strong><br />
• DBE1 (developed 2004-2006)<br />
• Hardware is based on a flexible FPGA-based signal-processing<br />
board from UC Berkeley (“iBOB”)<br />
• Developed collaboratively between <strong>Haystack</strong> and UC Berkeley<br />
Space Sciences Laboratory<br />
• DBE design based on Polyphase Filter Bank (PFB) concept<br />
• Processes each of two 500MHz IFs to 16 32MHz channels on<br />
VSI-H output connector; total 4096Mbps on two VSI-H outputs<br />
• Includes sample-clock synthesizer with temp coef
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