Microcontroller: 1-wire Interface, SPI Interface - IIIT

Microcontroller: 1-wire Interface,
SPI Interface
Amarjeet Singh
February 5, 2012

Logistics
Website updated with lecture slides from last 2 lectures
Assignment-3
Any problem
Assignment-4
Final assignment – and probably requires maximum effort
Make sure to build upon your previous assignments
Link for Hex file for boot loader given on the course website
2

Students Presentations – After Mid
Sem
Student presentations on specialization topics in Cyber Physical
Systems
Will share the list of topics with spreadsheet with everyone
Mandatory for CSE-537 students
Select one of the topics that you want to present by this weekend
and assign it to yourself in the spreadsheet
If CSE-337 students also present, their summary evaluation will
also carry 5 marks only
Presentations will start after mid semester
I will post the schedule after you all have selected the papers
All need to submit 1 page summary on the same paper before the
class (through email)
Each group need to submit one summary only
3

Revision from last two classes
For the 16-bit RTC in xMega:
What is the highest resolution obtained with 32.768 KHz clock
With a resolution of 1 second, what is the maximum timeout
period
How can you use the two Analog Comparator modules in xMega to
check if a signal is within a range
What is the maximum ADC resolution in xMega
How many maximum single ended signals can be supported using
ADC block in xMega
What is the reference voltage given to the negative channel for:
Single ended signal unsigned mode
Single ended signal signed mode
Differential signal (signed)
4

Revision from last two classes
What limits the sampling rate of ADC
How is propagation delay given for ADC block in xMega
What are things to consider when selecting a sensor to interface
with your microcontroller
What is the function of voltage regulators
What are some common types of voltage regulators
Where and why are decoupling capacitors used
Where and why are pull up/down resistors used
5

Revision from last two classes
Why is it important to take a look at DC characteristics while
interconnecting two ICs
I2C protocol
How many lines
What is the packet format
Why is it not suitable for peer to peer communication
6

1-Wire Interface
Online tutorial by Maxim
http://www.maximintegrated.com/products/1-wire/flash/overview/index.cfm
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DS18S20: 1-Wire Interface
Temperature Sensor from Maxim
9-bit temperature value
0.5 degree celsius accuracy from -10 to +85
Can derive power directly from the data line
Unique 64-bit code that allows multiple temperature sensors to
be connected on the same line – e.g. temperature monitoring in
HVAC
8

DS18S20: Function Commands
DS18S20 Transaction:
Initialization
ROM Command (followed by any required data exchange)
DS18S20 Function Command (followed by any required data
exchange)
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DS18S20: Operation Example 1
Multiple DS18S20 on the same line (in parasitic mode)
Master initiates a temperature conversion in a specific sensor
Master reads the scratchpad to recalculate the CRC and verify the
data
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DS18S20: Operation Example 2
Single DS18S20 on the bus (in parasitic mode)
Master writes to T H and T L registers in scratchpad and then reads
the scratchpad to verify the values
Master then copies scratchpad into EEPROM
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DS2482: I2C to 1-wire
DS2482-100: I2C to 1-wire bridge device
Interfaces with standard or fast I2C masters to perform bidirectional
conversion between I2C master and downstream 1-Wire
slave devices
Relative to 1-Wire slave devices, it acts as 1-Wire master
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SPI Signals
Four main signals:
Master Out Slave In (MOSI)
Master In Slave Out (MISO)
Serial Clock (SCK)
Chip Select (CS)
Since there is a separate CS
for each device on board,
SPI does not scale up well in
comparison with I2C
MOSI: Generated by master, received by slave
Also labeled as Serial Input (SI) or Serial Data In (SDI)
MISO: Generated by slave, under control by the master
Also labeled as Serial Output (SO) or Serial Data Out (SDO)
Chip Select (Slave Select) generated using spare I/O of master
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SPI Communication
Master configures SCK with frequency less than or equal to
maximum frequency supported by slave device (1-70 MHz)
Master pulls the CS low
Full duplex data transfer:
Both master and slave contain shift registers: Master starts the
transfer by writing to its SPI shift register
As master transfers the byte to the slave on MOSI, slave transfers the
contents of its shift register back to the master on MISO
After 5 bits are
transferred what
is the state of TX
Buffer
Both the write and the read performed simultaneously
For write only operation, read byte is ignored
For read only operation, a dummy byte is written to initiate slave
transmission
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SPI: Modes of Operation
Four modes of operation depending on clock polarity and clock phase
Low clock polarity (CPOL = 0): SCK is low when idle and toggles high
during transfer
High clock polarity (CPOL = 1): Reverse of low clock polarity
Clock phase zero (CPHA = 0): MOSI and MISO are valid on
rising/falling edge of SCK for low/high clock polarity respectively
Clock phase zero and low clock polarity
How does the timing diagram
change for CPOL = 1
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SPI: Modes of Operation
Clock phase one (CPHA = 1): MOSI and MISO are valid on
falling/rising edge of SCK for low/high clock polarity respectively
Clock phase one and low clock polarity
SPI Mode 0: CPOL = 0, CPHA = 0; SPI Mode 1: CPOL = 0, CPHA = 1;
SPI Mode 2: CPOL = 1, CPHA = 0; SPI Mode 3: CPOL = 1, CPHA = 1
Most common modes: SPI Mode 0 and 3 (data sampled on positive
clock edge)
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SPI: Modes of Operation
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SPI: Interfacing External Flash
Atmel AT25DF641: 64 Mbit Serial Flash Memory
Supports SPI mode 0 and 3
Works at 75 MHz
Low power dissipation: 5 mA (typical) active read current
100,000 Program/Erase cycles
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SPI: Interfacing External Flash
Atmel AT25DF641: 64 Mbit Serial Flash Memory
Supports SPI mode 0 and 3
Works at 75 MHz
Low power dissipation: 5 mA (typical) active read current
100,000 Program/Erase cycles
Which SPI mode does this waveform represent
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SPI: Key Observations
4 lines required: MOSI, MISO, SCK, CS
Allows simultaneous read and write making it more efficient
Higher data rate: Up to 4 Mbps or more
Multiple devices can be connected simultaneously but with only a
single master
Device selection based on Chip Select: Implies an extra pin for
each device on the master chip
More efficient in point to point connection: Why
No acknowledgement mechanism to confirm data receipt
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SPI vs I2C
SPI more suited for applications that are thought as data streams (as
opposed to reading/writing address locations in slave devices)
Gains efficiency in applications that take advantage of its duplex
capability e.g. codec (that requires sending samples in and out)
Due to lack of built-in device addressing, SPI requires more hardware
resources when more than one slave device is attached
But SPI more efficient and simpler in point-to-point links
Cost and complexity of I2C does not scale with number of devices
With its collision detection and acknowledgement scheme, I2C is a
true multi-master bus
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