PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ...
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ...
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ...
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Philips Semiconductors<br />
<strong>PAL</strong>/<strong>NTSC</strong>/<strong>SECAM</strong> <strong>video</strong> <strong>decoder</strong> <strong>with</strong> <strong>adaptive</strong> <strong>PAL</strong>/<strong>NTSC</strong><br />
<strong>comb</strong> filter, VBI-data slicer and high performance scaler<br />
Preliminary specification<br />
SAA7114H<br />
Raw VBI-data will be handled as specific input format and<br />
need an own programming page (= own task).<br />
In VBI pass through operation the processing of prescaler<br />
and vertical scaling has to be set to no-processing, but the<br />
horizontal fine scaling VPD can be activated. Upscaling<br />
(oversampling, zooming), free of frequency folding, up to<br />
factor 3.5 can be achieved, as required by some software<br />
data slicing algorithms.<br />
These raw samples are transported through the image<br />
port as valid data and can be output as Y only format.<br />
The lines are framed by SAV and EAV codes.<br />
8.3.1 ACQUISITION CONTROL AND TASK HANDLING<br />
(SUBADDRESSES 80H, 90H, 94H TO 9FH AND<br />
C4H TO CFH)<br />
The acquisition control receives horizontal and vertical<br />
synchronization signals from the <strong>decoder</strong> section or from<br />
the X-port. The acquisition window is generated via pixel<br />
and line counters at the appropriate places in the data<br />
path. From X-port only qualified pixels and lines<br />
(= lines <strong>with</strong> qualified pixel) are counted.<br />
The acquisition window parameters are:<br />
• Signal source selection regarding input <strong>video</strong> stream<br />
and formats from the <strong>decoder</strong>, or from X-port<br />
(programming bits SCSRC[1:0]91H[5:4] and<br />
FSC[2:0]91H[2:0])<br />
Remark: The input of raw VBI-data from internal<br />
<strong>decoder</strong> should be controlled via the <strong>decoder</strong> output<br />
formatter and the LCR registers (see Section 8.2<br />
“Decoder output formatter”)<br />
• Vertical offset defined in lines of the <strong>video</strong> source,<br />
parameter YO[11:0]99H[3:0]98H[7:0]<br />
• Vertical length defined in lines of the <strong>video</strong> source,<br />
parameter YS[11:0]9BH[11:8]9AH[7:0]<br />
• Vertical length defined in number of target lines, as<br />
result of vertical scaling, parameter<br />
YD[11:0]9FH[11:8]9EH[7:0]<br />
• Horizontal offset defined in number of pixels of the <strong>video</strong><br />
source, parameter XO[11:0]95H[3:0]94H[7:0]<br />
• Horizontal length defined in number of pixels of the<br />
<strong>video</strong> source, parameter XS[11:0]97H[3:0]96H[7:0]<br />
• Horizontal destination size, defined in target pixels after<br />
fine scaling, parameter XD[11:0]9DH[3:0]9CH[7:0].<br />
The source start offset (XO11 to XO0, YO11 to YO0)<br />
opens the acquisition window, and the target size<br />
(XD11 to XD0, YD11 to YD0) closes the window, but the<br />
window is cut vertically, if there are less output lines than<br />
expected. The trigger events for the pixel and line counts<br />
are the horizontal and vertical reference edges as defined<br />
in subaddress 92H.<br />
The task handling is controlled by subaddress 90H (see<br />
Section 8.3.1.2).<br />
8.3.1.1 Input field processing<br />
The trigger event for the field sequence detection from<br />
external signals (X-port) are defined in subaddress 92H.<br />
From the X-port the state of the scalers H-reference signal<br />
at the time of the V-reference edge is taken as field<br />
sequence identifier FID. For example, if the falling edge of<br />
the XRV input signal is the reference and the state of XRH<br />
input is logic 0 at that time, the detected field ID is logic 0.<br />
The bits XFDV[92H[7]] and XFDH[92H[6]] are defining the<br />
detection event and state of the flag from the X-port.<br />
For the default setting of XFDV and XFDH at ‘00’ the state<br />
of the H-input at the falling edge of the V-input is taken.<br />
The scaler directly gets a corresponding field ID<br />
information from the SAA7114H <strong>decoder</strong> path.<br />
The FID flag is used to determine, whether the first or<br />
second field of a frame is going to be processed <strong>with</strong>in the<br />
scaler and it is used as trigger condition for the task<br />
handling (see bits STRC[1:0]90H[1:0]).<br />
According to ITU 656, FID at logic 0 means first field of a<br />
frame. To ease the application, the polarities of the<br />
detection results on the X-port signals and the internal<br />
<strong>decoder</strong> ID can be changed via XFDH.<br />
As the V-sync from the <strong>decoder</strong> path has a half line timing<br />
(due to the interlaced <strong>video</strong> signal), but the scaler<br />
processing only knows about full lines, during 1st fields<br />
from the <strong>decoder</strong> the line count of the scaler possibly shifts<br />
by one line, compared to the 2nd field. This can be<br />
compensated by switching the V-trigger event, as defined<br />
by XDV0, to the opposite V-sync edge or by using the<br />
vertical scalers phase offsets. The vertical timing of the<br />
<strong>decoder</strong> can be seen in Figs 21 and 22.<br />
As the H and V reference events inside the ITU 656 data<br />
stream (from X-port) and the real-time reference signals<br />
from the <strong>decoder</strong> path are processed differently, the<br />
trigger events for the input acquisition also have to be<br />
programmed differently.<br />
2000 Mar 15 38