PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ...
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ...
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ...
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2000 Mar 15 6<br />
RES<br />
CE<br />
XTOUT<br />
XTALI<br />
XTALO<br />
AI11<br />
AI12<br />
AI21<br />
AI22<br />
AI23<br />
AI24<br />
AOUT<br />
AI1D<br />
AI2D<br />
AGND<br />
30<br />
27<br />
4<br />
7<br />
6<br />
20<br />
18<br />
16<br />
14<br />
12<br />
10<br />
22<br />
19<br />
13<br />
21<br />
LLC<br />
28<br />
LLC2<br />
RTCO<br />
(1)<br />
29<br />
REAL-TIME OUTPUT<br />
97 98 99 3<br />
TCK<br />
36<br />
TMS<br />
RTS0<br />
34<br />
TDI<br />
RTS1<br />
2<br />
TDO<br />
35<br />
XCLK<br />
CLOCK GENERATION<br />
AND<br />
POWER-ON CONTROL<br />
ANALOG<br />
DUAL<br />
ADC<br />
TRST<br />
BOUNDARY<br />
SCAN<br />
TEST<br />
94<br />
DIGITAL<br />
DECODER<br />
WITH<br />
ADAPTIVE<br />
COMB<br />
FILTER<br />
EXPANSION PORT PIN MAPPING I/O CONTROL I 2 C-BUS<br />
X PORT I/O FORMATTING<br />
ull pagewidth<br />
PROGRAMMING<br />
REGISTER<br />
ARRAY<br />
FIR-PREFILTER<br />
PRESCALER<br />
AND<br />
SCALER BCS<br />
A/B<br />
REGISTER<br />
MUX<br />
EVENT CONTROLLER<br />
LINE<br />
FIFO<br />
BUFFER<br />
VERTICAL<br />
SCALING<br />
HORIZONTAL<br />
FINE<br />
(PHASE)<br />
VIDEO<br />
SCALING FIFO 32<br />
to<br />
8(16)<br />
45<br />
AUDIO<br />
MUX<br />
GENERAL PURPOSE<br />
TEXT<br />
CLOCK<br />
VBI-DATA SLICER<br />
FIFO<br />
GENERATION 42<br />
37<br />
AMCLK<br />
XDQ<br />
40<br />
XPD[7:0]<br />
95 81, 82,<br />
84 to 87<br />
89, 90<br />
39<br />
ASCLK<br />
41<br />
ALRCLK AMXCLK<br />
(1)<br />
XRH<br />
92<br />
8<br />
V DD(XTAL)<br />
XRV<br />
91<br />
5<br />
XRDY<br />
V SS(XTAL)<br />
96<br />
XTRI<br />
33, 43,<br />
58, 68,<br />
83, 93<br />
V DDD(ICO1)<br />
to<br />
V DDD(ICO6)<br />
(1) The pins RTCO and ALRCLK are used for configuration of the I 2 C-bus interface<br />
and the definition of the crystal oscillator frequency at RESET (pin strapping).<br />
80<br />
HPD[7:0]<br />
1, 25,<br />
51, 75<br />
V DDD(EP1)<br />
to<br />
V DDD(EP4)<br />
64 to 67,<br />
69 to 72<br />
23, 17,<br />
11<br />
V DDA0<br />
to<br />
V DDA2<br />
SDA<br />
32<br />
chrominance of 16-bit input<br />
Fig.1 Block diagram.<br />
38, 63,<br />
88<br />
V SSD(ICO1)<br />
to<br />
V SSD(ICO3)<br />
SCL<br />
31<br />
26, 50,<br />
76, 100<br />
V SSD(EP1)<br />
to<br />
V SSD(EP4)<br />
24,<br />
15, 9<br />
V SSA0<br />
to<br />
V SSA2<br />
TEST5<br />
79<br />
TEST4<br />
78<br />
SAA7114H<br />
TEST3<br />
77<br />
TEST2<br />
VIDEO/TEXT<br />
ARBITER<br />
74<br />
TEST1<br />
73<br />
TEST0<br />
IMAGE PORT PIN MAPPING<br />
44<br />
54 to 57,<br />
59 to 62<br />
46<br />
53<br />
52<br />
48<br />
49<br />
47<br />
MHB528<br />
IPD[7:0]<br />
IDQ<br />
IGPH<br />
IGPV<br />
IGP0<br />
IGP1<br />
ICLK<br />
ITRDY<br />
ITRI<br />
6 BLOCK DIAGRAM<br />
<strong>PAL</strong>/<strong>NTSC</strong>/<strong>SECAM</strong> <strong>video</strong> <strong>decoder</strong> <strong>with</strong> <strong>adaptive</strong> <strong>PAL</strong>/<strong>NTSC</strong><br />
<strong>comb</strong> filter, VBI-data slicer and high performance scaler<br />
SAA7114H<br />
Philips Semiconductors Preliminary specification
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