J-Link / J-Trace User Guide (UM08001) - SEGGER Microcontroller

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28 CHAPTER 1 Introduction Reset low level output voltage (V OL ) V OL
• Serial Wire Viewer supported • Download speed up to 720 KBytes/second ** (higher download speeds will be available in the near future) • DCC speed up to 800 Kbytes/second ** • Comes with licenses for: J-Link ARM RDI, J-Link ARM FlashBP, J-Link ARM FlashDL, J-Link ARM GDB Server and J-Flash ARM. • Embedded Trace Buffer (ETB) support • Galvanic isolation from host via Ethernet • RDI interface available, which allows using J-Link with RDI compliant software ** = Measured with J-Link Pro Rev. 1.1, ARM7 @ 50 MHz, 12MHz JTAG speed. 1.3.4.2 Download speed The following table lists performance values (Kbytes/s) for writing to memory (RAM): Hardware Rev. 1 via USB Rev. 1 via TCP/IP All tests have been performed in the testing environment which is described on Measuring download speed on page 274. The actual speed depends on various factors, such as JTAG/SWD, clock speed, host CPU core etc. 1.3.4.3 Hardware versions Version 1.1 Compatible to J-Link ARM. • Provides an additional Ethernet interface which allows to communicate with J- Link via TCP/IP. 1.3.5 J-Link ARM Lite J-Link ARM Lite is a fully functional OEM-version of J-Link ARM. If you are selling evaluation-boards, J-Link ARM Lite is an inexpensive emulator solution for you. Your customer receives a widely acknowledged JTAG-emulator which allows him to start right away with his development. 1.3.5.1 Additional features ARM7 via JTAG 720 Kbytes/s (12 MHz JTAG) 720 Kbytes/s (12 MHz JTAG) ARM9 via JTAG 550 Kbytes/s (12 MHz JTAG) 550 Kbytes/s (12 MHz JTAG) Table 1.4: Download speed differences between hardware revisions Cortex-M3 via SWD 190 Kbytes/s (12 MHz SWD) 190 Kbytes (12 MHz SWD) • Very small form factor • Fully software compatible to J-Link ARM • Any ARM7/9/11, Cortex-A5/A8, Cortex-M0/M1/M3/M4, Cortex-R4 core supported • JTAG clock up to 4 MHz • SWD, SWO supported for Cortex-M devices • Flash download into supported MCUs • Standard 20-pin 0.1 inch JTAG connector (compatible to J-Link ARM) J-Link / J-Trace (UM08001) © 2004-2012 SEGGER Microcontroller GmbH & Co. KG 29
Page 1 and 2: J-Link / J-Trace User Guide Softwar
Page 3 and 4: Revision Date By Explanation V4.51e
Page 5 and 6: Revision Date By Explanation 74 090
Page 11 and 12: About this document This document d
Page 13 and 14: 13 Table of Contents 1 Introduction
Page 15 and 16: 5.3.4 JTAG Speed ..................
Page 17 and 18: 9.15.6 OMAP3530....................
Page 19 and 20: Chapter 1 Introduction This chapter
Page 21 and 22: 1.2 Supported OS J-Link/J-Trace can
Page 23 and 24: 1.3.1 Model comparison The followin
Page 25 and 26: LOW level input voltage (V IL ) V I
Page 27: 1.3.3 J-Link Ultra J-Link Ultra is
Page 31 and 32: 1.3.6.1 Specifications The followin
Page 33 and 34: 1.3.7.3 Download speed The followin
Page 35 and 36: Clock fall time (T fc ) Max. 10ns 1
Page 37 and 38: Target supply current Max. 300mA LO
Page 39 and 40: 1.5 Supported CPU cores J-Link / J-
Page 41 and 42: 1.6.2.1 Limitations of PC-side impl
Page 43 and 44: 1.6.3.2 Older models The table belo
Page 45 and 46: Chapter 2 Licensing This chapter de
Page 47 and 48: 2.2 Software components requiring a
Page 49 and 50: 2.3.2.1 Entering a key-based licens
Page 51 and 52: Manufacturer Name Licenses NXP LPC1
Page 57 and 58: 2.4 Legal use of SEGGER J-Link soft
Page 59 and 60: 2.5.3 J-Link Pro J-Link Pro is a JT
Page 61 and 62: 2.6 J-Link OEM versions There are s
Page 63 and 64: 2.6.6 IAR: J-Trace IAR J-Trace is a
Page 65 and 66: 2.8 Illegal Clones Clones are copie
Page 67 and 68: Chapter 3 J-Link and J-Trace relate
Page 69 and 70: J-Link GDB Server J-Link GDB Server
Page 71 and 72: -If Selects the target interface J-
Page 73 and 74: When passing all necessary informat
Page 75 and 76: eturn; } // // Check if ITM_TRC is
Page 77 and 78: 3.2.5 J-Link STM32 Commander (Comma
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3.2.7 J-Mem Memory Viewer J-Mem dis
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3.2.9 J-Link RDI (Remote Debug Inte
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3.3 Dedicated flash programming uti
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3.3.5.2 Purchasing the source code
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3.5 Using the J-LinkARM.dll 3.5.1 W
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Chapter 4 Setup This chapter descri
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2. The Welcome dialog box is opened
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4.2 Setting up the USB interface Af
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(jlink) USB and click the Change/Re
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The Network configuration page allo
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4.5 J-Link Configurator Normally, n
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4.6 J-Link USB identification In ge
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Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
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5.6 Connecting multiple J-Links / J
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5.7 J-Link control panel Since soft
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Flash download and flash breakpoint
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Available function calls to log: Re
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5.8 Reset strategies J-Link / J-Tra
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5.8.2 Strategies for Cortex-M devic
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performs a reset of the CPU and per
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5.10 J-Link script files In some si
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5.10.2.7 JTAG_WriteIR() Description
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5.10.2.18CORESIGHT_AddAP() Descript
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EMU_ETB_UseETB EMU_ETM_IsPresent EM
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• ARM966ES • ARM968ES • ARM11
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5.10.7.2 In debugger IDE environmen
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5.11.1.1 device This command select
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5.11.1.8 map ram This command shoul
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5.11.1.16 SetSysPowerDownOnIdle Whe
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On the Extra Options page, select U
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5.13 Cache handling Most ARM system
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Chapter 6 Flash download This chapt
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6.2 Licensing No extra license requ
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6.4 Setup for various debuggers (in
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Then J-Link has to be selected as d
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6.4.5 J-Link RDI The configuration
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Save the settings file and restart
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6.6 Using the DLL flash loaders in
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Chapter 7 Flash breakpoints This ch
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7.2 Licensing In order to use the f
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7.4 Setup & compatibility with vari
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Chapter 8 RDI RDI (Remote Debug Int
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8.2 Licensing In order to use the J
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Driver option to RDI. 3. Go to the
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8.3.2 ARM AXD (ARM Developer Suite,
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8.3.3 ARM RVDS (RealView developer
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4. Now select Add DLL to add the JL
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9. Now the RealView Debugger is con
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2. Click Method | New in the Connec
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8.3.5 KEIL MDK (µVision IDE) 8.3.5
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After finishing configuration, the
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8.4.4.1 General tab Connection to J
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Comands in the macro file Command D
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8.4.4.4 Flash tab Enable flash prog
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8.4.4.6 CPU tab Instruction set sim
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8.5 Semihosting Semihosting is a me
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8.5.5 Unexpected / unhandled SWIs W
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Chapter 9 Device specifics This cha
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• Analog ADuC7026x62 • Analog A
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• AT91SAM7XC512 • AT91SAM9XE128
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RDI Sample SetJTAGSpeed(30); // Set
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9.4 Ember J-Link has been tested wi
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9.6 Freescale J-Link has been teste
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} // Check current data flash & EEP
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9.8 Itron J-Link has been tested wi
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9.9.1 Unlocking LM3Sxxx devices If
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9.10.1 LPC ARM7-based devices 9.10.
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9.11 OKI J-Link has been tested wit
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9.13 Samsung J-Link has been tested
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9.14.1 STR91x 9.14.1.1 JTAG setting
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Disabling the hardware watchdog In
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9.15 Texas Instruments J-Link has b
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9.15.6 OMAP3530 Needs a J-Link scri
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Chapter 10 Target interfaces and ad
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PIN SIGNAL TYPE Description 15 RESE
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10.1.2 Pinout for SWD The J-Link an
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10.2 38-pin Mictor JTAG and Trace c
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PIN SIGNAL Description 22 Trace sig
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Parameter Min. Max. Explanation Tsh
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PIN SIGNAL TYPE Description 16 18 2
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10.5 Adapters There are various ada
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Chapter 11 Background information T
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11.1.4 The TAP controller The TAP c
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11.2 Embedded Trace Macrocell (ETM)
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11.2.3.2 Code coverage - Source cod
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11.3 Embedded Trace Buffer (ETB) Th
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11.4.4.3 Flash loader of compiler /
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Use an application (for example JLi
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Chapter 12 Designing the target boa
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12.2 Terminating the trace signal T
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Chapter 13 Support and FAQs This ch
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13.2 Troubleshooting 13.2.1 General
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13.3 Contacting support Before cont
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Chapter 14 Glossary This chapter de
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ID Identifier. IEEE 1149.1 The IEEE
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TDO The electronic signal output fr
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Chapter 15 Literature and reference
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A Adaptive clocking ...............
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J-Link / J-Trace User Guide (UM08001) - SEGGER Microcontroller

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