Hardware Design of Independent Experimental Platform ... - GSE

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scope of application is also different. In the comprehensive comparison of various vendor devices, development software, market conditions, based on the paper selected a price higher than the general chip market applications, that Altera's Cyclone series of EPIC3T144C8, as an experiment to study the main chip board. The logic unit is 2910, 13 internal RAM modules, the maximum available 110 port 104. The chip's versatile strong, affordable, develop a more suitable learning environment software platform. FPGA configuration chip EPCS 1, single-chip capacity of 1M bits, can be powered down to save the data. Download circuit with JT AG and AS modes of two to download in order to achieve online and download the debugging [7]. Software platform uses Altera's Quartus II development environment. Cyclone series FPGA structure as shown in Figure 1. We designed 3.3V and 1.5V DC power supply. The circuit schematic diagram is shown in Figure 3 and Figure 4. 1 -::+e5 vees -- Lf ---.L -=- 3 UI 1085 IN ADJ!GND I I Figure 3. alIT 2 VCC3.3 -- + -=- -'- RI R2 C9 3.3V Power Supply vecs 112 1085 ,--__ ---, VCC1.S C2 VCCIO VCCIO .---J.IN ADJ/GND alIT I--+---"- rl--+---
and will receive the down by the MODEM carrier signal demodulation into a digital data, sent along the receive data line RXD terminal. RI-Ring Indicator, when the MODEM receive the switch signals sent by ringing call to be effective to notify the terminal had to be called. TXD-transmit data through the serial data TXD data lines will be sent to the MODEM, DTE -> DCE. RXD-receive data received through the RXD data line sent from the MODEM serial data, DCE -> DTE. basic structure of Simple programmable logic device is shown in Figure 6. XI --.---------I Xn --..-----1 PI Pd ----1---Z1 « or " array TABLE I. RS232 PIN ASSIGNMENT INSTRUCTIONS L-____ ------_Zm DSR Pin Shorthand Significance Pin 1 DCD carrier detect Pin2 RXD receive Pin3 TXD transmit Pin4 DTR data terminal ready Pin5 GND ground Pin6 DSR data set ready Pin7 RTS request to send Pin8 CTS clear to send Pin9 RI ring indicator 9-pin RS232 interface pins are shown in Figure 5. RTS 0 CTS Rl DCD RXD TXD DTR GND Figure 6. The Basic Structure of Programmable Logic Devices From the figure we can see, assuming that programmable logic device input number n, the output number m, the number of the product items d, Then the device chip area can be expressed as: S = (2n + m) * d. For "and/or" array, the designer can change specific connections of "and/or" array to achieve a different logic functions. Usually, as long as any of an array of connection of "and/or" array changes, then the corresponding programmable logic device functions will change. In the digital circuit, according to different combinations form of "and/or" array in programmable logic devices, a simple programmable logic device is divided into three types: (1) Programmable read-only memory (PROM), which is characterized with fixed "and" array and programmable "or"array; (2) The programmable logic array (PLA), which is characterized with programmable "and/or" array; (3) Programmable array logic (PAL), which is characterized with fixed "or" array and programmable "and"array. V. PROGRAM SAMPLE OF EXPERIMENTAL PLATFORM Figure 5. RS232 Interface Pin Map As the RS232 electrical characteristics and FPGA are different, so the middle to connect an interface chip to complete the RS232 negative TTL logic and FPGA-level conversion between. IV. BASIC STRUCTURE AND CHARACTERISTICS OF PLD Programmable logic device is a new integrated device developed from the 20th century, 70 years, the user can achieve the required logic functions through programming for the device, programmable logic device is a semicustom integrated circuits. Because PLD is of relatively low cost, flexibility, short design cycle, and high reliability, risk, thus has been widely applied, and develop very rapidly [4]. PLD can be divided into simple PLD, EPLD/CPLD, FPGA. Simple PLD including PROM, PLA, PAL and GAL, is characterized by the composition "and" array and "or" array, which can effectively achieve the logic functions with "addition of product" form. According to Boolean algebra knowledge, all of the logic functions may be described using "and/or" expression, so by changing the connection of "or" array and "and" array we can implement different logic functions, a simple combination of PLD is mainly used to achieve the logic function. The Experiment content define an input clock port "clkin", an clock output port "clkout" and 7 keyboard input ports "sound (0-7)", input clock frequency of I.SM, each key pressed corresponds to a sound state ,can input clock frequency of sub-frequency of the corresponding seven different frequencies. Example procedures are as follows: library ieee; use ieee.std _logic _1164.all; use ieee.std _logic _ unsigned. all; entity fs is porte elkin: in std _logic; sound: in std_logic_vector(7 downto 1); elkoutout std_logic); end fs; architecture behave of fs is begin process( elkin) variable count integer range 0 to 3000; begin if (clkin'event and clkin='I') then case sound is when "1111110"=> case count is when 0 to 1433=> 46
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